1. A method for managing a storage device having a plurality of non-volatile memory areas in communication with a controller, the method comprising the controller:
receiving a write command from a host, the write command associated with an amount of data greater than a physical page and less than an integer number of physical pages of the non-volatile memory areas of the storage device;
identifying an unaligned portion of the data, the unaligned portion comprising data not aligned with the physical page of the non-volatile memory areas of the memory;
storing the unaligned portion in a first queue in the storage device; and
storing portions of the data aligned with the physical page of the non-volatile portion of the data in a second queue in the storage device.
2. The method of claim 1, wherein the first queue comprises a separate list of unaligned portions of data for each of the plurality of non-volatile memory areas the processor is configured to write to in parallel and storing the unaligned portion comprises storing the unaligned portion in a list of the first queue associated with the non-volatile memory area to which the unaligned portion of data belongs.
3. The method of claim 1, further comprising writing unaligned portions of data from the first queue in parallel to at least some of the plurality of non-volatile memory areas when the controller detects a timeout condition.
4. The method of claim 3, further comprising writing data from the first queue in parallel to an appropriate one or more of the plurality of non-volatile memory areas, regardless of whether the first queue contains unaligned data for all of the non-volatile memory areas, when an amount of unaligned data in the first queue reaches a predetermined threshold.
5. The method of claim 1, wherein storing the unaligned data in the first queue comprises storing the unaligned data in a RAM cache in the storage device.
6. The method of claim 2, further comprising writing unaligned data from each of the lists, in parallel, to each of the respective plurality of non-volatile memory areas in a first in first out (FIFO) manner.
7. The method of claim 2, wherein the non-volatile memory areas comprise separate banks of flash memory.
8. The method of claim 7, wherein the physical page comprises a metapage spanning one of the plurality of banks of flash memory.
9. A storage device comprising:
a memory having plurality of non-volatile memory areas;
a random access memory (RAM); and
a controller in communication with the memory and the RAM, the controller configured to:
receive a write command from a host, the write command associated with an amount of data greater than a physical page and less than an integer number of physical pages of the non-volatile memory areas;
identify an unaligned portion of the data, the unaligned portion comprising data not aligned with the physical page of the non-volatile memory areas of the memory;
store the unaligned portion in a first queue in the RAM of the storage device; and
store portions of the data aligned with the physical page of the non-volatile memory areas in a second queue in the RAM of the storage device.
10. The storage device of claim 9, wherein the first queue comprises a plurality of lists configured to receive unaligned portions of data for a respective one of the plurality of non-volatile memory areas and the controller is configured to store the unaligned portion in a list of the first queue associated with the non-volatile memory area to which the unaligned portion of data is directed.
11. The storage device of claim 10, wherein the controller is further configured to write unaligned portions of data from the first queue in parallel to each of the plurality of non-volatile memory areas when the first queue contains a threshold amount of unaligned portions of data.
12. The storage device of claim 11, wherein the controller is further configured to write data from the first queue in parallel to an appropriate one or more of the plurality of non-volatile memory areas, regardless of whether the first queue contains unaligned data for all of the non-volatile memory areas, when an amount of unaligned data in the first queue reaches a predetermined threshold.
13. The storage device of claim 9, wherein the RAM comprises a RAM cache in the controller.
14. The storage device of claim 10, wherein the controller is configured to write unaligned data from each of the lists, in parallel, to each of the respective plurality of non-volatile memory areas in a first in first out (FIFO) manner.
15. The storage device of claim 10, wherein the non-volatile memory areas comprise separate banks of flash memory.
16. The storage device of claim 15, wherein the physical page comprises a metapage spanning one of the plurality of banks of flash memory.
17. The storage device of claim 11, wherein the second queue comprises a plurality of lists configured to receive the aligned portions of data for a respective one of the plurality of non-volatile memory areas and the controller is configured to store the aligned portion in a list of the second queue associated with the non-volatile memory area to which the unaligned portion of data is directed.
18. The storage device of claim 17, wherein the controller is further configured to write aligned portions of data from the second queue in parallel to each of the plurality of non-volatile memory areas when the controller detects a timeout condition.
19. The storage device of claim 18, wherein the controller is configured to only write data from one queue at a time for writing data to the plurality of non-volatile memory areas.
20. The storage device of claim 18, wherein the controller is configured to select data from one of the first queue or the second queue to permit parallel writing to each of the plurality of non-volatile storage areas regardless of the order the selected data was received in the first or second queue.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus for controlling a linear compressor having a piston and a valve, comprising:
a voltage detection unit detecting a voltage supplied to the linear compressor;
a current detection unit detecting a current supplied to the linear compressor;
a control unit determining whether a collision of the piston with the valve occurs by comparing output signals of the voltage and current detection units and controlling an amplitude of the piston if the collision of the piston with the valve occurs;
a compressor drive unit controlling the amplitude of the piston under control of the control unit;
a first storage unit storing preset data and a second storage unit storing data reset by the control unit, the second storage unit being a non-volatile memory that allows reading or writing by the control unit to control the amplitude of the piston;
a collision detection unit detecting the collision of the piston with the valve in accordance with the output signals of the voltage detection unit and the current detection unit; and
an amplitude calculation unit calculating the amplitude of the piston using an output signal of the collision detection unit and providing the control unit with the calculated amplitude of the piston.
2. An apparatus for controlling a linear compressor having a piston and a valve comprising:
a voltage detection unit detecting a voltage supplied to the linear compressor;
a current detection unit detecting a current supplied to the linear compressor;
a control unit determining whether a collision of the piston with the valve occurs by comparing output signals of the voltage and current detection units and controlling an amplitude of the piston if the collision of the piston with the valve occurs;
a conduction angle setting unit setting a maximum conduction angle of the linear compressor according to the voltage supplied to the linear compressor; and
a conduction angle adjustment unit adjusting a conduction angle set by said conduction angle setting unit according to an operation pattern and a consumed current of the linear compressor.
3. The apparatus according to claim 1, wherein if the collision is determined the control unit controls the amplitude of the piston differently than if the collision is not determined.