1. An electrical system comprising:
a plurality of variable loads;
an electrical power generator that provides power to the variable loads via an output terminal;
a plurality of system sensors that sense a plurality of generator parameters related to the operation of the generator, the generator parameters including a voltage at the output terminal of the generator and a current drawn from the output terminal of the generator;
a generator controller that is coupled to the plurality of system sensors for receipt of data indicative of the plurality of generator parameters and that determines therefrom a present generator output power proxy and a generator power capacity; and
at least one load controller that is communicably coupled to the generator controller for receipt of data indicative of the present generator output power proxy and the generator power capacity and that controls a power consumption of at least one of the variable loads as a function the present generator output power proxy and the generator power capacity.
2. The electrical system of claim 1 wherein the generator parameters further comprise at least one parameter selected from the group consisting of ambient temperature, stator temperature, rotor temperature, rotor speed, and output signal frequency.
3. The electrical system of claim 1 wherein the generator parameters further comprise an amount of time the generator has been caused to operate outside of its rated continuous capacity.
4. The electrical system of claim 1 wherein the at least one load controller comprises a plurality of load controllers communicably coupled to each other and to the generator controller via a communications network.
5. The electrical system of claim 4 wherein each load controller evaluates a performance set point of its load, a measured performance of its load, a present power consumed proxy of its load, a power consumption capacity of its load, the present generator output power proxy, and the generator power capacity in determining the power consumption of its load.
6. The electrical system of claim 5 wherein each load controller communicates the present power consumption of its load and the power consumption capacity of its load to both the other load controllers and the generator controller via the communications network.
7. The electrical system of claim 4 wherein the generator controller is responsive to a request from one of the load controllers to adjust the output voltage of the generator.
8. The electrical system of claim 4 wherein the load controllers have priority values associated therewith for determining an order in which the load controllers determine the power consumption of their load.
9. The electrical system of claim 1 and further comprising:
a prime mover that provides a rotational energy to the generator for conversion by the generator into electrical power; and
a prime mover controller that controls a rotation of the prime mover and that is communicably coupled to the generator controller via a communications network, wherein the generator controller is responsive to requests from the prime mover controller to adjust a power generation load of the generator on the prime mover.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A bipolar transistor comprising:
a conductive back electrode for receiving a bias voltage;
a second buried insulating layer located over said conductive back electrode having a second thickness;
a first buried insulating layer located adjacent to said second buried insulating layer and said conductive back electrode, said first buried insulating layer having a first thickness that is greater than the second thickness;
a first semiconductor layer located predominately over said second buried insulating layer, said first semiconductor layer including a first conductive type dopant, wherein said conductive back electrode is biased to form an accumulation layer in said first semiconductor layer at an interface between said first semiconductor layer and said second buried insulating layer;
a base located atop at least said first semiconductor layer, said base comprising a second semiconductor layer having a second conductivity type dopant that differs from the first conductivity type dopant; and
an emitter comprising a third semiconductor layer of the first conductivity type dopant located over a portion of said base.
2. The bipolar transistor of claim 1 wherein an outer portion of said base over a first insulator which is not protected by a second insulator is exposed.
3. The bipolar transistor of claim 2 wherein the outer exposed portion of the base, the emitter, the first semiconductor layer and exposed surfaces of the conductive back electrode each include a silicide.
4. The bipolar transistor of claim 3 wherein the silicide is in contact with a metal contact that is located atop the silicide inside a contact opening formed in an interconnect dielectric.
5. The bipolar transistor of claim 1 wherein the emitter comprises a single-finger.
6. The bipolar transistor of claim 1 wherein said first semiconductor layer comprises an extrinsic collector and an intrinsic collector, said extrinsic collector is more heavily doped with said first conductivity type dopant than the intrinsic collector.
7. The bipolar transistor of claim 1 wherein said second buried insulating layer is a thin insulating layer having a thickness from about 1 to about 15 nm.
8. The bipolar transistor of claim 1 wherein said first buried insulating layer has a thickness from about 100 to about 1000 nm.
9. The bipolar transistor of claim 1 wherein the base contains a p-type dopant, the emitter contains an n-type dopant, and the first semiconductor layer comprises an n-type dopant.
10. The bipolar transistor of claim 1 wherein the base contains an n-type dopant, the emitter contains a p-type dopant, and the first semiconductor layer comprises a p-type dopant.
11. An integrated semiconductor structure comprising
a bipolar transistor including a conductive back electrode for receiving a bias voltage, a second buried insulating layer located over said conductive back electrode having a second thickness, a first buried insulating layer located adjacent to said second buried insulating layer and said conductive back electrode, said first buried insulating layer having a first thickness that is greater than the second thickness, a first semiconductor layer located predominately over said second buried insulating layer, said first semiconductor layer including a first conductive type dopant, wherein said conductive back electrode is biased to form an accumulation layer in said first semiconductor layer at an interface between said first semiconductor layer and said second buried insulating layer, a base located atop at least said first semiconductor layer, said base comprising a second semiconductor layer having a second conductivity type dopant that differs from the first conductivity type dopant, and an emitter comprising a third semiconductor layer of the first conductivity type dopant located over a portion of said base; and
at least one adjacent complementary metal oxide semiconductor device.
12. The integrated semiconductor structure of claim 11 wherein the complementary metal oxide semiconductor device is a field effect transistor.
13. The integrated semiconductor structure of claim 12 wherein said field effect transistor is a back gate field effect transistor.
14. The integrated semiconductor structure of claim 13 wherein said back gate field effect transistor comprises a conductive back electrode for receiving a bias voltage; a second buried insulating layer located over said conductive back electrode having a second thickness; a first buried insulating layer located adjacent to said second buried insulating layer and said conductive back electrode, said first buried insulating layer having a first thickness that is greater than the second thickness; a first semiconductor layer located predominately over said second buried insulating layer; and at least a gate dielectric and a gate conductor located atop the first semiconductor layer.