1. An image transmission apparatus, comprising:
a difference image specifying unit for specifying a difference image indicating a difference between an image before changing and an image after changing;
a pattern determination unit for determining a pattern for optimizing compression coding of the difference image and transmission of the compression-coded difference image from among one or more box pattern including the difference image;
a compression coding unit for performing compression coding of the difference image using each of boxes constituting the pattern determined by the pattern determination unit as a unit of compression coding; and
a transmitting unit for transmitting the compression-coded difference image.
2. The image transmission apparatus of claim 1, further comprising
a change instruction unit for accepting an instruction on a change from a current output of an image before changing by an image output apparatus to an output of a image after changing desirably,
wherein the difference image specifying unit specifies the difference image indicating the difference between the image before changing currently output by the image output apparatus and the image after changing desirably, and
the transmitting unit transmits the compression-coded difference image to the image output apparatus.
3. The image transmission apparatus of claim 2, wherein
the transmitting unit transmits position information of the difference image to the image output apparatus.
4. An image output apparatus, comprising:
a receiver unit for receiving the difference image and position information of the difference image from the image transmission apparatus according to claim 3;
an output unit for outputting an image;
an expansion unit for decoding and expanding the difference image; and
a controller unit for controlling the output unit so as to substitute a part indicated by the position information of the difference image in the image before changing with the decoded and expanded difference image and to output the image.
5. An image transmission method to be performed by one or more computer, comprising:
specifying a difference image indicating a difference between an image before changing and an image after changing;
determining a pattern for optimizing compression coding of the difference image and transmission of the compression-coded difference image from among one or more box pattern including the difference image;
performing compression coding of the difference image using each of boxes constituting the determined pattern as a unit of compression coding; and
transmitting the compression-coded difference image.
6. A non-transitory recording medium on which a program for causing a computer to execute an image transmission is non-transitorily recorded, the program comprising computer-executable instructions of:
specifying a difference image indicating a difference between an image before changing and an image after changing;
determining a pattern for optimizing compression coding of the difference image and transmission of the compression-coded difference image from among one or more box pattern including the difference image;
performing compression coding of the difference image using each of boxes constituting the determined pattern as a unit of compression coding; and
transmitting the compression-coded difference image.
7. An image transmission system, comprising:
a difference image specifying unit for specifying a difference image indicating a difference between an image before changing and an image after changing;
a pattern determination unit for determining a pattern for optimizing compression coding of the difference image and transmission of the compression-coded difference image from among one or more box pattern including the difference image;
a compression coding unit for performing compression coding of the difference image using each of boxes constituting the pattern determined by the pattern determination unit as a unit of compression coding;
a transmitting unit for transmitting the compression-coded difference image;
a receiver unit for receiving the difference image and position information of the difference image;
an output unit for outputting an image;
an expansion unit for decoding and expanding the difference image; and
a controller unit for substituting a part indicated by the position information of the difference image in the image before changing with the decoded and expanded difference image and outputting the image to the output unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory read method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of memory cells, a plurality of word lines and a plurality of bit lines, each of the memory cells electrically connected to one of the word lines and one of the bit lines, each of the memory cells stores at least one bit data, each of the bit data is identified as a first state or a second state according to a voltage, and the memory cells constitute a plurality of physical pages, the memory read method comprising:
applying a test voltage to a first word line among the word lines to read a plurality of verification bit data, wherein a threshold voltage set is set with a first read voltage value set and assigned to the first word line;
calculating a variation of bit data identified as the first state among the verification bit data;
obtaining a second read voltage value set according to the variation;
updating the threshold voltage set with the second read voltage value set; and
using the threshold voltage set updated with the second read voltage value set to read data from a first physical page among the physical pages, wherein memory cells constituting the first physical page among the memory cells are electrically connected to the first word line.
2. The data reading method according to claim 1, further comprising:
programming test data into the memory cells connected by the first word line and applying the test voltage to the first word line to read a plurality of initial verification bit data; and
calculating an amount of bit data identified as the first state among the initial verification bit data.
3. The data reading method according to claim 2, wherein the step of calculating the variation of bit data identified as the first state among the verification bit data comprises:
calculating an amount of bit data identified as the first state among the verification bit data; and
obtaining the variation by subtracting the amount of bit data identified as the first state among the initial verification bit data from the amount of bit data identified as the first state among the verification bit data.
4. The data reading method according to claim 1, further comprising:
determining whether an amount of error bits occurring in data read from the first physical page by using the threshold voltage set updated with the second read voltage value set is larger than a predetermined threshold;
using a margin to adjust the second read voltage value set to generate a third read voltage value set and updating the threshold voltage set with the third read voltage value set if the amount of error bits occurring in the data read from the first physical page by using the threshold voltage set updated with the second read voltage value set is larger than the predetermined threshold; and
performing a retry read on the first physical page by using the threshold voltage set updated with the third read voltage value set.
5. The data reading method according to claim 1, wherein the first read voltage value set includes a plurality of read voltage values and a value of the test voltage is equal to a maximum read voltage value among the read voltage values or between the maximum read voltage value and a second largest read voltage value among the read voltage values.
6. The data reading method according to claim 1, further comprising:
reading data from the first physical page by using the threshold voltage set with the first read voltage value set;
determining whether an amount of error bits occurring in the data read from the first physical page by using the threshold voltage set with the first read voltage value set is larger than a predetermined threshold;
wherein the step of applying the test voltage to the first word line to read the plurality of verification bit data is performed if the amount of error bits occurring in the data read from the first physical page by using the threshold voltage set with the first read voltage value set is larger than the predetermined threshold.
7. The data reading method according to claim 1, further comprising:
determining whether an erase count of the rewritable non-volatile memory module is larger than an erase count threshold,
wherein the step of applying the test voltage to the first word line to read the plurality of verification bit data is performed if the erase count of the rewritable non-volatile memory module is larger than the erase count threshold.
8. The data reading method according to claim 1, wherein the step of obtaining the second read voltage value set according to the variation comprises:
looking up a read voltage corresponding table according to the variation to obtain the second read voltage value set.
9. A memory controller for reading data from a plurality of memory cells of a rewritable non-volatile memory module, the control comprising:
an interface configured to electrically connected to the memory cells, a plurality of word lines and a plurality of bit lines, wherein each of the memory cells electrically connected to one of the word lines and one of the bit lines, each of the memory cells stores at least one bit data, each of the bit data is identified as a first state or a second state according to a voltage and the memory cells constitute a plurality of physical pages; and
a memory management circuit coupled to the interface and configured to apply a test voltage to a first word line among the word lines to read a plurality of verification bit data, wherein the memory management circuit set a first read voltage value set as a threshold voltage set for the first word line,
wherein the memory management circuit is further configured to calculate a variation of bit data identified as the first state among the verification bit data and obtain a second read voltage value set based on the variation,
wherein the memory management circuit is further configured to update the threshold voltage set with the second read voltage value set and read data from a first physical page among the physical pages by using the threshold voltage set updated with the second read voltage value set, wherein memory cells constituting the first physical page among the memory cells are electrically connected to the first word line.
10. The control circuit according to claim 9, wherein the memory management circuit is further configured to program test data into the memory cells connected by the first word line and apply the test voltage to the first word line to read a plurality of initial verification bit data,
wherein the memory management circuit is further configured to calculate an amount of bit data identified as the first state among the initial verification bit data.
11. The control circuit according to claim 10, wherein in the operation of calculating the variation of bit data identified as the first state among the verification bit data, the memory management circuit calculates an amount of bit data identified as the first state among the verification bit data and obtains the variation by subtracting the amount of bit data identified as the first state among the initial verification bit data from the amount of bit data identified as the first state among the verification bit data.
12. The control circuit according to claim 9, wherein the memory management circuit is further configured to determine whether an amount of error bits occurring in data read from the first physical page by using the threshold voltage set updated with the second read voltage value set is larger than a predetermined threshold,
if the amount of error bits occurring in the data read from the first physical page by using the threshold voltage set updated with the second read voltage value set is larger than the predetermined threshold, the memory management circuit uses a margin to adjust the second read voltage value set to generate a third read voltage value set, updates the threshold voltage set with the third read voltage value set and performs a retry read on the first physical page by using the threshold voltage set updated with the third read voltage value set.
13. The control circuit according to claim 9, wherein the first read voltage value set includes a plurality of read voltage values, and a value of the test voltage is equal to a maximum read voltage value among the read voltage values or between the maximum read voltage value and a second largest read voltage value among the read voltage values.
14. The control circuit according to claim 9, wherein the memory management circuit is further configured to read data from the first physical page by using the threshold voltage set with the first read voltage value set and determine whether an amount of error bits occurring in the data read from the first physical page by using the threshold voltage set with the first read voltage value set is larger than a predetermined threshold,
wherein the memory management circuit applies the test voltage to the first word line to read the plurality of verification bit data if the amount of error bits occurring in the data read from the first physical page by using the threshold voltage set with the first read voltage value set is larger than the predetermined threshold.
15. The control circuit according to claim 9, wherein the memory management circuit is further configured to determine whether an erase count of the rewritable non-volatile memory module is larger than an erase count threshold,
wherein the memory management circuit applies the test voltage to the first word line to read the plurality of verification bit data if the erase count of the rewritable non-volatile memory module is larger than the erase count threshold.
16. The control circuit according to claim 9, wherein in the operation of obtaining the second read voltage value set according to the variation, the memory management circuit looks up a read voltage corresponding table according to the variation to obtain the second read voltage value set.
17. A memory storage apparatus, comprising:
a connector configured to couple to a host system;
a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of memory cells, a plurality of word lines and a plurality of bit lines, each of the memory cells electrically connected to one of the word lines and one of the bit lines, each of the memory cells stores at least one bit data, each of the bit data is identified as a first state or a second state according to a voltage and the memory cells constitute a plurality of physical pages; and
a memory controller coupled to the connector and the rewritable non-volatile memory module, wherein the memory controller is configured to apply a test voltage to a first word line among the word lines to read a plurality of verification bit data, wherein the memory controller sets a first read voltage value set as a threshold voltage set for the first word line,
wherein the memory controller is further configured to calculate a variation of bit data identified as the first state among the verification bit data and obtain a second read voltage value set based on the variation,
wherein the memory controller is further configured to update the threshold voltage set with the second read voltage value set and read data from a first physical page among the physical pages by using the threshold voltage set updated with the second read voltage value set, wherein memory cells constituting the first physical page among the memory cells are electrically connected to the first word line.
18. The memory storage apparatus according to claim 17, wherein the memory controller is further configured to program test data into the memory cells connected by the first word line and apply the test voltage to the first word line to read a plurality of initial verification bit data,
wherein the memory controller is further configured to calculate an amount of bit data identified as the first state among the initial verification bit data.
19. The memory storage apparatus according to claim 18, wherein in the operation of calculating the variation of bit data identified as the first state among the verification bit data, the memory controller calculates an amount of bit data identified as the first state among the verification bit data and obtains the variation by subtracting the amount of bit data identified as the first state among the initial verification bit data from the amount of bit data identified as the first state among the verification bit data.
20. The memory storage apparatus according to claim 17, wherein the memory controller is further configured to determine whether an amount of error bits occurring in data read from the first physical page by using the threshold voltage set updated with the second read voltage value set is larger than a predetermined threshold,
if the amount of error bits occurring in the data read from the first physical page by using the threshold voltage set updated with the second read voltage value set is larger than the predetermined threshold, the memory controller uses a margin to adjust the second read voltage value set to generate a third read voltage value set, updates the threshold voltage set with the third read voltage value set and performs a retry read on the first physical page by using the threshold voltage set updated with the third read voltage value set.
21. The memory storage apparatus according to claim 17, wherein the first read voltage value set includes a plurality of read voltage values, and a value of the test voltage is equal to a maximum read voltage value among the read voltage values or between the maximum read voltage value and a second largest read voltage value among the read voltage values.
22. The memory storage apparatus according to claim 17, wherein the memory controller is further configured to read data from the first physical page by using the threshold voltage set with the first read voltage value set and determine whether an amount of error bits occurring in the data read from the first physical page by using the threshold voltage set with the first read voltage value set is larger than a predetermined threshold,
wherein the memory controller applies the test voltage to the first word line to read the plurality of verification bit data if the amount of error bits occurring in the data read from the first physical page by using the threshold voltage set with the first read voltage value set is larger than the predetermined threshold.
23. The memory storage apparatus according to claim 17, wherein the memory controller is further configured to determine whether an erase count of the rewritable non-volatile memory module is larger than an erase count threshold,
wherein the memory controller applies the test voltage to the first word line to read the plurality of verification bit data if the erase count of the rewritable non-volatile memory module is larger than the erase count threshold.
24. The memory storage apparatus according to claim 17, wherein in the operation of obtaining the second read voltage value set according to the variation, the memory controller looks up a read voltage corresponding table according to the variation to obtain the second read voltage value set.
25. A memory module, comprising:
a plurality of word lines;
a plurality of bit lines;
a plurality of memory cells, wherein each of the memory cells electrically connected to one of the word lines and one of the bit lines, each of the memory cells stores at least one bit data, each of the bit data is identified as a first state or a second state according to a voltage and the memory cells constitute a plurality of physical pages; and
a control circuit coupled to the word lines, the bit lines and the memory cells, wherein the control circuit is configured to apply a test voltage to a first word line among the word lines to read a plurality of verification bit data, wherein the control circuit sets a first read voltage value set as a threshold voltage set for the first word line,
wherein the control circuit is further configured to calculate a variation of bit data identified as the first state among the verification bit data and obtain a second read voltage value set based on the variation,
wherein the control circuit is further configured to update the threshold voltage set with the second read voltage value set and read data from a first physical page among the physical pages by using the threshold voltage set updated with the second read voltage value set, wherein memory cells constituting the first physical page among the memory cells are electrically connected to the first word line.