1. A semiconductor memory device comprising:
a first and a second signal line forming a pair of signal lines;
a third and a fourth signal line forming another pair of signal lines;
a memory cell connected to the first and second signal lines; and
a sense amplifier circuit provided between the first and second signal lines and the third and fourth signal lines,
wherein
the sense amplifier circuit includes
a first transistor of a first conductivity type having a gate connected to a precharge signal, a source connected to a first power supply potential, and a drain connected to the first signal line,
a second transistor of the first conductivity type having a gate connected to the precharge signal, a source connected to the first power supply potential, and a drain connected to the second signal line,
a third transistor of the first conductivity type having a gate connected to the first signal line, a source connected to the first power supply potential, and a drain connected to the third signal line,
a fourth transistor of the first conductivity type having a gate connected to the second signal line, a source connected to the first power supply potential, and a drain connected to the fourth signal line,
a fifth transistor of a second conductivity type having a gate connected to the third signal line, a source connected to a second power supply potential, and a drain connected to the first signal line, and
a sixth transistor of the second conductivity type having a gate connected to the fourth signal line, a source connected to the second power supply potential, and a drain connected to the second signal line.
2. The semiconductor memory device of claim 1, wherein
the first and second signal lines are local bit lines,
the third and fourth signal lines are global bit lines,
the local and global bit lines form a hierarchical bit line architecture.
3. The semiconductor memory device of claim 1, wherein the memory cell includes
a first cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to a first memory node, and a gate connected to a second memory node,
a second cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,
a third cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the first memory node, and a gate connected to the second memory node,
a fourth cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,
a fifth cell transistor of the second conductivity type having a source connected to the first memory node, a drain connected to the first signal line, and a gate connected to a word line, and
a sixth cell transistor of the second conductivity type having a source connected to the second memory node, a drain connected to the second signal line, and a gate connected to the word line.
4. The semiconductor memory device of claim 1, wherein the memory cell includes
a first cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to a first memory node, and a gate connected to a second memory node,
a second cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,
a third cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the first memory node, and a gate connected to the second memory node,
a fourth cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,
a fifth cell transistor of the second conductivity type having a source connected to the first memory node, a drain connected to the first signal line, and a gate connected to a first word line, and
a sixth cell transistor of the second conductivity type having a source connected to the second memory node, a drain connected to the second signal line, and a gate connected to a second word line different from the first word line.
5. The semiconductor memory device of claim 1, wherein the sense amplifier circuit further includes
a seventh transistor of the second conductivity type having a drain connected to the sources of the fifth and sixth transistors, a source connected to the second power supply potential, and a gate connected to a control signal derived from a column selection signal.
6. The semiconductor memory device of claim 1, wherein
the potential value of the second power supply potential connected to the sources of the fifth and sixth transistors is controlled based on a control signal derived from a column selection signal.
7. A semiconductor memory device comprising:
memory cells;
bit lines each connected to corresponding ones of the memory cells; and
sense amplifier circuits each connected to corresponding ones of the bit lines,
wherein
each of the sense amplifier circuits has a single-end configuration and a function of writing data read from a corresponding one of the memory cells back to the corresponding bit lines, and achieves data write operation to a corresponding one of the memory cells by the function of writing data back to the corresponding bit lines.
8. The semiconductor memory device of claim 7, wherein
the bit lines have a hierarchical architecture divided in memory cell arrays.
9. The semiconductor memory device of claim 7, wherein
the function of writing data back to the bit line is a function of writing back one of high data and low data.
10. The semiconductor memory device of claim 7, wherein
each of the sense amplifier circuits is provided between separated memory cell arrays.
11. The semiconductor memory device of claim 10, wherein
two of the sense amplifier circuits connected to two separated ones of the bit lines are arranged adjacent to each other.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. An apical foramen locator comprising:
a power circuit operable to generate a stimulus voltage across two electrodes and across a reference resistor connected to one of the electrodes;
an impedance-sensing circuit operable to sense the stimulus voltage, a first voltage across the two electrodes and a second voltage across the reference resistor;
at least one impedance map including apical foramen location data corresponding to a combination of a first voltage index and a second voltage index wherein the apical foramen location data is generated from reference teeth;
a processing component including a memory storing the at least one impedance map and a microprocessor that is operable to derive the first and second voltage indices from the voltages sensed by the impedance-sensing circuit and to select from the impedance map apical foramen location data that corresponds to the first and second voltage indices; and
a display operable to present the selected apical foramen location data.
2. The locator of claim 1 wherein the stimulus voltage has a single frequency.
3. The locator of claim 1 wherein the stimulus voltage includes a voltage having a waveform and a frequency.
4. The locator of claim 1 wherein the power circuit includes a filter operable to modify the stimulus voltage before the impedance-sensing circuit senses the stimulus voltage.
5. The locator of claim 4 wherein the filter is operable to modify the stimulus voltage to include a 100 mV peak-to-peak sine wave at 30 KHz.
6. The locator of claim 1 wherein one of the electrodes includes a lip clip and the other electrode is connected to a file.
7. The locator of claim 1 wherein the impedance sensing circuit includes an amplifier operable to amplify at least one of the following voltages, the stimulus voltage, the first voltage and the second voltage.
8. The locator of claim 1 wherein the processing component includes an analogue-to-digital converter operable to generate digital data from each of the respective stimulus, first and second voltages.
9. The locator of claim 1 wherein the apical foramen location data represents the location of a tip of a tool relative to a patient’s apical foramen.
10. The locator of claim 1 wherein:
the first voltage index is derived from the stimulus voltage and the first voltage; and
the second voltage index is derived from the stimulus voltage and the second voltage.
11. The locator of claim 10 wherein:
the first voltage index includes a ratio of the stimulus voltage to the first voltage and
the second voltage index includes a ratio of the stimulus voltage to the second voltage.
12. The locator of claim 1 wherein:
one of the electrodes is connected to a tool inserted into the a root canal of a patient’s tooth; and
the display includes at least one of the following:
a visual display that indicates the location of a tip of the tool relative to the patient’s apical foramen; and
an aural display that includes sounds to indicate the location of a tip of the tool relative to the patient’s apical foramen.
13. The locator of claim 1 further comprising a mode button operable to select an impedance map that the processing component uses to select apical foramen location data.
14. A method for locating an apical foramen of a patient’s tooth, comprising:
applying a stimulus voltage across two electrodes and a reference resistor, wherein one electrode contacts a tool inserted into the root canal of the patient and the other electrode contacts another region of the patient;
sensing the stimulus voltage, a first voltage across the two electrodes and a second voltage across the reference resistor; and
deriving a first and second voltage index from the stimulus, first and second voltages; and
selecting from an impedance map apical foramen location data that corresponds to the combination of the first and second voltage indices.
15. The method of claim 14 wherein another region of the patient includes the lip of the patient.
16. The method of claim 14 wherein:
deriving the first voltage index includes deriving a ratio between the stimulus and first voltages; and
deriving the second voltage index includes deriving a ratio between the stimulus and second voltages.
17. The method of claim 14 further comprising displaying the selected apical foramen location data.
18. The method of claim 17 wherein displaying the selected apical foramen data includes at least one of the following:
presenting at least one of the following: text and images;
turning on a light; and
providing a sound.
19. The method of claim 14 further comprising:
moving the tool toward the apical foramen of the patient’s tooth; and
reading the stimulus voltage, the first voltage and the second voltage as the tool is moved.
20. The method of claim 14 further comprising selecting an impedance map.
21. The method of claim 14 further comprising selecting an impedance map generated by reference teeth having at least one of the following, the same or substantially the same physical geometry as the patient’s tooth and the same or substantially the same abnormality as the patient’s tooth.
22. The method of claim 21 wherein selecting an impedance map includes comparing at least one of the following characteristics of a patient’s tooth, physical geometry and abnormality, to a respective characteristic of the reference teeth used to generate the impedance map.
23. The method of claim 14 further comprising:
inserting a tool into a root canal of the patient’s tooth; and
contacting the tool with an electrode.
24. An impedance map generated from reference teeth for use with an apical foramen locator, comprising:
first voltage indices;
second voltage indices; and
apical foramen location data corresponding to a combination of one of the first and one of the second voltage indices.
25. The map of claim 24 wherein the reference teeth include at least one of the following teeth: molars, bicuspids, cuspids and incisors.
26. The map of claim 24 wherein the reference teeth are normal.
27. The map of claim 24 wherein the reference teeth include at least one of the following abnormalities, at least one accessory canal, at least one lateral canal, at least one filling, tooth decay and an absence of an apical constriction.
28. The method of claim 24 wherein the reference teeth include the same or substantially the same physical geometry.
29. A method for generating an impedance map from reference teeth for use with an apical foramen locator, comprising:
applying a voltage across two electrodes and a reference resistor, wherein one electrode contacts a tool inserted into the root canal of one of the reference teeth and the other electrode contacts a surface of the same reference tooth;
sensing the voltage across the two electrodes and the reference resistor; recording voltage indices derived from the applied voltage and the sensed voltages;
recording the distance between the tool inserted into the root canal and the tooth’s apical foramen;
moving the inserted tool toward the reference tooth’s apical foramen; and repeating the acts.
30. The method of claim 29 further comprising repeating the process using another one of the reference teeth.