1. A communication device comprising an input device to operate said communication device, a microphone to input audio data to said communication device, a speaker to output audio data from said communication device, a display to display a plurality of images, a wireless communication system which sends and receives wireless signals, a voice communication mode implementor, and a multiple & simultaneous speech-to-text mode implementor, wherein said voice communication mode implementor transfers a 1st voice data which indicates a 1st voice input from said microphone via said wireless communication system and outputs a 2nd voice indicated by a 2nd voice data received via said wireless communication system from said speaker,
said multiple & simultaneous speech-to-text mode implementor includes a 1st speech-to-text mode implementor and a 2nd speech-to-text mode implementor, wherein said 1st speech-to-text mode implementor converts said 1st voice data to a 1st text data and said 2nd speech-to-text mode implementor converts said 2nd voice data to a 2nd text data, wherein the conversions implemented by said 1st speech-to-text mode implementor and said 2nd speech-to-text mode implementor are performed simultaneously, and
said 1st text data and said 2nd text data are displayed on said display, wherein said 1st text data includes alphanumeric data indicated by said 1st voice and said 2nd text data includes alphanumeric data indicated by said 2nd voice.
2. The communication device of claim 1, wherein said 1st text data is displayed with a 1st color and said 2nd text data is displayed with a 2nd color on said display.
3. The communication device of claim 1, wherein said 1st text data is displayed with a 1st font and said 2nd text data is displayed with a 2nd font on said display.
4. The communication device of claim 1, wherein a 1st tag and a 2nd tag are displayed on said display, wherein said 1st tag is an identifier of said 1st text data and said 2nd tag is an identifier of said 2nd text data.
5. The communication device of claim 1, wherein a 1st tag and a 2nd tag are displayed on said display, wherein said 1st tag is an identifier of said 1st text data and said 2nd tag is an identifier of said 2nd text data, wherein said 2nd tag indicates a name of a person.
6. The communication device of claim 1, wherein a 1st tag is displayed adjacent to said 1st text data and a 2nd tag is displayed adjacent to said 2nd text data, wherein said 1st tag indicates a caller and said 2nd tag indicates a callee.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor substructure comprising:
a substrate;
a gate structure, wherein said gate structure is formed over said substrate;
a spacer formed adjacent to a sidewall of said gate structure; and
a sourcedrain structure disposed adjacent said gate structure, said sourcedrain structure formed of a strain material and disposed in a recess that extends below an upper surface of said substrate,
wherein a portion of said recess underlies the gate structure, and
wherein an interface between said spacer and said source-drain structure located under said spacer is above a lower surface of said gate structure.
2. The semiconductor substructure as in claim 1, wherein said semiconductor substructure comprises a PMOS transistor.
3. The semiconductor substructure as in claim 1, wherein said strain material comprises SiGe.
4. The semiconductor substructure as in claim 1, wherein said substrate comprises crystalline silicon.
5. The semiconductor substructure as in claim 1, further comprising a P-type dopant impurity region in said source-drain structure, said gate structure, or both.
6. The semiconductor substructure as in claim 1, wherein said gate structure comprises a gate electrode over a gate dielectric.
7. The semiconductor substructure as in claim 6, wherein said spacer contacts said gate electrode.
8. The semiconductor substructure as in claim 6, further comprising at least one nitride layer between said spacer and said gate electrode.
9. The semiconductor substructure as in claim 1, wherein said gate structure comprises a high dielectric (\u03ba) metal gate (HKMG) structure.
10. The semiconductor substructure as in claim 9, wherein said spacer contacts said gate electrode.
11. The semiconductor substructure as in claim 9, further comprising at least one nitride layer between said spacer and said gate electrode.
12. A semiconductor substructure comprising:
a substrate;
a gate structure comprising a gate insulating layer over said substrate, and a gate electrode over the gate insulating layer (8);
a spacer formed adjacent to a sidewall of said gate electrode; and
a sourcedrain structure disposed adjacent said gate structure, said sourcedrain structure formed of a strain material and disposed in a recess that extends below an upper surface of said substrate,
wherein a portion of said recess underlies the gate structure, and
wherein said spacer directly contacts the sourcedrain structure above a lower surface of said gate insulating layer.
13. A semiconductor substructure as in claim 12, wherein the spacer directly contacts the sourcedrain structure at least 1 nm above said lower surface of said gate insulating layer.
14. A semiconductor substructure as in claim 12, wherein the spacer directly contacts the sourcedrain structure at least 2 nm above said lower surface of said gate insulating layer.
15. A method for forming a semiconductor substructure, said method comprising:
forming a gate structure over a semiconductor substrate, wherein said gate structure comprises a gate electrode over a gate insulating layer;
forming an insertion layer over said semiconductor substrate;
forming a spacer along a sidewall of said gate structure;
creating a recess extending into said semiconductor substrate, adjacent said gate structure;
removing at least a portion of said insertion layer under said spacer; and
filling said recess with a strain material, said strain material directly contacting a bottom surface of the spacer above a lower surface of said gate insulating layer.
16. The method as in claim 15, wherein said creating recesses comprises anisotropic etching where said recesses extend under said spacer.
17. The method as in claim 15, wherein said insertion layer comprises an oxide and said spacer comprises a nitride.
18. The method as in claim 15, further comprising,
replacing said gate structure with a high dielectric (K), metal gate.
19. The method as in claim 15, further comprising:
forming a nitride layer along said sidewall of said gate structure prior to said step of forming said spacer.
20. The semiconductor substructure as in claim 1, wherein the portion of the recess that underlies the gate structure underlies a gate structure selected from the group consisting of a gate electrode, a gate dielectric, and a high dielectric (\u03ba) metal gate (HKMG) structure.