1. A computer system comprising:
a processor;
a first bus coupled to the processor;
a memory controller coupled to the first bus;
a memory coupled to the memory controller;
a first inputoutput (IO) controller coupled to the first bus; and
a test module coupled to the first IO controller;
wherein the test module is configured to cause tests to be performed on the memory using the first bus.
2. The computer system of claim 1 further comprising:
an operating system;
wherein the processor is configured to cause the operating system to be booted, and wherein the test module is configured to cause the tests to be performed on the memory using the first bus subsequent to the operating system being booted.
3. The computer system of claim 1 further comprising:
an operating system;
wherein the processor is configured to cause the operating system to be executed, and wherein the test module is configured to cause the tests to be performed on the memory using the first bus during execution of the operating system.
4. The computer system of claim 1 wherein the first bus comprises a system bus.
5. The computer system of claim 1 further comprising:
a second IO controller coupled to the first bus;
a second bus coupled to the second IO controller; and
a device coupled to the second bus.
6. The computer system of claim 1 wherein the test module is configured to cause tests to be performed on the memory using the first bus by providing read and write transactions to the first IO controller.
7. The computer system of claim 6 wherein the read and write transactions comprise direct memory access (DMA) transactions.
8. The computer system of claim 1 further comprising:
a bus bridge coupled to the first bus and the first IO controller.
9. A method performed by a computer system that includes a memory comprising:
selecting a portion of the memory for testing during operation of the computer system;
generating a test transaction in a test module coupled to an inputoutput (IO) controller; and
providing the test transaction to the portion using direct memory access (DMA).
10. The method of claim 9 further comprising:
detecting an error that occurs in response to the test transaction; and
performing a remedial action in response to detecting the error.
11. The method of claim 9 further comprising:
providing the test transaction from the test module to the IO controller;
providing the test transaction from the IO controller to a bus bridge;
providing the test transaction from the bus bridge to a system bus;
providing the test transaction from the system bus to a memory controller; and
providing the test transaction from the memory controller to the portion.
12. The method of claim 11 further comprising:
storing information in the memory in response to the test transaction being a write transaction.
13. The method of claim 11 further comprising:
in response to the test transaction being a read transaction:
providing information associated with the test transaction from the portion to the memory controller;
providing the information from the memory controller to the system bus;
providing the information from the system bus to the bus bridge;
providing the information from the bus bridge to the IO controller; and
providing the information from the IO controller to the test module.
14. The method of claim 9 further comprising:
providing the test transaction from the test module to the IO controller;
providing the test transaction from the IO controller to a system controller;
providing the test transaction from the system controller to a memory controller; and
providing the test transaction from the memory controller to the portion.
15. A computer system comprising:
a processor;
a bus coupled to the processor;
a system controller coupled to the bus;
a memory coupled to the system controller;
an input output (IO) controller coupled to the system controller; and
a test module coupled to the IO controller;
wherein the test module is configured to cause tests to be performed on the memory using direct memory access (DMA).
16. The computer system of claim 15 further comprising:
an operating system;
wherein the processor is configured to cause the operating system to be booted, and wherein the test module is configured to cause the tests to be performed on the memory using DMA subsequent to the operating system being booted.
17. The computer system of claim 15 further comprising:
an operating system;
wherein the processor is configured to cause the operating system to be executed, and wherein the test module is configured to cause the tests to be performed on the memory using DMA during execution of the operating system.
18. The computer system of claim 15 wherein the bus comprises a system bus.
19. The computer system of claim 15 wherein the test module is configured to cause tests to be performed on the memory using DMA by providing read and write transactions to the IO controller.
20. The computer system of claim 19 wherein the read and write transactions comprise direct memory access (DMA) transactions.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
I claim:
1. A method of reducing mortality and morbidity after myocardial infarction, comprising administering to a patient in need thereof, a compound selected from the group consisting of GLP-1, GLP-1 analogs, GLP-1 derivatives, and pharmaceutically-acceptable salts thereof, at a dose effective to normalize blood glucose.
2. The method of claim 1, wherein the compound is administered intravenously.
3. The method of claim 1, wherein the compound is administered subcutaneously.
4. The method of claims 2 or 3, wherein the administration is continuous.
5. The method of claim 4 wherein the rate of administration of the compound is between 0.25 and 6 pmolkgh.
6. The method of claim 5 wherein the rate of administration of the compound is between 0.6 and 2.4 pmolkgh.
7. The method of claims 2 or 3 wherein the intravenous administration is intermittent.
8. The method of claim 2 wherein the compound is administered intravenously and also administered by another parenteral route.
9. The method of claim 8 wherein the other parenteral route is the subcutaneous route.
10. The method of claim 1 wherein the compound administered is GLP(7-36) amide, or a pharmaceutically-acceptable salt thereof.
11. A method of reducing morbidity and mortality after myocardial infarction, comprising, administering a compound that exerts insulinotropic activity by interacting with the same receptor, or receptors, with which GLP-1, GLP-1 analogs, and GLP-1 derivatives interact in exerting their insulinotropic activity.
12. A method of reducing morbidity and mortality after myocardial infarction, comprising, administering a compound that enhances insulin sensitivity by interacting with the same receptor, or receptors, with which GLP-1, GLP-1 analogs, and GLP-1 derivatives interact to enhance insulin sensitivity.