1. Apparatus comprising, in combination,
an illumination source for emitting pulses of light toward a scene,
a sensor
for measuring the intensity of light from said scene, in such a manner that
the measured intensity at a pixel of said sensor from a pulse of light varies over time due to different paths that said light travels between said illumination source and said sensor, and
said sensor takes said measurements with respect to a plurality of said pulses, which plurality of pulses are not all in the same direction, and
for outputting signals indicative of data gathered in said measurements, and
one or more processors for processing said data to calculate positions of at least two points in said scene, based, at least in part, on different amounts of time it takes light to travel different paths.
2. The apparatus of claim 1, wherein said illumination source is a pulsed laser.
3. The apparatus of claim 1, wherein said apparatus is adapted for calculating the position of at least one point in said scene, which point is occluded from direct view of said illumination source and said sensor.
4. The apparatus of claim 1, wherein said apparatus is adapted for calculating the distance to a substantially specular surface that does not reflect light directly back to said sensor.
5. The apparatus of claim 1, wherein said illumination source and said sensor are housed in the same device.
6. The apparatus of claim 1, wherein said sensor is directionally-sensitive.
7. The apparatus of claim 1, wherein said sensor comprises an array of photosensors.
8. The apparatus of claim 1, wherein said sensor is adapted to be able to take a measurement of light intensity at least as often as once every 50 picoseconds.
9. The apparatus of claim 1, wherein said sensor is adapted to be able to take a measurement of light intensity at least as often as once every nanosecond.
10. The apparatus of claim 1, wherein said data gathered by said sensor comprises an impulse response, the dimensions of which impulse response relate at least to pixel position, direction of light pulse, and time.
11. The apparatus of claim 10, wherein said one or more processors use onset information in said impulse response to calculate pairwise distances between points in said scene.
12. The apparatus of claim 11, wherein said one or more processors employ isometric embedding to calculate the position of at least two points in said scene.
13. A method comprising the following steps, in combination:
emitting a directionally-varying pulsed signal toward an environment,
using a sensor to take time samples of the intensity of the signal reflected back directly or indirectly to said sensor from said pulses, and
using one or more processors to calculate geometry of said scene, based at least in part on the different amounts of time it takes for a signal to travel different paths.
14. The method of claim 13, wherein said sensor measures light intensity at least once every 50 picoseconds.
15. The method of claim 13, wherein at least one of said processors uses onset information to calculate pairwise distances between points in said scene.
16. The method of claim 15, wherein at least one of said processors uses isometric embedding to calculate the position of at least two points in said scene.
17. A process comprising, in combination:
emitting pulses of light toward a scene,
using a directionally-sensitive sensor to take a plurality of time samples of light reflecting back from said scene, in such a way as to record a multi-dimensional impulse response, the dimensions of which impulse response relate at least to pixel position, direction of light pulse, and time,
using onset information in said impulse response to calculate pairwise distances between points in said scene, and
using isometric embedding to calculate the position of at least two points in said scene.
18. The process of claim 17, wherein said pulses of light are emitted by a laser.
19. The process of claim 18, wherein the position of at least one point in said scene is calculated, which point is occluded from direct view of said sensor.
20. The process of claim 17, wherein a time sample captures changes in light intensity at a pixel as light from a pulse travels back to said pixel over different paths.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory having embodied thereon circuitry comprising:
a digital phase mixer having a first input operative to receive a first input signal having a first phase, a second input operative to receive a second input signal having a second phase, a third input operative to receive a first select signal, a fourth input operative to receive a second select signal, and an output, said digital phase mixer generating a signal at said output having a third phase between said first phase and said second phase based on said first select signal and said second select signal;
a first voltage source coupled to said phase mixer;
a second voltage source coupled to drive said first select signal and said second select signal, wherein said second voltage source has a voltage greater than said first voltage source; and
a ground voltage coupled to said phase mixer.
2. The memory of claim of 1 wherein said first select signal and said second select signal each comprises a same predetermined number of bits.
3. The memory of claim 2 wherein:
said first select signal has a first number of bits enabled; and
said second select signal has a second number of bits enabled.
4. The memory of claim 3 wherein a sum of said first number and said second number is said predetermined number.
5. The memory of claim 3 wherein:
when said first number is greater than said second number, said third phase is closer in phase to said first phase than said second phase;
when said first number is substantially equal to said second number, said third phase is substantially halfway between said first phase and said second phase; and
when said first number is less than said second number, said third phase is closer in phase to said second phase than said first phase.
6. The memory of claim 1 wherein said digital phase mixer comprises:
a first driving block operative to receive said first input signal and said first select signal, and to output a signal having a first phase relationship to said first phase based on said first select signal;
a second driving block operative to receive said second input signal and said second select signal, and to output a signal having a second phase relationship to said second phase based on said second select signal; and
an inverter operative to receive said signal from said first driving block and said signal from said second driving block, and to output said signal having said third phase.
7. The memory of claim 6 wherein said first driving block comprises:
a first NMOS transistor connected to said ground voltage and having a gate coupled to receive a bit from said first select signal;
a second NMOS transistor connected in series to said first NMOS transistor;
a first PMOS transistor connected to said first voltage source and having a gate coupled to receive a complement of said bit from said first select signal; and
a second PMOS transistor connected in series to said first PMOS transistor, said second PMOS transistor and said second NMOS transistor having their gates coupled to a node that receives said first input signal and having their drains coupled to a node that outputs said output of said first driving block.
8. The memory of claim 6 wherein said second driving block comprises:
a first NMOS transistor connected to said ground voltage and having a gate coupled to receive a bit from said second select signal;
a second NMOS transistor connected in series to said first NMOS transistor;
a first PMOS transistor connected to said first voltage source and having a gate coupled to receive a complement of said bit from said second select signal; and
a second PMOS transistor connected in series to said first PMOS transistor, said second PMOS transistor and said second NMOS transistor having their gates coupled to a node that receives said second input signal and having their drains coupled to a node that outputs said output of said second driving block.
9. The memory of claim 6 wherein:
said first phase relationship is a proportionate weight of said first phase based on a number of bits in said first select signal that is enabled; and
said second phase relationship is a proportionate weight of said second phase based on a number of bits in said second select signal that is enabled.
10. The memory of claim 1 wherein said digital phase mixer is differential.
11. The memory of claim 10 further comprising:
a first NMOS transistor connected to said ground voltage and having a gate coupled to receive a bit from said first select signal;
a second NMOS transistor, connected in series to said first NMOS transistor, having a gate coupled to receive said first input signal;
a third NMOS transistor connected to said ground voltage and having a gate coupled to receive a bit from said second select signal;
a fourth NMOS transistor, connected in series to said third NMOS transistor, having a gate coupled to receive said second input signal;
a first PMOS transistor having a source connected to said first voltage source and a drain coupled to drains of said second NMOS transistor and said fourth NMOS transistor at a complement output node that outputs a complement of said output;
a fifth NMOS transistor connected to said ground voltage and having a gate coupled to receive said bit from said first select signal;
a sixth NMOS transistor, connected in series to said fifth NMOS transistor, having a gate coupled to receive a complement of said first input signal;
a seventh NMOS transistor connected to said ground voltage and having a gate coupled to receive said bit from said second select signal;
an eighth NMOS transistor, connected in series to said seventh NMOS transistor, having a gate coupled to receive a complement of said second input signal; and
a second PMOS transistor having a source connected to said first voltage source and a drain coupled to drains of said sixth NMOS transistor and said eighth NMOS transistor at an output node that outputs said output, said first PMOS transistor having a gate coupled to said output node and said second PMOS transistor having a gate coupled to said complement output node.
12. The memory of claim 1 wherein:
said first voltage source is operative to drive a first voltage to said first input signal, said second input signal, and said output; and
said second voltage source is operative to drive a second voltage to said first select signal and said second select signal.
13. A memory having embodied thereon a digital phase mixer comprising:
a first driving block having a first input operative to receive a first input signal having a first phase, a second input operative to receive a first control signal, and an output, said first control signal having a higher logical 1 voltage than said first input signal, said first driving block generating a first signal at said output having a first phase relationship to said first phase based on said first control signal;
a second driving block having a first input operative to receive a second input signal having a second phase, a second input operative to receive a second control signal, and an output, said second control signal having a higher logical 1 voltage than said second input signal, said second driving block generating a second signal at said output having a second phase relationship to said second phase based on said second control signal; and
an inverter having an input coupled to said first driving block output and said second driving block output, said inverter having an output and operative to generate a third signal at said output having a third phase between said first phase and said second phase.
14. The memory of claim 13 wherein said first control signal and said second control signal each comprises a same predetermined number of bits.
15. The memory of claim 14 wherein:
said first control signal has a first number of bits enabled; and
said second control signal has a second number of bits enabled.
16. The memory of claim 15 wherein a sum of said first number and said second number is said predetermined number.
17. The memory of claim 15 wherein:
when said first number is greater than said second number, said third phase is closer in phase to said first phase than said second phase;
when said first number is substantially equal to said second number, said third phase is substantially halfway between said first phase and said second phase; and
when said first number is less than said second number, said third phase is closer in phase to said second phase than said first phase.
18. The memory of claim 13 wherein said first driving block comprises:
a first NMOS transistor connected to a ground voltage and having a gate coupled to receive a bit from said first control signal;
a second NMOS transistor connected in series to said first NMOS transistor;
a first PMOS transistor connected to said first voltage source and having a gate coupled to receive a complement of said bit from said first control signal; and
a second PMOS transistor connected in series to said first PMOS transistor, said second PMOS transistor and said second NMOS transistor having their gates coupled to a node that receives said first input signal and having their drains coupled to a node that outputs said output of said first driving block.
19. The memory of claim 13 wherein said second driving block comprises:
a first NMOS transistor connected to a ground voltage and having a gate coupled to receive a bit from said second control signal;
a second NMOS transistor connected in series to said first NMOS transistor;
a first PMOS transistor connected to said first voltage source and having a gate coupled to receive a complement of said bit from said second control signal; and
a second PMOS transistor connected in series to said first PMOS transistor, said second PMOS transistor and said second NMOS transistor having their gates coupled to a node that receives said second input signal and having their drains coupled to a node that outputs said output of said second driving block.
20. The memory of claim 13 wherein:
said first phase relationship is a proportionate weight of said first phase based on a number of bits in said first control signal that is enabled; and
said second phase relationship is a proportionate weight of said second phase based on a number of bits in said second control signal that is enabled.
21. A dynamic random access memory having embodied thereon circuitry comprising:
a digital phase mixer having a first input operative to receive a first input signal having a first phase, a second input operative to receive a second input signal having a second phase, a third input operative to receive a first select signal, a fourth input operative to receive a second select signal, and an output, said digital phase mixer generating a signal at said output having a third phase between said first phase and said second phase based on said first select signal and said second select signal;
a first voltage source coupled to said phase mixer;
a second voltage source coupled to drive said first select signal and said second select signal, wherein said second voltage source has a voltage greater than said first voltage source; and
a ground voltage coupled to said phase mixer.
22. A dynamic random access memory having embodied thereon a digital phase mixer comprising:
a first driving block having a first input operative to receive a first input signal having a first phase, a second input operative to receive a first control signal, and an output, said first control signal having a higher logical 1 voltage than said first input signal, said first driving block generating a first signal at said output having a first phase relationship to said first phase based on said first control signal;
a second driving block having a first input operative to receive a second input signal having a second phase, a second input operative to receive a second control signal, and an output, said second control signal having a higher logical 1 voltage than said second input signal, said second driving block generating a second signal at said output having a second phase relationship to said second phase based on said second control signal; and
an inverter having an input coupled to said first driving block output and said second driving block output, said inverter having an output and operative to generate a third signal at said output having a third phase between said first phase and said second phase.