1. A method of fabricating a package substrate for carrying a chip having a plurality of bumps thereon, the method comprising:
providing a first substrate and a second substrate, wherein the first substrate has at least a first circuit layer disposed on a surface thereof;
forming a second circuit layer on the second substrate such that the second circuit layer and the second substrate form an interposer, wherein the second circuit layer comprises a plurality of bonding pads and a plurality of traces such that each trace is electrically connected to one of the bonding pads and the bonding pads are disposed in locations corresponding to the bumps on the chip;
disposing the interposer on the first substrate;
after disposing the interposer, forming at least a dielectric layer over the first substrate and in a periphery of the interposer; and
forming a third circuit layer over a portion of the dielectric layer such that the third circuit layer is electrically connected to the second circuit layer of the interposer and the first circuit layer of the first substrate.
2. The method of claim 1, wherein the process of disposing the interposer on the first substrate comprises performing an adhesion process.
3. The method of claim 1, wherein before disposing the interposer on the first substrate, the method further comprises forming a passivation layer over the second substrate and the traces but exposes the bonding pads.
4. The method of claim 1, wherein the process further comprises forming a plurality of conductive vias in the dielectric layer such that the third circuit layer is electrically connected to the first circuit layer of the first substrate through the conductive vias.
5. The method of claim 1, wherein the process further comprises forming a solder mask layer over the third circuit layer and the dielectric layer but exposes the interposer.
6. The method of claim 1, wherein the process of forming the second circuit layer on the second substrate comprises depositing a metallic layer over the second substrate and performing a photolithographic and etching process on the metallic layer.
7. The method of claim 1, wherein at least one of the traces is disposed between two neighboring bonding pads.
8. The method of claim 1, wherein the process of fabricating the dielectric layer and the third circuit layer comprises performing a build-up process.
9. The method of claim 1, wherein the dielectric layer contacts a peripheral sidewall of the interposer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A metalized film capacitor comprising:
a dielectric film;
a first metal vapor-deposition electrode provided on an upper surface of the dielectric film;
a second metal vapor-deposition electrode having an upper surface facing a lower surface of the first metal vapor-deposition electrode across the dielectric film;
a low resistance portion made of a conductor provided at the first metal vapor-deposition electrode;
a first electrode connected to the first metal vapor-deposition electrode; and
a second electrode connected to the second metal vapor-deposition electrode, wherein
the first metal vapor-deposition electrode is made of substantially only aluminum and magnesium,
the first metal vapor-deposition electrode includes:
a first metal vapor-deposition layer having a lower surface constituting the lower surface of the first vapor-deposition electrode; and
a second metal vapor-deposition layer having an upper surface constituting an upper surface of the first vapor-deposition electrode, wherein
the low resistance portion is provided between an upper surface of the first metal vapor-deposition layer and a lower surface of the second metal vapor-deposition layer.
2. The metalized film capacitor according to claim 1, wherein
the first metal vapor-deposition layer of the first metal vapor-deposition electrode mainly contains aluminum, and
the second metal vapor-deposition layer of the first metal vapor-deposition electrode contains magnesium.
3. The metalized film capacitor according to claim 1, wherein
the first electrode is provided on an end of the dielectric film,
the low resistance portion is connected to the first electrode at the end of the dielectric film.
4. The metalized film capacitor according to claim 1, wherein the lower surface of the second metal vapor-deposition layer of the first metal vapor-deposition electrode is situated on the upper surface of the first metal vapor-deposition layer and extends onto an upper surface of the low resistance portion.
5. The metalized film capacitor according to claim 4, wherein
the first metal vapor-deposition layer of the first metal vapor-deposition electrode mainly contains aluminum, and
the second metal vapor-deposition layer of the first metal vapor-deposition electrode contains magnesium.
6. A metalized film capacitor comprising:
a dielectric film;
a first metal vapor-deposition electrode provided on an upper surface of the dielectric film;
a second metal vapor-deposition having an upper surface facing a lower surface of the first metal vapor-deposition electrode across the dielectric film;
a first electrode connected to the first metal vapor-deposition electrode; and
a second electrode connected to the second metal vapor-deposition electrode, wherein
at least one metal vapor-deposition electrode of the first metal vapor-deposition electrode and the second metal vapor-deposition electrode is made of substantially only aluminum and magnesium, and
an amount of magnesium in the at least one metal vapor-deposition electrode ranges from 0.5 wt. % to 25 wt. %.
7. A metalized film capacitor comprising:
a dielectric film;
a first metal vapor-deposition electrode provided on an upper surface of the dielectric film;
a second metal vapor-deposition having an upper surface facing a lower surface of the first metal vapor-deposition electrode across the dielectric film;
a first electrode connected to the first metal vapor-deposition electrode; and
a second electrode connected to the second metal vapor-deposition electrode, wherein
at least one metal vapor-deposition electrode of the first metal vapor-deposition electrode and the second metal vapor-deposition electrode is made of substantially only aluminum and magnesium,
the at least one metal vapor-deposition electrode is made of an alloy including aluminum and magnesium,
an amount of magnesium in the alloy ranges from 0.5 wt. % to 15 wt. %,
magnesium is distributed unevenly in the at least one metal vapor-deposition electrode, and
a maximum concentration of magnesium in the at least one of the metal vapor-deposition electrodes is located within a region from an upper surface of the at least one metal vapor-deposition electrode up to a distance of \u2153 of a thickness of the at least one metal vapor-deposition electrode, or within a region from a lower surface of the at least one metal vapor-deposition electrode up to a distance of \u2153 of the thickness of the at least one metal vapor-deposition electrode.