1. A method for implementing an interactive automated system, comprising:
processing spoken utterances of a person using a processing system located in proximity to the person;
transmitting the processed speech information to a remote data center using a wireless link;
analyzing the transmitted speech information;
based upon an indicated intent of the spoken utterances, selecting at least one optimal speech recognition engine from a set of speech recognition engines;
converting the analyzed speech information into packet data format to produce packet speech information;
using an internet-protocol transport network, transporting the packet speech information to the selected at least one optimal speech recognition engine and recognizing the converted speech information with the selected at least one optimal speech recognition engine;
retrieving recognition results and an associated confidence score from the selected at least one optimal speech recognition engine;
if the confidence score meets or exceeds a predetermined threshold for a best match, processing the recognition results to:
perform a search;
generate search results;
transport the search results to the processing system; and
present the search results to the person; and
if the confidence score is below the predetermined threshold, selecting at least one alternative optimal speech recognition engine to carry out recognition of the converted speech information.
2. The method according to claim 1, wherein the processing system located in proximity to the person is a telematics processing system.
3. The method according to claim 1, wherein the generated search results are in the form of a list of the search results.
4. The method according to claim 3, wherein the list of search results is transported to the processing system and presented to the person.
5. The method according to claim 1, wherein the at least one alternative optimal speech recognition engine is agent-assisted.
6. The method according to claim 1, wherein the selected at least one optimal speech recognition engine is not local.
7. The method according to claim 1, wherein the presentation of the search results is continued with the person prior to, or subsequent to, receiving the recognition results in an asynchronous manner.
8. The method according to claim 1, wherein the presentation of the search results is continued with the person subsequent to receiving the recognition results in a synchronous manner.
9. The method according to claim 1, further comprising logging packet data of the packet speech information and the recognition results for subsequent analysis.
10. The method according to claim 1, wherein the processing system is located on-board a vehicle.
11. The method according to claim 10, further comprising transporting vehicle location information along with the packet speech information to the selected at least one optimal speech recognition engine.
12. The method according to claim 11, further comprising logging the vehicle location information for subsequent analysis.
13. The method according to claim 1, wherein the indicated intent pertains to at least one of:
internet browsing; and
navigational information.
14. A method for implementing an interactive automated system, comprising:
processing spoken utterances of a vehicle driver using a telematics processing system located on-board a vehicle;
transmitting the processed speech information to a remote data center using a wireless link;
analyzing the transmitted speech information;
based upon an indicated intent of the spoken utterances, selecting at least one optimal speech recognition engine from a set of speech recognition engines;
converting the analyzed speech information into packet data format to produce packet speech information;
using an internet-protocol transport network, transporting the packet speech information and vehicle location information to the selected at least one optimal speech recognition engine and recognizing the converted speech information with the selected at least one optimal speech recognition engine;
retrieving recognition results and an associated confidence score from the selected at least one optimal speech recognition engine;
if the confidence score meets or exceeds a predetermined threshold for a best match, processing the recognition results to:
perform a search;
generate search results;
transport the search results to the processing system; and
present the search results to the vehicle driver; and
if the confidence score is below the predetermined threshold, selecting at least one alternative optimal speech recognition engine to carry out recognition of the converted speech information.
15. The method according to claim 14, wherein the at least one alternative optimal speech recognition engine is agent-assisted.
16. The method according to claim 14, wherein the selected at least one optimal speech recognition engine is not local.
17. The method according to claim 14, wherein the presentation of the search results is continued with the vehicle driver prior to, or subsequent to, receiving the recognition results in an asynchronous manner.
18. The method according to claim 14, wherein the presentation of the search results is continued with the vehicle driver subsequent to receiving the recognition results in a synchronous manner.
19. The method according to claim 14, wherein the indicated intent pertains to at least one of:
internet browsing; and
navigational information.
20. An interactive automated speech recognition system, comprising:
a processing system located in proximity to a person;
a remote data center;
a wireless link that transmits processed speech information from the processing system to the remote data center,
wherein the processing system:
receives spoken utterances of a person; and
processes the spoken utterances and transmits the processed speech information to the remote data center using the wireless link, wherein the remote data center analyzes the transmitted processed speech information and converts the analyzed speech information into packet data format;
at least one optimal speech recognition engine selected to recognize the converted speech information, the at least one optimal speech recognition engine being selected from a set of speech recognition engines based upon an indicated intent of the spoken utterances;
an internet protocol transport network that transports the converted speech information to the selected at least one optimal speech recognition engine; and
wherein the selected at least one optimal speech recognition engine produces recognition results and an associated confidence score, whereby:
if the confidence score meets or exceeds a predetermined threshold for a best match, the recognition results are processed to:
perform a search;
generate search results;
transport the search results to the processing system; and
present the search results to the person; and
if the confidence score below the predetermined threshold, at least one alternative optimal speech recognition engine is selected to carry out recognition of the converted speech information.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system comprising:
a digital-to-analog converter (DAC) comprising:
a first DAC core that generates a first output;
a second DAC core that generates a second output; and
a butterfly switch that includes switch transistors,
wherein said butterfly switch selectively connects said first output and said second output to an output stage of said DAC; and
a gate drive module that generates a protection bias voltage that biases said switch transistors to operate in a protected mode when an output of a power supply, a bias circuit, and a clock generator associated with said DAC is not within a predetermined range,
wherein said protective bias voltage is output concurrently with a supply voltage of said output stage.
2. The system of claim 1 further comprising cascode transistors, wherein said switch transistors and said cascode transistors have voltage ratings less than said supply voltage of said output stage.
3. The system of claim 1 further comprising cascode transistors, wherein said cascode transistors are biased using said supply voltage of said output stage.
4. The system of claim 1 wherein said gate drive module sets states of clock signals that are output to gates of said switch transistors to a predetermined state when said switch transistors operate in said protected mode.
5. The system of claim 1 wherein said gate drive module generates a normal bias voltage that is used to bias said switch transistors after said power supply, said bias circuit, and said clock generator begin operating within respective predetermined ranges.
6. The system of claim 1 further comprising cascode transistors, wherein outputs of said switch transistors are input to corresponding ones of said cascode transistors, and wherein outputs of said cascode transistors are combined at said output stage to generate an output of said DAC.
7. The system of claim 1 further comprising cascode transistors, wherein outputs of said switch transistors are combined and input to said cascode transistors, and wherein outputs of said cascode transistors are coupled to said output stage to generate an output of said DAC.
8. The system of claim 1 wherein an output data rate of said DAC is twice a clock rate of clock signals used to drive said switch transistors when different samples are concurrently input to said first DAC core and said second DAC core.
9. The system of claim 1 wherein an output of said butterfly switch has a non-return-to-zero (NRZ) impulse response when identical samples are input to said first and second DAC cores.
10. The system of claim 1 wherein an output of said butterfly switch has a radio frequency (RF) impulse response when a sample is input to said first DAC core and an inverted version of said sample is input to said second DAC core.
11. The system of claim 1 wherein an output of said butterfly switch has a return-to-zero (RZ) impulse response when samples to be converted are input to said first DAC core and a fixed code is input to said second DAC core.
12. A method of operating a digital-to-analog converter (DAC), comprising:
generating a first output using a first DAC core of said DAC;
generating a second output using a second DAC core of said DAC;
selectively connecting said first output and said second output to an output stage of said DAC using a butterfly switch that includes switch transistors and cascode transistors;
generating a protection bias voltage;
outputting said protection bias voltage concurrently with a supply voltage of said output stage;
biasing said cascode transistors using said supply voltage;
biasing said switch transistors to operate in a protected mode using said protection bias voltage when an output of a power supply, a bias circuit, and a clock generator associated with said DAC is not within a predetermined threshold;
setting states of clock signals that are output to gates of said switch transistors to a predetermined state when said switch transistors operate in said protected mode; and
biasing said switch transistors using a normal bias voltage after said power supply, said bias circuit, and said clock generator begin operating within respective predetermined ranges.
13. The method claim 12 wherein said switch transistors and said cascode transistors have voltage ratings less than said supply voltage of said output stage.
14. The method of claim 12 further comprising:
inputting outputs of said switch transistors to corresponding ones of said cascode transistors; and
combining outputs of said cascode transistors at said output stage to generate an output of said DAC.
15. The method of claim 12 further comprising:
combining outputs of said switch transistors to generate combined outputs;
inputting said combined outputs to said cascode transistors; and
coupling outputs of said cascode transistors to said output stage to generate an output of said DAC.
16. The method of claim 12 further comprising:
outputting data from said DAC at a data rate that is twice a clock rate of clock signals used to drive said switch transistors when different samples are concurrently input to said first and second DAC cores;
generating a non-return-to-zero (NRZ) impulse response at said output stage by inputting identical samples to said first and second DAC cores;
generating a radio frequency (RF) impulse response at said output stage by inputting a sample to said first DAC core and an inverted version of said sample to said second DAC core; or
generating a return-to-zero (RZ) impulse response at said output stage by inputting samples to said first DAC core and a fixed code is input to said second DAC core.
17. A digital-to-analog converter (DAC) comprising:
a first DAC core that generates a first output;
a second DAC core that generates a second output; and
a butterfly switch that includes switch transistors and cascode transistors,
wherein said butterfly switch selectively connects said first output and said second output to an output stage of said DAC, and
wherein said cascode transistors are biased using a supply voltage of said output stage; and
a gate drive module that generates a protection bias voltage that biases said switch transistors to operate in a protected mode when an output of a power supply, a bias circuit, and a clock generator associated with said DAC is not within a predetermined range,
wherein said protective bias voltage is output concurrently with said supply voltage of said output stage.
18. The DAC of claim 17 wherein said switch transistors and said cascode transistors have voltage ratings less than said supply voltage of said output stage.
19. The DAC of claim 17 further comprising:
a protection module that receives outputs from at least one of said power supply, said bias circuit, and said clock generator associated with said DAC,
wherein said protection module selectively operates said switch transistors in the protected mode when one of said outputs is not within said predetermined range.
20. The DAC of claim 17 wherein said gate drive module sets states of clock signals that are output to gates of said switch transistors to a predetermined state when said switch transistors operate in said protected mode.
21. The DAC of claim 17 wherein said gate drive module generates a normal bias voltage that is used to bias said switch transistors after said power supply, said bias circuit, and said clock generator begin operating within respective predetermined ranges.
22. The DAC of claim 17 wherein outputs of said switch transistors are input to corresponding ones of said cascode transistors, and wherein outputs of said cascode transistors are combined at said output stage to generate an output of said DAC.
23. The DAC of claim 17 wherein outputs of said switch transistors are combined and input to said cascode transistors, and wherein outputs of said cascode transistors are coupled to said output stage to generate an output of said DAC.
24. The DAC of claim 17 wherein an output data rate of said DAC is twice a clock rate of clock signals used to drive said switch transistors when different samples are concurrently input to said first DAC core and said second DAC core.
25. The DAC of claim 17 wherein an output of said butterfly switch has a non-return-to-zero (NRZ) impulse response when identical samples are input to said first and second DAC cores.
26. The DAC of claim 17 wherein an output of said butterfly switch has a radio frequency (RF) impulse response when a sample is input to said first DAC core and an inverted version of said sample is input to said second DAC core.
27. The DAC of claim 17 wherein an output of said butterfly switch has a return-to-zero (RZ) impulse response when samples to be converted are input to said first DAC core and a fixed code is input to said second DAC core.