1. A system for processing positioning signals, the system comprising:
a mobile phone including:
a tracker hardware interface for receiving positioning information from a tracker hardware internal or external to the mobile phone;
a memory including a GPS library having a user interface, a tracker interface, and an operating system interface, the tracker interface including at least one tracker interface function for communicating with the tracker hardware over the tracker hardware interface; and
a processor for running the tracker interface function,
wherein the processor, using the GPS library, computes a location of the mobile phone based on the positioning information obtained by the tracker interface function, and is configured to communicate the location of the mobile phone to a plurality of respectively different user programs running on the mobile phone in response to requests from the respective programs.
2. The system of claim 1, wherein the tracker hardware interface comprises a serial interface.
3. The system of claim 1, wherein the user interface comprises at least one positioning control function and at least one positioning engine communication function.
4. The system of claim 3, wherein the positioning control function comprises a positioning engine start function.
5. The system of claim 3, wherein the positioning control function comprises a positioning engine stop function.
6. The system of claim 3, wherein the positioning engine communication function is a command delivery function.
7. The system of claim 1, wherein the user programs includes at least one of: a mapping program displaying the location of the mobile phone, a course charter program displaying a path traveled by the mobile phone and a location aid program displaying location information of the mobile phone.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising an EEPROM and a FLASH-EPROM memory, in which the EEPROM memory comprises a matrix of rows and columns of memory cells with a selection transistor having a selection gate and, arranged in series therewith, a memory transistor having a floating gate and a control gate, in which the selection transistor is further connected to a bit line of the EEPROM memory and the memory transistor is connected to a source line of the EEPROM memory, which source line is common for a plurality of memory cells, and in which the FLASH-EPROM memory comprises a matrix of rows and columns of memory cells with a memory transistor having a floating gate and a control gate, characterized in that, in addition to the memory transistor having a floating gate and a control gate, the memory cells of the FLASH-EPROM memory comprise a transistor arranged in series with this memory transistor and having a control gate, the memory transistor being further connected to a bit line of the FLASH-EPROM memory, and the transistor arranged in series with the memory transistor being connected to a source line of the FLASH-EPROM memory, which source line is common for a large number of memory cells.
2. A semiconductor device as claimed in claim 1, comprising a silicon body having a surface which is provided at the area of the memory cells of the EEPROM memory with a layer of silicon oxide having a thickness which renders it suitable as a gate oxide for the selection transistor, which layer underneath the floating gate of the memory transistor is provided with a part having a smaller thickness which renders said part of the layer of silicon oxide suitable as a tunnel oxide for the memory transistor, characterized in that the surface of the silicon oxide is provided with a layer of silicon oxide at the area of the memory cells of the FLASH-EPROM memory underneath the control gates of the transistors arranged in series with the memory transistors, which layer of silicon oxide has a thickness which is equal to the thickness of the part having the smaller thickness and being present underneath the floating gate of the memory transistors of the EEPROM memory.
3. A semiconductor device as claimed in claim 2, characterized in that the surface of the silicon body is provided with a layer of silicon oxide at the area of the memory cells of the FLASH-EPROM memory underneath the floating gates of the memory transistors, which layer of silicon oxide has a thickness which is also equal to the thickness of the part having the smaller thickness and being present underneath the floating gate of the memory transistors of the EEPROM memory.
4. A method of manufacturing a semiconductor device as claimed in claim 3, characterized in that, after active semiconductor regions of a first conductivity type adjacent the surface of the silicon body have been formed in said silicon body at the area of the memory cells to be formed in the two memories, the silicon body is subjected to a first oxidation process in which the surface of the silicon body is provided with a first layer of silicon oxide in which windows are formed at the area of floating gates to be formed in the memory transistors of the EEPROM memory and at the area of the memory cells to be formed in the FLASH-EPROM memory, whereafter the silicon body is subjected to a second oxidation process in which a second layer of silicon oxide is formed within the windows with such a thickness that said layer can serve as a tunnel oxide for the memory transistors to be formed in both memories and as a gate oxide of the transistor arranged in series with the memory transistor of the FLASH-EPROM memory, and in which the first layer of silicon oxide acquires such a larger thickness that it can serve as a gate oxide for the selection transistors to be formed in the EEPROM memory.
5. A method of manufacturing a semiconductor device as claimed in claim 4, characterized in that, prior to the first oxidation treatment, the active regions for the memory cells of the EEPROM memory are provided with semiconductor zones of the first conductivity type adjacent the surface and serving as tunnel zones are formed at the area of the floating gates to be formed in the memory transistors, which semiconductor zones have a doping concentration which is higher than that of the active regions.
6. A method of manufacturing a semiconductor device as claimed in claim 4 or 5, characterized in that, after the formation of the two layers of silicon oxide, a first layer of amorphous or polycrystalline silicon is deposited in which the floating gates of the memory transistors and the selection gates of the selection transistors of the memory cells of the EEPROM memory, and the floating gates of the memory transistors and the control gates of the FLASH-EPROM memory transistors arranged in series therewith are formed.
7. A method of manufacturing a semiconductor device as claimed in claim 6, characterized in that, after the formation of the floating gates of the memory cells of both memories in the first layer of polycrystalline silicon, these floating gates are provided with a layer of dielectric, whereafter a second layer of amorphous or polycrystalline silicon is deposited, in which layer the control gates of the memory transistors of the memory cells of the EEPROM memory and the control gates of the memory transistors of the memory cells of the FLASH-EPROM memory are formed.