1. A semiconductor package, comprising:
a substrate having a die attach surface; and
a die mounted on die attach surface of the substrate via a conductive pillar bump, wherein the die comprises:
a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, wherein the length of the first edge is different from that of the second edge from a plan view.
2. The semiconductor package as claimed in claim 1, wherein the die further comprises:
an interconnection structure between the substrate and the metal pad, wherein the interconnection structure comprises a plurality of metal layers and a plurality of dielectric layers, wherein the interconnection structure comprises a first passivation layer formed by an uppermost dielectric layer of the dielectric layers of the interconnection structure;
a second passivation layer disposed between the substrate and the conductive pillar bump, on the metal pad; and
an underfill between the die and the substrate.
3. The semiconductor package as claimed in claim 1, wherein the metal pad is an octangular shape in the plan view.
4. The semiconductor package as claimed in claim 2, wherein the metal pad is formed by a topmost metal layer of the metal layers of the interconnection structure.
5. The semiconductor package as claimed in claim 1, wherein the conductive pillar bump is composed of a metal stack comprising an under bump metallurgy (UBM) layer, a copper layer, and a solder cap.
6. The semiconductor package as claimed in claim 1, wherein the metal pad has a similar shape to the corresponding conductive pillar bump in the plane view.
7. The semiconductor package as claimed in claim 1, wherein the metal pad has 2-fold rotational symmetry only in the plane view.
8. The semiconductor package as claimed in claim 1, wherein the conductive pillar bump is an octangular shape or oval shape in the plan view.
9. The semiconductor package as claimed in claim 2, wherein the second passivation layer has an opening therein to expose the metal pad.
10. The semiconductor package as claimed in claim 9, wherein the opening is an octangular shape in the plan view and the opening has a third edge and a fourth edge substantially vertical to each other, wherein the length the third edge is different from the fourth edge in the plan view.
11. A semiconductor package, comprising:
a substrate having a die attach surface; and
a die mounted on die attach surface of the substrate via a conductive pillar bump, wherein the die comprises:
a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first length along a first direction and a second length, which is different from the first length, along a second direction from a plan view, wherein the angle between the first direction and the second direction is larger than 0 degrees and less than or equal to 90 degrees.
12. The semiconductor package as claimed in claim 11, wherein the die further comprises:
an interconnection structure between the substrate and the metal pad, wherein the interconnection structure comprises a plurality of metal layers and a plurality of dielectric layers, wherein the interconnection structure comprises a first passivation layer formed by an uppermost dielectric layer of the dielectric layers of the interconnection structure;
a second passivation layer disposed between the substrate and the conductive pillar bump, on the metal pad; and
an underfill between the die and the substrate.
13. The semiconductor package as claimed in claim 11, wherein the metal pad is an octangular shape or oval shape in the plan view.
14. The semiconductor package as claimed in claim 12, wherein the metal pad is formed by a topmost metal layer of the metal layers of the interconnection structure.
15. The semiconductor package as claimed in claim 11, wherein the conductive pillar bump is composed of a metal stack comprising an under bump metallurgy (UBM) layer, a copper layer, and a solder cap.
16. The semiconductor package as claimed in claim 11, wherein the metal pad has similar shape to the corresponding conductive pillar bump in the plane view.
17. The semiconductor package as claimed in claim 11, wherein the metal pad has 2-fold rotational symmetry only in the plane view.
18. The semiconductor package as claimed in claim 11, wherein the conductive pillar bump is an octangular shape or oval shape in the plan view.
19. The semiconductor package as claimed in claim 12, wherein the second passivation layer has an opening therein to expose the metal pad.
20. The semiconductor package as claimed in claim 19, wherein the opening is an octangular shape in the plan view and the opening has a third length along the first direction and a fourth length, which is different from the third length, along the second direction in the plan view.
21. The semiconductor package as claimed in claim 11, wherein a ratio of the first length to the second length is between 46:45 and 99:54.
22. A semiconductor package, comprising:
a substrate having a die attach surface; and
a die mounted on die attach surface of the substrate via a conductive pillar bump, wherein the die comprises:
a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has 2-fold rotational symmetry only from a plan view.
23. The semiconductor package as claimed in claim 22, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, wherein the length of the first edge is different from that of the second edge from the plan view.
24. The semiconductor package as claimed in claim 22, wherein the metal pad has a first length along a first direction and a second length, which is different from the first length, along a second direction from a plan view, wherein the angle between the first direction and the second direction is larger than 0 degrees and less than or equal to 90 degrees.
25. The semiconductor package as claimed in claim 22, wherein the die further comprises:
an interconnection structure between the substrate and the metal pad, wherein the interconnection structure comprises a plurality of metal layers and a plurality of dielectric layers, wherein the interconnection structure comprises a first passivation layer formed by an uppermost dielectric layer of the dielectric layers of the interconnection structure;
a second passivation layer disposed between the substrate and the conductive pillar bump, on the metal pad; and
an underfill between the die and the substrate.
26. The semiconductor package as claimed in claim 22, wherein the metal pad is an octangular shape or oval shape in the plan view.
27. The semiconductor package as claimed in claim 25, wherein the metal pad is formed by a topmost metal layer of the metal layers of the interconnection structure.
28. The semiconductor package as claimed in claim 22, wherein the conductive pillar bump is composed of a metal stack comprising an under bump metallurgy (UBM) layer, a copper layer, and a solder cap.
29. The semiconductor package as claimed in claim 22, wherein the metal pad has similar shape to the corresponding conductive pillar bump in the plane view.
30. The semiconductor package as claimed in claim 22, wherein the conductive pillar bump is an octangular shape or oval shape in the plan view.
31. The semiconductor package as claimed in claim 25, wherein the second passivation layer has an opening therein to expose the metal pad.
32. The semiconductor package as claimed in claim 31, wherein the opening is an octangular shape in the plan view and the opening has a third length along the first direction and a fourth length, which is different from the third length, along the second direction in the plan view.
33. The semiconductor package as claimed in claim 24, wherein a ratio of the first length to the second length is between 46:45 and 99:54.
34. A semiconductor package, comprising:
a substrate;
a conductive trace disposed on the substrate; and
a conductive pillar bump disposed on the conductive trace, wherein the conductive bump is coupled to a die.
35. The semiconductor package as claimed in claim 34, wherein conductive trace comprising a first portion having a first width and a second portion having a second width, and the conductive pillar bump is disposed on the second portion of the conductive trace.
36. The semiconductor package as claimed in claim 34, wherein the semiconductor package comprises a plurality of conductive pillar bumps disposed on the second portion of the conductive trace.
37. The semiconductor package as claimed in claim 34, wherein the semiconductor package further comprises a metal pad located between the conductive trace and the substrate.
38. The semiconductor package as claimed in claim 37, wherein the semiconductor package further comprises a metal pad located between the conductive pillar bump and the conductive trace.
39. The semiconductor package as claimed in claim 34, wherein the conductive trace comprises a plurality of conductive layers and a metal pad, wherein the metal pad is sandwiched by the plurality of conductive layers
40. A semiconductor package, comprising:
a substrate;
a first conductive trace disposed on the substrate;
a second conductive trace disposed on the substrate;
a conductive pillar bump disposed on the second conductive trace, connecting to a conductive bump or a metal pad of the semiconductor die;
a first conductive structure disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate; and
a die disposed over the first conductive trace.
41. The semiconductor package as claimed in claim 40, further comprising:
a solder resistance layer disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the first conductive trace.
42. The semiconductor package as claimed in claim 40, wherein the first conductive structure contacts the second conductive trace, overlapping with the conductive pillar bump.
43. The semiconductor package as claimed in claim 40, further comprising:
a second conductive structure disposed overlapping a portion of the second conductive trace and the semiconductor die or a portion of the second conductive trace and the substrate, wherein the portion of the second conductive trace is away from the conductive pillar bump.
44. The semiconductor package as claimed in claim 43, wherein the third conductive structure or the second conductive structure comprises a single-layer structure or a multi-layer structure.
45. The semiconductor package as claimed in claim 44, wherein the single-layer structure comprises a trace or a pad.
46. The semiconductor package as claimed in claim 44, wherein the multi-layer structure is a stack of traces, pads or combinations thereof.
47. The semiconductor package as claimed in claim 40, wherein the first conductive structure is a polygonal shape, a rounded shape, or a drop shape.
48. The semiconductor package as claimed in claim 40, wherein the second conductive trace comprises signal traces or ground traces.
49. The semiconductor package as claimed in claim 41, wherein the solder resistance layer is disposed away from a portion of the second conductive trace, which overlaps with the conductive pillar bump, by a distance.
50. The semiconductor package as claimed in claim 41, further comprising an underfill material filling a gap between the substrate and the semiconductor die, covering the solder resistance layer.
51. The semiconductor package as claimed in claim 41, wherein the extending portion of the solder resistance layer and the portion of the first conductive trace collectively have a T-shaped cross section.
52. The semiconductor package as claimed in claim 41, wherein the extending portion of the solder resistance layer is below the semiconductor die and within a projection area of the semiconductor die.
53. The semiconductor package as claimed in claim 50, wherein a portion of a bottom surface of the extending portion of the solder resistance layer is exposed from the portion of the first conductive trace.
54. The semiconductor package as claimed in claim 53, wherein the portion of the bottom surface of the extending portion of the solder resistance layer is wrapped by the underfill material.
55. The semiconductor package as claimed in claim 41, wherein the extending portion of the solder resistance layer has a vertical sidewall extruding over to an adjacent vertical sidewall of the portion of the first conductive trace.
56. The semiconductor package as claimed in claim 41, wherein the extending portion of the solder resistance layer extends along the first conductive trace and over a die attach surface of the semiconductor die.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of forming a porous fuel cell sheet, comprising:
flattening a screen to form a sheet that has a plurality of apertures operative to communicate a fluid within a fuel cell.
2. The method of claim 1, wherein the screen is a wire screen.
3. The method of claim 2, wherein the flattening step joins a first wire of the wire screen to a second wire of the wire screen.
4. The method of claim 2, wherein the flattening step cold welds a first wire of the wire screen to a second wire of the wire screen.
5. The method of claim 1, including weaving a plurality of wires to form the screen.
6. The method of claim 5, wherein the plurality of wires comprise metal wires.
7. The method of claim 5, wherein the plurality of wires have a generally circular cross-section.
8. The method of claim 1, wherein the screen includes a plurality of openings before the flattening step, and the flattening step decreases a width of the plurality of openings to form the plurality of apertures.
9. The method of claim 1, wherein the screen has a higher porosity than the sheet.
10. The method of claim 1, wherein the flattening step comprises rolling and compressing the screen.
11. The method of claim 1, wherein the sheet is operative to support a cell.
12. The method of claim 1, wherein the plurality of apertures are operative to communicate the fluid between an interconnector and a cell.
13. The method of claim 1, wherein the flattening step comprises multiple rolling and compression steps.
14. The method of claim 1, wherein the flattening step comprises multiple rolling and compression steps with intermediate annealing steps.
15. A fuel cell stack assembly comprising:
a cell; and
a sheet formed from a flattened screen, the sheet defining a plurality of apertures configured to allow passage of a fuel cell fluid through the sheet.
16. The fuel cell stack assembly of claim 15, wherein the cell comprises a thick film tri-layer cell.
17. The fuel cell stack assembly of claim 15, wherein the flattened screen comprises a plurality of flattened metal wires.
18. The fuel cell stack assembly of claim 15, including an interconnector, and wherein the sheet is configured to communicate a fuel cell fluid between the interconnector and the cell.
19. The fuel cell stack assembly of claim 15, wherein the cell comprises an anode portion adjacent the sheet layer.
20. The fuel cell stack assembly of claim 15, wherein the sheet supports the cell.