1. A logic simulation method, comprising:
storing a state vector in a computational memory;
distributing, by each of multiple data stream controllers, an input comprising a portion of the state vector for processing by a sub-array of computational logic processors, wherein each of the multiple data stream controllers is coupled with a different sub-array of computational logic processors;
processing the inputs by a product term latching comparator within each of the computational logic processors;
sending, by the computational logic processors, computational results of processing the inputs to the data stream controllers;
sending the computational results, by the data stream controllers, to the computational memory; and
assembling the computational results into a new state vector in the computational memory.
2. The method of claim 1, wherein one or more of the computational logic processors comprises a Boolean computational logic processor or a real time computational logic processor.
3. The method of claim 1, wherein one or more of the computational logic processors are configured to provide modeling of logic constructions.
4. The method of claim 1, wherein one or more of the computational logic processors comprises a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).
5. The method of claim 1, wherein one or more of the computational logic processors comprises a real-time computational logic processor, and further comprising performing real-time look-ups by the real-time computational logic processor to determine timing of logic propagation and transition to simulate behavior of a physical circuit simulated by the logic simulation method.
6. A logic simulation system, comprising:
a computational memory configured to store an input state vector;
one or more deterministic data buses coupled with the computational memory, each of the deterministic data buses configured to propagate input and output state vector data;
multiple data stream controllers coupled with the one or more deterministic data buses, each of the data stream controllers configured to manage steps in a computational cycle completed by multiple computational logic processors; and
a plurality of sub-arrays of computational logic processors, each sub-array coupled with a data stream controller, wherein each of the computational logic processors comprises a product term latching comparator configured to compute a portion of a next state vector from the input state vector.
7. The logic simulation system of claim 6, wherein one or more of the computational logic processors comprises a Boolean computational logic processor or a real time computational logic processor.
8. The logic simulation system of claim 6, wherein one or more of the computational logic processors is configured to provide modeling of logic constructions.
9. The logic simulation system of claim 6, wherein one or more of the computational logic processors comprises a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).
10. The logic simulation system of claim 6, wherein one or more of the computational logic processors comprises a real-time computational logic processor, and wherein the real-time computational logic processor comprises a real time look up engine configured to perform real-time look-ups to determine timing of logic propagation and transition to simulate behavior of a physical circuit simulated by the logic simulation system.
11. The logic simulation system of claim 6, further comprising a host processor configured to run a simulation cycle, comprising triggering a simulation cycle and transmitting test fixture inputs and outputs.
12. The logic simulation system of claim 6, wherein one or more of the computational logic processors comprises a Boolean computational logic processor or a real time computational logic processor coupled with a dual port RAM, a Vector State Stream (VSS) module, and a deterministic data bus, wherein the dual port RAM is configured to store instructions, logic expression tables, and assigned input vectors, and wherein the VSS module is configured to splice input state vectors into components and to recombine computed output vector data into the deterministic data bus.
13. The logic simulation system of claim 12, wherein the VSS module coupled to the real time computational logic processor comprises a RAM based FIFO configured to sort output vector data based on time of change before the output vector is released to the deterministic data bus.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A cooling device, comprising:
a cooling unit having horizontally extending fluid guide channels with fins extending between said guide channels, said guide channels having first and second ends;
a first housing part formed as part of said cooling unit, and having a first collecting space adjacent said first ends of said guide channels, a filter chamber located therein, a partition wall within the first housing part adjacent to and separating the first collecting space from the filter chamber, and a through-opening extending through said partition wall;
a second housing part formed as a part of said cooling unit and having a second collecting space adjacent said second ends of said guide channels;
an outlet extending from said second housing part and opening into said second collecting space;
an inlet extending from said first housing part and opening into said filter chamber; and
a filter element mounted within said filter chamber and sealed to said through-opening;
whereby unfiltered fluid flows through said inlet and into said filter chamber, through said filter element, out said through-opening and into said first collecting space, through said first ends into and through said fluid guide channels, through said second ends into said second collecting space, and out said outlet.
2. A cooling device according to claim 1 wherein
said cooling unit is a plate shaped finned cooler.
3. A cooling device according to claim 1 wherein
said housing parts are formed of sheet metal.
4. A cooling device according to claim 1 wherein
said housing parts are castings.
5. A cooling device according to claim 1 wherein
said filter chamber is cylindrical;
said inlet opens in an upper portion of said filter chamber; and
said outlet opens in a lower portion of said second collecting space.
6. A cooling device according to claim 1 wherein
said filter chamber is integral with said first housing part.
7. A cooling device according to claim 1, wherein
at least two bypass valves are between said filter chamber and said first collecting space, said valves responding to different volumetric flows.
8. A cooling device according to claim 1 wherein
said filter element is formed of incineratable material and conducts fluid from outside to inside thereof.
9. A cooling device according to claim 1 wherein
a motor-fan unit is connected to said cooling unit.
10. A cooling device according to claim 1 wherein
said motor-fan unit is connected to a front side of said cooling unit.
11. A cooling device according to claim 1 wherein
a sealing cover seats said filter chamber; and
a connecting point for a fouling indicator is provided on said filter chamber.
12. A cooling device according to claim 1 wherein
said filter chamber extends along said partition wall; and
said partition wall is free of fins.