1. A method, comprising:
at a processor,
configuring a shared buffer to support processing of a first read stream and a second read stream, wherein the first read stream is associated with a first video codec format, and wherein the second read stream is associated with a second video codec format different than the first video codec format;
determining a first buffer write address within the shared buffer in response to a memory request associated with the first read stream; and
determining a second buffer write address within the shared buffer in response to a memory request associated with the second read stream, wherein the second buffer write address is different than the first buffer write address,
wherein the configuration data specifies the first buffer write address and the second buffer write address.
2. The method of claim 1, further comprising:
writing pixel data to the first buffer write address; and
reading the pixel data from the shared buffer.
3. The method of claim 2, further comprising:
writing second pixel data to the second buffer write address; and
reading the second pixel data from the shared buffer.
4. The method of claim 1, wherein the shared buffer comprises a pre-fetch buffer.
5. The method of claim 1, wherein the shared buffer comprises cache memory.
6. (canceled)
7. (canceled)
8. A method, comprising:
at a processor,
configuring a shared buffer to support processing of a first read stream, wherein the first read stream is associated with a first video codec format;
determining a first buffer write address within the shared buffer in response to a memory request associated with the first read stream;
reconfiguring the shared buffer to support processing of a second read stream, wherein the second read stream is associated with a second video codec format; and
determining a second buffer write address within the shared buffer in response to a memory request associated with the second read stream,
wherein the first configuration data specifies the first buffer write address, and wherein the second configuration data specifies the second buffer write address.
9. The method of claim 8, further comprising before reconfiguring the shared buffer to support processing of the second read stream:
writing pixel data to the first buffer write address; and
reading the pixel data from the shared buffer.
10. The method of claim 9, further comprising after reconfiguring the shared buffer to support processing of the second read stream:
writing second pixel data to the second buffer write address; and
reading the second pixel data from the shared buffer.
11. The method of claim 8, wherein the shared buffer comprises a pre-fetch buffer.
12. The method of claim 8, wherein the shared buffer comprises cache memory.
13. (canceled)
14. (canceled)
15. A system, comprising:
an integrated circuit (IC) including internal memory, the IC further including logic configured to:
configure a shared buffer within the internal memory to support processing of a first read stream, wherein the first read stream is associated with a first video codec format;
determine a first buffer write address within the shared buffer in response to a memory request associated with the first read stream;
reconfigure the shared buffer to support processing of a second read stream, wherein the second read stream is associated with a second video codec format;
determine a second buffer write address within the shared buffer in response to a memory request associated with the second read stream;
configure the shared buffer in response to the first configuration data; and
reconfigure the shared buffer in response to the second configuration data.
16. The system of claim 15, further comprising:
external memory coupled to the IC, the external memory to store first pixel data and second pixel data, wherein the first pixel data is associated with the first read stream, and wherein the second pixel data is associated with the second read stream.
17. The system of claim 16, wherein the logic is further configured to:
write the first pixel data to the first buffer write address; and
write the second pixel data to the second buffer write address.
18. (canceled)
19. (canceled)
20. The system of claim 15, wherein the shared buffer comprises a pre-fetch buffer.
21. The system of claim 15, wherein the internal memory comprises cache memory.
22. A non-transitory article comprising a computer program product having stored therein instructions that, if executed, result in:
at a processor,
configuring a shared buffer to support processing of a first read stream and a second read stream, wherein the first read stream is associated with a first video codec format, and wherein the second read stream is associated with a second video codec format different than the first video codec format;
determining a first buffer write address within the shared buffer in response to a memory request associated with the first read stream; and
determining a second buffer write address within the shared buffer in response to a memory request associated with the second read stream, wherein the second buffer write address is different than the first buffer write address,
wherein the configuration data specifies the first buffer write address and the second buffer write address.
23. non-transitory article of claim 22, further having stored therein instructions that, if executed, result in:
writing pixel data to the first buffer write address; and
reading the pixel data from the shared buffer.
24. non-transitory article of claim 23, further having stored therein instructions that, if executed, result in:
writing second pixel data to the second buffer write address; and
reading the second pixel data from the shared buffer.
25. non-transitory article of claim 22, wherein the shared buffer comprises a pre-fetch buffer.
26. non-transitory article of claim 22, wherein the shared buffer comprises cache memory.
27. (canceled)
28. (canceled)
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A vapor deposition method of an organic compound, said method comprising:
accommodating a mixture of an organic compound powder with one of a powder and crushed particles of at least one of a ceramic, a metal, and a metal coated with a ceramic in a receptacle; and
heating said receptacle which accommodates said mixture, in a vacuum, so that said organic compound is sublimated and vaporized, and is deposited onto an object surface so as to form a thin organic compound layer thereon.
2. The vapor deposition method of an organic compound according to claim 1, wherein a mixing ratio of the organic compound powder and at least one of the ceramic, the metal, and the metal coated with a ceramic is in the range of 1:50 to 50:1 in volume.
3. The vapor deposition method of an organic compound according to claim 1, wherein the grain diameter of the powder or crushed particles of the ceramic, the metal and the metal coated with a ceramic is in the range of 0.01 m to 6 mm.
4. The vapor deposition method of an organic compound according to claim 1, wherein the ceramic comprises a porous ceramic material.
5. The vapor deposition method of an organic compound according to claim 1, wherein the ceramic comprises one of a metal oxide, a metal nitride, a carbide and carbon.
6. The vapor deposition method of an organic compound according to claim 5, wherein the ceramic comprises one of an aluminum nitride, silicon carbide and carbon.
7. The vapor deposition method of an organic compound according to claim 1, wherein the organic compound is used to form an organic electroluminescent element.
8. The vapor deposition method of an organic compound according to claim 1, wherein the receptacle is one of a crucible and a boat.
9. A refinement method of an organic compound, said method comprising:
accommodating a mixture of an organic compound powder with one of a powder and crushed particles of at least one of a ceramic, a metal, and a metal coated with a ceramic in a receptacle; and
heating said receptacle which accommodates said mixture, in a vacuum, so that said organic compound is sublimated and vaporized to extract the organic compound.
10. The refinement method of an organic compound according to claim 9, wherein a mixing ratio of the organic compound powder and at least one of the ceramic, the metal, and the metal coated with a ceramic is in the range of 1:50 to 50:1 in volume.
11. The refinement method of an organic compound according to claim 9, wherein the grain diameter of the powder or crushed particles of the ceramic, the metal, and the metal coated with a ceramic is in the range of 0.01 m to 6 mm.
12. The refinement method of an organic compound according to claim 9, wherein the ceramic comprises a porous ceramic material.
13. The refinement method of an organic compound according to claim 9, wherein the ceramic comprises one of a metal oxide, a metal nitride, a carbide and carbon.
14. The refinement method of an organic compound according to claim 13, wherein the ceramic comprises one of an aluminum nitride, silicon carbide and carbon.
15. The refinement method of an organic compound according to claim 9, wherein the organic compound is used to form an organic electroluminescent element.
16. The refinement method of an organic compound according to claim 9, wherein the receptacle is one of a crucible and a boat.