1. A method of digital watermark processing, the method comprising:
receiving a content signal;
performing a watermark decoding on the content signal;
from the watermark decoding, determining a watermark state of the content signal;
evaluating a watermarking rule based on the watermark state to determine watermark encoding to apply to the content signal to comply with the watermarking rule; and
performing the watermark encoding on the content signal to embed a digital watermark layer into the content signal;
wherein the watermark rule enforces a priority of plural watermark layers by determining when to overwrite a previously embedded watermark with a new watermark layer based on the watermark state and a determined user goal;
wherein the determined user goal comprises embedding watermark information to signal an event in the content signal to which a desired behavior triggered by the digital watermark layer is to be synchronized.
2. The method of claim 1 wherein the watermark rule manages use of a limited bandwidth within the content signal for carrying plural watermark layers by selecting between overwriting a pre-existing watermark layer, and embedding a new watermark layer that co-exists with the pre-existing watermark layer.
3. The method of claim 1 wherein the watermark rule specifies that a distributor identifier and time stamp are to be embedded in the content signal and indexed to a corresponding content identifier for a portion of the content signal in which the distributor identifier and time stamp are embedded.
4. The method of claim 1 wherein the watermark state is determined by detecting a watermark protocol of a watermark embedded in the content signal.
5. The method of claim 4 wherein the watermark protocol is determined from detection of embedded synchronization signals in the content signal.
6. The method of claim 1 wherein the digital watermark layer is multiplexed within the content signal with a preexisting watermark layer by frequency multiplexing frequency components of the digital watermark layer with frequency components of the preexisting watermark layer.
7. The method of claim 1 wherein the watermark encoding comprising encoding the watermark layer so that the watermark layer overwrites a preexisting digital watermark layer, and information from the preexisting watermark layer is indexed to a information in the digital watermark layer in a database.
8. A non-transitory computer readable medium on which is stored instructions, which, when executed by a computer, perform a method of digital watermark processing on an electronic content signal, the method comprising:
performing a watermark decoding on the content signal;
from the watermark decoding, determining a watermark state of the content signal;
evaluating a watermarking rule based on the watermark state to determine watermark encoding to apply to the content signal to comply with the watermarking rule; and
performing the watermark encoding on the content signal to embed a digital watermark layer into the content signal;
wherein the watermark rule enforces a priority of plural watermark layers by determining when to overwrite a previously embedded watermark with a new watermark layer based on the watermark state and a determined user goal;
wherein the determined user goal comprises embedding watermark information to signal an event in the content signal to which a desired behavior triggered by the digital watermark layer is to be synchronized.
9. A digital watermark processor, the processor comprising:
means for receiving a content signal;
means for performing a watermark decoding on the content signal;
means for determining, from the watermark decoding, a watermark state of the content signal;
means for evaluating a watermarking rule based on the watermark state to determine watermark encoding to apply to the content signal to comply with the watermarking rule; and
means for performing the watermark encoding on the content signal to embed a digital watermark layer into the content signal;
wherein the watermark rule enforces a priority of plural watermark layers by determining when to overwrite a previously embedded watermark with a new watermark layer based on the watermark state and a determined user goal;
wherein the determined user goal comprises embedding watermark information to signal an event in the content signal to which a desired behavior triggered by the digital watermark is to be synchronized.
10. The processor of claim 9 wherein the means for evaluating manages, based on the watermark rule, a use of a limited bandwidth within the content signal for carrying plural watermark layers by selecting between overwriting a pre-existing watermark layer, and embedding a new watermark layer that co-exists with the pre-existing watermark layer.
11. The processor of claim 9 wherein the watermark rule specifies that a distributor identifier and time stamp are to be embedded in the content signal and indexed to a corresponding content identifier for a portion of the content signal in which the distributor identifier and time stamp are embedded.
12. The processor of claim 9 wherein the watermark state is determined by detecting a watermark protocol of a watermark embedded in the content signal.
13. The processor of claim 12 wherein the watermark protocol is determined from detection of embedded synchronization signals in the content signal.
14. The processor of claim 12 wherein the digital watermark layer is multiplexed within the content signal with a preexisting watermark layer by frequency multiplexing frequency components of the digital watermark layer with frequency components of the preexisting watermark layer.
15. The processor of claim 12 wherein the watermark encoding comprising encoding the digital watermark layer so that the watermark layer overwrites a preexisting digital watermark layer, and information from the preexisting watermark layer is indexed to a information in the digital watermark layer in a database.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A phase change memory device, comprising:
a memory cell array comprising a plurality of memory cells; and
a write driver circuit adapted to provide a set current and a reset current to a selected memory cell among the plurality of memory cells;
wherein the write driver circuit comprises a set current driver adapted to provide the set current and a reset current driver adapted to provide the reset current.
2. The phase change memory device of claim 1, wherein the write driver circuit further comprises:
a pulse controller receiving one of a set pulse and a reset pulse according to a logic level of an input data signal and generating a set control signal with a logic level based on the logic level of the input data and a logic level of the set pulse, and generating a reset control signal with a logic level based on a logic level of the input data signal and a logic level of the reset pulse;
a set current controller operating in response to the set control signal, and controlling a magnitude of the set current in response to a set direct current (DC) voltage; and
a reset current controller operating in response to the reset control signal and controlling a magnitude of the reset current in response to a reset DC voltage.
3. The phase change memory device of claim 2, wherein the pulse controller comprises:
a first transfer gate receiving the set pulse and selectively outputting the set pulse according to the logic level of the input data signal;
a second transfer gate receiving the reset pulse and selectively outputting the set pulse according to the logic level of the input data signal;
a set control signal generator generating the set control signal with the logic level based on the logic level of the input data and the logic level of the set pulse; and
a reset control signal generator generating the reset control signal with the logic level based on the logic level of the input data signal and the logic level of the reset pulse.
4. The phase change memory device of claim 2, wherein the set current controller comprises:
a positive metal-oxide semiconductor (PMOS) transistor having a first terminal receiving a power source voltage, a second terminal connected to a set node, and a gate connected to the set node;
a first negative metal-oxide semiconductor (NMOS) transistor having a first terminal connected to the set node, a second terminal, and a gate receiving the set DC voltage; and
a second NMOS transistor having a first terminal connected to the set node, a second terminal connected to ground, and a gate receiving the set control signal.
5. The phase change memory device of claim 4, wherein the set current controller further comprises:
a set current cut-off circuit adapted to prevent the set current driver from generating the set current by controlling a logic level of the set node based on a logic level of the set pulse.
6. The phase change memory device of claim 5, wherein the set current cutoff circuit comprises a PMOS transistor having a first terminal receiving the power source voltage, a second terminal connected to the set node, and a gate controlled by the logic state of the set pulse or the reset pulse.
7. The phase change memory device of claim 4, wherein the set current driver controls a magnitude of the set current according to a voltage level apparent on the set node.
8. The phase change memory device of claim 2, wherein the reset current controller comprises:
a positive metal-oxide semiconductor (PMOS) transistor having a first terminal receiving a power source voltage, a second terminal connected to a reset node, and a gate receiving the reset control signal; and
a transfer gate adapted to selectively transfer the reset DC voltage to the reset node based on a logic level of the reset control signal.
9. The phase change memory device of claim 8, wherein the reset DC voltage has a level of 0V.
10. The phase change memory device of claim 8, wherein the reset current driver controls a magnitude of the reset current according to a voltage level apparent on the reset node.
11. The phase change memory device of claim 10, wherein the reset current driver comprises a PMOS transistor having a gate connected to the reset node, a first terminal receiving the power source voltage, and a second terminal connected to the selected memory cell via a data line.
12. The phase change memory device of claim 1, wherein each of the plurality of memory cells comprises:
a memory element comprising a phase change material; and
a select element for selecting the memory cell.
13. The phase change memory device of claim 12, wherein the select element comprises a diode connected between the memory element and a word line.
14. The phase change memory device of claim 12, wherein the select element comprises a negative metal-oxide semiconductor (NMOS) transistor having a first terminal connected to the memory element, a second terminal connected to ground, and a gate connected to a word line.
15. A method of programming a phase change memory device, the memory device comprising a memory cell array comprising a plurality of memory cells, and a write driver circuit comprising a set current driver and a reset current driver respectively providing a set current and a reset current to a selected memory cell among the plurality of memory cells, the method comprising:
receiving one of a set pulse and a reset pulse according to a logic level of an input data signal;
generating a reset control signal according to the logic level of the input data signal and a logic level of the reset pulse; and
upon receiving the reset pulse, receiving a reset direct current (DC) voltage according to the logic level of the reset control signal and providing the reset current to the selected memory cell in response to the reset DC voltage.
16. The method of claim 15, wherein the reset current driver controls a magnitude of the reset current according to a level of the reset DC voltage.
17. The method of claim 15, further comprising:
upon receiving the set pulse, generating a set control signal according to the logic level of the input data signal and a logic level of the set pulse and providing the set current to the selected memory cell in response to the set control signal and a set DC voltage.
18. The method of claim 17, wherein the set current driver controls a magnitude of the set current according to a level of the set DC voltage.