1. An apparatus comprising:
a plurality of interrupt inputs, a normal interrupt output and an error interrupt output, both interrupt outputs coupled to one or more of the plurality of interrupt inputs;
an interrupt status queue coupled to one of the plurality of interrupt inputs;
a status register coupled to the status queue and to the normal interrupt output;
a normal interrupt register coupled to normal interrupt output; and
a vectored interrupt control register coupled to the normal interrupt register.
2. The apparatus of claim 1 wherein the status register is burst readable.
3. The apparatus of claim 1 wherein the status queue is a first-in, first-out (FIFO) queue.
4. The apparatus of claim 1, wherein the interrupt input coupled to the interrupt queue is also coupled to an analog front end (AFE).
5. The apparatus of claim 4 wherein the interrupts input to the interrupt queue are latency-sensitive interrupts.
6. The apparatus of claim 1, further comprising a control processor coupled to the vectored interrupt control register via an auxiliary bus.
7. The apparatus of claim 1, further comprising an error interrupt register coupled to the error interrupt output.
8. The apparatus of claim 7 wherein the error interrupt register is coupled to the vectored interrupt control register.
9. An apparatus comprising:
a plurality of protocol engines, each having an interrupt handler including:
a plurality of interrupt inputs, a normal interrupt output and an error interrupt output, both interrupt outputs being coupled to one or more of the plurality of interrupt inputs,
an interrupt status queue coupled to one of the plurality of interrupt inputs,
a status register coupled to the status queue and to the normal interrupt output, and
a normal interrupt register coupled to normal interrupt output; and
a vectored interrupt control register coupled to the plurality of normal interrupt registers via an OR gate.
10. The apparatus of claim 9 wherein the status register is burst readable.
11. The apparatus of claim 9 wherein the status queue is a first-in, first-out (FIFO) queue.
12. The apparatus of claim 9, wherein the interrupt input coupled to the interrupt status queue originates from an analog front end (AFE).
13. The apparatus of claim 12 wherein the interrupts input to the interrupt status queue are latency-sensitive interrupts.
14. The apparatus of claim 9, further comprising a control processor coupled to the vectored interrupt control register via an auxiliary bus.
15. A process comprising:
providing protocol engine having an interrupt handler including:
an interrupt status queue coupled to one of a plurality of interrupt inputs,
a status register coupled to the status queue and to the normal interrupt output, and
a normal interrupt register coupled to normal interrupt output;
writing a plurality of interrupts to the interrupt status queue;
reading one or more of the interrupts from the interrupt status queue in first in, first out (FIFO) order and writing the interrupts to the status register;
reading the one or more interrupts from the status register and writing them to the normal interrupt register; and
reading the one or more interrupts from the normal interrupt register and writing them to a vectored interrupt control register.
16. The process of claim 15 wherein writing a plurality of interrupts to the interrupt status queue comprises:
detecting whether each interrupt to be entered in the interrupt status queue duplicates an interrupt already in the queue; and
writing each non-duplicate interrupt received to the interrupt status queue in the order received.
17. The process of claim 15 wherein reading one or more interrupts from the interrupt status queue in FIFO order comprises:
reading one or more interrupts from the interrupt status queue in FIFO order;
clearing the read interrupts from the queue; and
advancing a queue pointer to the next interrupt to be read in FIFO order.
18. The process of claim 15 wherein reading one or more interrupts from the status register comprises:
reading one or more interrupts from the status register;
clearing the read interrupts from the status register; and
advancing a pointer to the next interrupt in the register to be read.
19. The process of claim 15 wherein reading one or more interrupts from the status register comprises burst reading the interrupts.
20. The process of claim 15 wherein writing a plurality of interrupt to the interrupt status queue comprises writing latency-sensitive interrupts to the queue.
21. A system comprising:
a control processor and a memory coupled to each other by a main bus;
a protocol engine coupled to the main bus, the protocol engine having an interrupt handler including:
a plurality of interrupt inputs, a normal interrupt output and an error interrupt output, both interrupt outputs being coupled to one or more of the plurality of interrupt inputs,
an interrupt status queue coupled to one of the plurality of interrupt inputs,
a status register coupled to the interrupt status queue and to the normal interrupt output, and
a normal interrupt register coupled to normal interrupt output;
a vectored interrupt control register coupled to the normal interrupt register; and
an auxiliary bus coupling the vectored interrupt control register to the control processor.
22. The system of claim 21, further comprising at least one additional protocol engine, wherein the normal interrupt registers of the protocol engines are coupled to the vectored interrupt control register via an OR gate.
23. The system of claim 22 wherein the status queue is a first-in, first-out (FIFO) queue.
24. The system of claim 21, wherein the interrupt input coupled to the interrupt queue is also coupled to an analog front end (AFE).
25. The system of claim 24 wherein the interrupts input to the interrupt queue are latency-sensitive interrupts.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A human-machine interface system comprising:
a network; and
a plurality of nodes that are interconnected with the network, wherein human-machine interface functions are actualized in forms of distributed objects allocated to the nodes and are realized by mediating interaction between the nodes.
2. A human-machine interface system according to claim 1, wherein each of the plurality of nodes corresponds to an application node that performs inputoutput functions of information for a human user in execution of a specific application by way of the human-machine interface function thereof, a service node that processes the information input to or output from the application node, or a composite node that acts as an application node andor a service node.
3. A human-machine interface system according to claim 2, wherein there are provided a low-order service node or a low-order composite node that performs data processing depending upon expression media such as sound and picture as well as a high-order service node or a high-order composite node that performs data processing independently from the expression media, so that the high-order service node or the high-order composite node is commonly shared by the low-order service node or the low-order composite node that highly depends upon different expression media respectively.
4. A human-machine interface system according to claim 2 or 3 wherein the application node or the composite node sends a start request of a prescribed service and its processing data to the service node or another composite node which in turn produces input information or output information for the application node or the composite node.
5. A human-machine interface system according to any one of claims 1 to 4, wherein each of the plurality of nodes has a hierarchical layered structure in execution of software, which is configured by arranging from a top place to a bottom place, an application node or a service node, a proxy corresponding to a high-order portion of the distributed object, a object transport structure and a remote class reference structure corresponding to a low-order portion of the distributed object, a network transport layer and a network interface circuit.
6. A computer-readable media storing programs that cause nodes corresponding to computers or processors interconnected with a network to actualize a human-machine interface system based on a distributed object model, wherein human-machine interface functions are actualized in forms of distributed objects allocated to the nodes and are realized by mediating interaction between the nodes.
7. A human-machine interface system comprising:
a network;
a plurality of nodes that are interconnected with the network, wherein human-machine interface functions are actualized in forms of distributed objects allocated to the nodes and are realized by mediating interaction between the nodes,
wherein each of the nodes corresponds to an application node that performs a prescribed application for a human user by way of a human-machine interface function thereof or a service node that provides a specific service in relation with execution of the prescribed application.
8. A human-machine interface system according to claim 7, wherein there are provided a low-order service node that performs data processing depending on expression media such as sound and picture and a high-order service node that performs data processing independently of the expression media.
9. A human-machine interface system according to claim 7, wherein each of the nodes has a hierarchical layered structure in execution of software, which is configured by arranging from a top to a bottom, an application object or a service object, a proxy, an object transport structure, a remote class reference structure, a network transport layer, and a network interface circuit.
10. A human-machine interface system according to claim 7, wherein the service corresponds to a speech recognition service or a speech synthesis service.