Author: claimsbot

1. Hydraulic transmitting device for vehicles, in particular, for vehicles steered by handlebars, comprising a housing with a hydraulic master cylinder, a displaceable piston being arranged in said cylinder, an actuating lever movable relative to the housing and a push rod transferring movement of the actuating lever to the piston, the push rod being supported on the actuating lever, the push rod being adjustable in the direction of a longitudinal axis as a result of rotation about said axis and the push rod being securable relative to the actuating lever in specific rotary positions around the longitudinal axis by means of a locking device,
the locking device comprising a locking element, the locking element having at least one locking vane and the at least one locking vane abutting with a locking surface on a locking section of the push rod deviating from a circular cross section in a flexible manner and acted upon by a force.
2. Transmitting device as defined in claim 1, wherein the push rod is accommodated in an internal thread of the locking device with a threaded section.
3. Transmitting device as defined in claim 2, wherein the locking device is connected non-rotatably to the lever.
4. Transmitting device as defined in claim 1, wherein the push rod is accommodated in an internal thread of a bearing member with a threaded section.
5. Transmitting device as defined in claim 3, wherein the push rod is supported on the actuating lever by the bearing member.
6. Transmitting device as defined in claim 4, wherein the locking device comprises a locking element connected non-rotatably to the bearing member such that the push rod is securable relative to the bearing member in specific rotary positions around the longitudinal axis.
7. Transmitting device as defined in claim 4, wherein the bearing member andor the locking element are connected non-rotatably to the lever.
8. Transmitting device as defined in claim 1, wherein the locking element is designed so as to engage essentially around the locking section.
9. Transmitting device as defined in claim 1, wherein the locking element has several locking vanes.
10. Transmitting device as defined in claim 9, wherein the locking vanes abut on the locking section at several areas arranged at a distance from one another in circumferential direction.
11. Transmitting device as defined in claim 9, wherein the locking section is located between two locking vanes.
12. Transmitting device as defined in claim 11, wherein the locking vanes are designed in the shape of shells.
13. Transmitting device as defined in claim 9, wherein each locking vane is designed as a partial section of a one-piece locking element member forming the locking element.
14. Transmitting device as defined in claim 13, wherein the locking vanes are fixed radially on a retaining area of the locking element facing the bearing member and are elastically movable radially to the longitudinal axis with an end facing away from the bearing member.
15. Transmitting device as defined in claim 4, wherein the locking element comprises at least one locking vane and a support area supporting it.
16. Transmitting device as defined in claim 15, wherein the at least one locking vane is an arm of a U-shaped spring clip.
17. Transmitting device as defined in claim 1, wherein the locking section has radially projecting areas and between them areas set back radially.
18. Transmitting device as defined in claim 17, wherein the radially projecting areas are designed as edges.
19. Transmitting device as defined in claim 17, wherein the areas set back radially are designed as flat sides.
20. Transmitting device as defined in claim 17, wherein the locking section is designed in cross section as a polygon.
21. Transmitting device as defined in claim 1, wherein the locking element has a receiving means for the bearing member.
22. Transmitting device as defined in claim 21, wherein the bearing member is inserted into the receiving means.
23. Transmitting device as defined in claim 21, wherein the receiving means is connectable to the bearing member in an interlocking manner.
24. Transmitting device as defined in claim 23, wherein the receiving means has retaining clips interlockable with the bearing member.
25. Transmitting device as defined in claim 24, wherein the retaining clips engage around the bearing member on the circumferential side.
26. Transmitting device as defined in claim 1, wherein the bearing member is guided in a non-rotational manner in relation to the actuating lever.
27. Transmitting device as defined in claim 1, wherein the bearing member is supported on a pressure arm of the actuating lever.
28. Transmitting device as defined in claim 26, wherein the bearing member is supported on the pressure arm so as to be pivotable.
29. Transmitting device as defined in claim 28, wherein the bearing member is mounted on the pressure arm by at least one rotary bearing.
30. Transmitting device as defined in claim 27, wherein the bearing member is supported on a guide surface of the pressure arm.
31. Transmitting device as defined in claim 27, wherein the bearing member is guided on the pressure arm in a non-rotational manner by a guide element engaging on the pressure arm.
32. Transmitting device as defined in claim 31, wherein the guide element is guided on an outer surface of the pressure arm.
33. Transmitting device as defined in claim 32, wherein the outer surface is designed as a guide surface cylindrical in relation to an axis.
34. Transmitting device as defined in claim 1, wherein the locking element has a receiving means for a protective bellows.
35. Transmitting device as defined in claim 34, wherein a retaining ring of the protective bellows acts on the locking vanes in the direction of the locking section, said retaining ring being radially elastic and fixable to the locking element.
36. Transmitting device as defined in claim 34, wherein the retaining ring of the protective bellows engages on the locking element in an end area facing away from the bearing member.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus for adjusting a rail on a rail substructure, comprising:
a support plate which supports the rail and is held on the rail substructure by means of bolts arranged on both sides of the rail,
two rotatable adjusting units, each associated with one of the bolts for adjusting the support plate relative to the bolts, each of the adjusting units including two members that are rotatable relative to one another to perform an adjustment operation, and
a gear mechanism which couples the two adjusting units for synchronously adjusting the two adjusting units.
2. The apparatus according to claim 1, wherein the adjusting units each have an eccentric for a lateral adjustment of the rail.
3. The apparatus according to claim 2, wherein the gear mechanism comprises two toothed rings which are each formed at the eccentric of one of the adjusting units and are coupled to one another by an intermediate gear.
4. The apparatus according to claim 2, wherein each eccentric is rotatably journaled in a support structure which is rigidly connected to the support plate in a lateral direction, and each eccentric has a bushing arranged eccentrically relative to the axis of rotation and penetrated by the associated bolt.
5. The apparatus according to claim 4, wherein the bolts are each screwed into a dowel which has a top end and is anchored in the rail substructure, and the bushings engage the top ends of the dowels.
6. The apparatus according to claim 5, wherein the rail substructure is formed by a flat track bed made of concrete.
7. The apparatus according to claim 1, wherein each adjusting unit has a pair of threaded sleeves held in thread-engagement with one another for a height adjustment of the support plate.
8. The apparatus according to claim 7, wherein the gear mechanism has two toothed rings which are each formed on one of the threaded sleeves of each adjusting unit and are coupled with one another by an intermediate gear.
9. The apparatus according to claim 7, wherein the adjusting units each have an eccentric for a lateral adjustment of the rail, the gear mechanism comprises a first pair of toothed rings which are each formed at the eccentric of one of the adjusting units and are coupled to one another by a first intermediate gear, and the threaded sleeves of each adjusting unit comprise a base sleeve arranged coaxially with the axis of rotation of the eccentric and supported on said eccentric, and a telescopic sleeve which supports the support plate.
10. The apparatus according to claim 9, wherein the gear mechanism has a second pair of toothed rings which are each formed on one of the threaded sleeves of each adjusting unit and are coupled with one another by a second intermediate gear, said toothed rings of the second pair being formed on the telescopic sleeves which are rotatably journaled in the support plate, and the base sleeves being held non-rotatably relative to the support plate.
11. The apparatus according to claim 10, wherein a non-rotatable third base sleeve is arranged on the base plate between the base sleeves of the two adjusting units, the third base sleeve being in thread-engagement with a third telescopic sleeve supporting the support plate, and the second intermediate gear, which couples the toothed rings of the telescopic sleeves of the adjusting units, is formed by a toothed ring on the third telescopic sleeve.
12. The apparatus according to claim 11, wherein a ratio between a thread pitch of the third telescopic sleeve and a thread pitch of the other telescopic sleeves is equal to a ratio between a pitch circle of the second intermediate gear and pitch circles of the toothed rings of the telescopic sleeves of the adjusting units.
13. The apparatus according to claim 3, comprising an adjusting tool having a shaft adapted to be inserted from above through an opening of the support plate into the apparatus and driving a gear which meshes with one of the toothed rings.
14. The apparatus according to claim 9, comprising an adjusting tool having a shaft adapted to be inserted from above into the apparatus, and a gear mounted on said shaft, wherein the support plate has a first opening arranged near a first one of said adjusting units such that the gear of the adjusting tool, when inserted in the first opening, meshes with the toothed ring of the eccentric of said first adjusting unit, and the support plate has a second opening and a receptacle arranged near a second one of said adjusting units such that the gear of the adjusting tool, when inserted in the second opening and supported in said receptacle, meshes with the toothed ring of the telescopic sleeve of said second adjusting unit.
15. The apparatus according to claim 1, wherein the rail is fixed on the support plate by flat, rigid clamping plates adapted to be biased against a rail base of the rail.
16. The apparatus according to claim 15, wherein the clamping plates are arranged on said bolts and are adapted to be biased against the rail base through heads of said bolts.
17. The apparatus according to claim 16, wherein each of said clamping plates has a bottom side provided with a noise-absorbing and high-friction coating.
18. The apparatus of claim 3, comprising an adjusting tool having a shaft adapted to be inserted from above through an opening of the support plate into the apparatus and driving a gear which meshes with the intermediate gear.
19. The apparatus of claim 2, wherein each eccentric is rotatably journaled in a base plate which is fixedly coupled with the support plate in a lateral direction, and each eccentric has a bushing arranged eccentrically relative to the axis of rotation and penetrated by the associated bolt.

1. An integrated circuit, comprising:
an array of memory cells;
volatile storage;
non-volatile storage; and
a circuit configured to sense first addresses of first defective memory cells from the non-volatile storage to obtain sensed first addresses, wherein the circuit detects second defective memory cells via the sensed first addresses and stores second addresses of the second defective memory cells in the volatile storage and the non-volatile storage.
2. The integrated circuit of claim 1, wherein the first addresses are stored in first entries in the volatile storage and the second addresses are stored in second entries in the volatile storage, which are different than the first entries in the volatile storage.
3. The integrated circuit of claim 2, wherein the sensed first addresses are stored in the first entries in the volatile storage.
4. The integrated circuit of claim 2, wherein the first entries are grayed out prior to storing the second addresses in the non-volatile storage.
5. The integrated circuit of claim 2, wherein the first addresses are stored in third entries in the non-volatile storage and the second addresses are stored in fourth entries in the non-volatile storage, which are different than the third entries in the non-volatile storage.
6. The integrated circuit of claim 5, wherein the first entries correspond to the third entries and the second entries correspond to the fourth entries.
7. The integrated circuit of claim 5, wherein the second addresses are stored in the non-volatile storage via the volatile storage and the second entries correspond to the fourth entries.
8. The integrated circuit of claim 1, wherein the array of memory cells includes banks of memory cells and the volatile storage includes sets of volatile storage elements and each of the banks of memory cells is electrically coupled to a different one of the sets of volatile storage elements.
9. The integrated circuit of claim 8, wherein the non-volatile storage includes sets of non-volatile storage elements and each of the sets of non-volatile storage elements corresponds to a different one of the banks of memory cells.
10. The integrated circuit of claim 8, wherein the circuit provides a repair status flag that indicates one of the sets of volatile storage elements is full.
11. A memory device, comprising:
an array of memory cells;
volatile storage;
non-volatile storage; and
a circuit configured to detect first defective memory cells and store first addresses of the first defective memory cells in the volatile storage and the non-volatile storage, wherein the circuit senses the first addresses stored in the non-volatile storage to obtain sensed first addresses, detects second defective memory cells via the sensed first addresses and stores second addresses of the second defective memory cells in the volatile storage and the non-volatile storage.
12. The memory device of claim 11, wherein the first addresses are stored in first entries in the volatile storage and the second addresses are stored in second entries in the volatile storage, which are different than the first entries in the volatile storage.
13. The memory device of claim 12, wherein the first entries are grayed out prior to programming the second addresses into the non-volatile storage via the volatile storage.
14. The memory device of claim 12, wherein the sensed first addresses are stored in the first entries in the volatile storage.
15. An integrated circuit, comprising:
an array of memory cells;
means for temporarily storing first addresses of first defective memory cells and second addresses of second defective memory cells;
means for non-temporarily storing the first addresses and the second addresses;
means for sensing the first addresses from the means for non-temporarily storing to obtain sensed first addresses;
means for detecting the second defective memory cells via the sensed first addresses; and
means for storing the second addresses in the means for temporarily storing and the means for non-temporarily storing.
16. The integrated circuit of claim 15, wherein the means for temporarily storing first addresses of first defective memory cells and second addresses of second defective memory cells includes:
means for temporarily storing the first addresses in first entries; and
means for temporarily storing the second addresses in second entries that are different than the first entries.
17. The integrated circuit of claim 16, wherein the means for temporarily storing first addresses of first defective memory cells and second addresses of second defective memory cells includes:
means for temporarily storing the sensed first addresses in the first entries.
18. The integrated circuit of claim 16, comprising:
means for graying out the first entries prior to storing the second addresses in the means for non-temporarily storing.
19. A method of repairing a memory, comprising:
sensing first addresses of first defective memory cells from non-volatile storage to obtain sensed first addresses;
detecting second defective memory cells via the sensed first addresses;
storing second addresses of the second defective memory cells in volatile storage; and
storing the second addresses in non-volatile storage via the volatile storage.
20. The method of claim 19, comprising:
storing the first addresses of the first defective memory cells in first entries of the volatile storage, wherein storing second addresses of the second defective memory cells in volatile storage comprises:
storing the second addresses of the second defective memory cells in second entries of the volatile storage, which are different than the first entries of the volatile storage.
21. The method of claim 20, comprising:
storing the sensed first addresses in the first entries of the volatile storage.
22. The method of claim 20, comprising:
graying out the first entries prior to storing the second addresses in the non-volatile storage via the volatile storage.
23. A method of repairing a memory, comprising:
detecting first defective memory cells;
storing first addresses of the first defective memory cells in volatile storage;
storing the first addresses of the first defective memory cells in non-volatile storage via the volatile storage;
sensing the first addresses from the non-volatile storage to obtain sensed first addresses;
detecting second defective memory cells via the sensed first addresses;
storing second addresses of the second defective memory cells in the volatile storage; and
storing second addresses of the second defective memory cells in the non-volatile storage via the volatile storage.
24. The method of claim 23, wherein:
storing first addresses of the first defective memory cells in volatile storage comprises storing the first addresses in first entries in the volatile storage;
storing second addresses of the second defective memory cells in the volatile storage comprises storing the second addresses in second entries in the volatile storage, which are different than the first entries in the volatile storage;
storing the first addresses of the first defective memory cells in non-volatile storage comprises storing the first addresses in third entries in the non-volatile storage; and
storing second addresses of the second defective memory cells in the non-volatile storage comprises storing the second addresses in fourth entries in the non-volatile storage, which are different than the third entries in the non-volatile storage.
25. The method of claim 24, wherein the first entries correspond to the third entries and the second entries correspond to the fourth entries and comprising:
graying out the first entries prior to storing the second addresses in the fourth entries of the non-volatile storage via the volatile storage.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device comprising:
a silicon substrate constituting a base;
a semiconductor chip provided on said base and having a first main surface on which a plurality of electrode pads is provided, a surface protection film formed on said first main surface such that said electrode pads are exposed, a second main surface which opposes said first main surface, and a plurality of side surfaces between the surface of said surface protection film and said second main surface;
an insulating extension portion formed on said base so as to surround said side surfaces of said semiconductor chip;
a plurality of wiring patterns electrically connected to said electrode pads and extended from said electrode pads to the surface of said extension portion;
a plurality of electrode posts formed on portions of said wiring patterns, the portions of said wiring patterns being arranged on the insulating extension portion;
a sealing resin formed on said wiring patterns, said insulating extension potion, and the side surfaces of the electrode posts; and
a plurality of external terminals provided on said electrode posts.
2. The semiconductor device according to claim 1, wherein said electrode posts are formed from a conductive material.
3. The semiconductor device according to claim 1, wherein said external terminals are formed as solder balls.
4. The semiconductor device according to claim 1, wherein portions of the wiring patterns on a boundary and vicinity thereof between semiconductor chip and the extension portion are formed wider or more thickly than other portions of said wiring patterns.
5. The semiconductor device according to claim 1, wherein said extension portion is formed from an insulating material having a greater molding shrinkage than the molding shrinkage of said sealing portion.
6. The semiconductor device according to claim 5, wherein said extension portion is formed from an insulating liquid resin having a linear expansion coefficient in a temperature range than glass transition point of less than 1.5\xd710\u22125\xb0 C. and a modulus of elasticity within a range of 7.8 to 22 GPa.
7. The semiconductor device according to claim 1, wherein said semiconductor chip is in contact with said silicon substrate.
8. A semiconductor device comprising:
a silicon substrate constituting a base;
an extension portion having a concave portion which is formed from an insulating material and provided on said base;
a semiconductor chip having a first main surface on which a plurality of ejectrode pads are provided, a surface protection film formed on said first main surface such that said electrode pads are exposed, a second main surface which opposes said first main surface, and a plurality of side surfaces between the surface of said surface protection film and said second main surface, which is provided within the concave portion of said extension portion such that said side surfaces are surrounded by said extension portion;
a plurality of wiring patterns electrically connected to said electrode pads and extended from said electrode pads to the surface of said extension portion;
a plurality of electrode posts formed on portions of said wiring patterns, the portions of said wiring patterns being arranged on the extension portion;
a sealing resin formed on said wiring patterns, said extension potion, and the side surfaces of the electrode posts; and
a plurality of external terminals provided on said electrode posts.
9. The semiconductor device according to claim 8, wherein said electrode posts are formed from a conductive material.
10. The semiconductor device according to claim 8, wherein portions of the wiring patterns on a boundary and vicinity thereof between semiconductor chip and the extension portion are formed wider or more thickly than other portions of said wiring patterns.
11. The semiconductor device according to claim 8, wherein said extension portion is formed from an insulating material having a greater molding shrinkage than the molding shrinkage of said sealing portion.
12. The semiconductor device according to claim 11, wherein said extension portion is formed from an insulating liquid resin having a linear expansion coefficient in a lower temperature range than glass transition point of less than 1.5\xd710\u22125\xb0 C. and a modulus of elasticity within a range of 7.8 to 22 GPa.
13. The semiconductor device according to claim 8, wherein said extension portion is in contact with said silicon substrate.
14. A semiconductor device comprising:
a silicon substrate constituting a base;
an insulating extension portion provided on said base and having a concave portion having inclined inside walls;
a semiconductor chip comprising a first main surface on which a plurality of electrode pads is provided, a surface protecting film formed on said first main surface such that said electrode pads are exposed, a second main surface which opposes said first main surface, and a plurality of side surfaces between the surface of said surface protecting film and said second main surface, which is provided within the concave portion of said extension portion such that said side surfaces are surrounded by said extension portion;
an insulating film formed over the surface of said inside walls, the surface of said extension portion, and said surface protecting film such that a part of said electrode pads is exposed;
a plurality of wiring patterns formed on said insulating film, electrically connected to said electrode pads, and extended from said electrode pads to the surface of said extension portion;
a plurality of electrode posts formed on portions of said wiring patterns, the portions of said wiring patterns being arranged on the insulating extension portion;
a sealing resin formed on said wiring patterns, said insulating extension potion, and the side surfaces of the electrode posts; and
a plurality of external terminals provided on said electrode posts.
15. The semiconductor device according to claim 14, wherein said extension portion is formed from an insulating material having a greater molding shrinkage than the molding shrinkage of said sealing portion.
16. The semiconductor device according to claim 15, wherein said extension portion is formed from an insulating liquid resin having a linear expansion coefficient in a lower temperature range than glass transition point of less than 1.5\xd710\u22125\xb0 C. and a modulus of elasticity within a range of 7.8 to 22 GPa.
17. The semiconductor device according to claim 14, wherein said insulating extension is in contact with said silicon substrate.