Author: claimsbot

1. A backlight module comprising:
a first optical film having high light reflection characteristics;
a second optical film spaced apart from said first optical film, and having polarization light selection transmission characteristics and light reflection characteristics;
a plurality of lampshades having high light reflection characteristics, disposed between said first optical film and said second optical film, extending in an axial direction, and arranged so that any two spaced-apart adjacent ones of said lampshades cooperate with said first and second optical films to define a light mixing chamber thereamong, thereby forming a plurality of said light mixing chambers between said first and second optical films; and
a plurality of line light sources each disposed in a corresponding one of said light mixing chambers, extending in the axial direction and mounted to a corresponding one of said lampshades for emitting light;
wherein light emitted by each of said line light sources is mixed in the corresponding one of said light mixing chambers through reflection by two corresponding spaced-apart ones of said lampshades defining the corresponding one of said light mixing chambers such that light transmitted out from the corresponding one of said light mixing chambers through said second optical film forms a surface light field.
2. The backlight module as claimed in claim 1, wherein each of said lampshades includes an elongate base wall extending in the axial direction, mounted with a corresponding one of said line light sources thereon and having opposite sides, and two extending walls extending respectively from said opposite sides of said base wall and toward a corresponding spaced-apart adjacent one of said lampshades.
3. The backlight module as claimed in claim 2, wherein said extending walls of each of said lampshades abut respectively against said first and second optical films.
4. The backlight module as claimed in claim 2, wherein, for each of said lampshades, an angle formed between said base wall and any one of said extending walls is not less than 90\xb0 but less than 180\xb0.
5. The backlight module as claimed in claim 1, wherein each of said lampshades has a light reflection rate ranging from 5% to 95%.
6. The backlight module as claimed in claim 1, wherein each of said lampshades is made from a material selected from the group consisting of polymethylmethacrylate (PMMA), polycarbonate (PC), polystyrene (PS), and polyethylene terephthalate (PET).
7. The backlight module as claimed in claim 1, wherein said first optical film has a light reflection rate greater than 80%.
8. The backlight module as claimed in claim 1, wherein said second optical film has a light transmission rate ranging from 15% to 95%, and a light reflection rate ranging from 15% to 95%.
9. The backlight module as claimed in claim 1, wherein each of said line light sources includes one of a cold cathode fluorescent (CCFL) and a light-emitting diode (LED).
10. The backlight module as claimed in claim 1, further comprising a frame body surrounding said first and second optical films.
11. The backlight module as claimed in claim 10, wherein said frame body has an inner surrounding surface with a light reflection rate greater than 80%.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of modeling for use with an integrated circuit (IC) design, the method comprising:
partitioning an edge of a shape in the IC design into a plurality of intervals; and
assigning at least one dimension to each interval;
wherein the partitioning includes:
generating a core Voronoi diagram for the shape, the core Voronoi diagram being generated based on a L\u221e metric, the L\u221e metric defining a distance between two points in the shape as the maximum of a horizontal distance and a vertical distance between the two points; and
partitioning the edge based on a core element for each vertex of the core Voronoi diagram, the core element being one of a largest possible core element and a smallest possible core element; and

wherein in the case that the core element is the largest possible core element, the intervals are as large as possible, and wherein in the case that the core element is the smallest possible core element, the intervals are as small as possible.
2. The method of claim 1, wherein the assigning is based on a Euclidean metric.
3. The method of claim 1, wherein the at least one dimension includes a width for each interval and a spacing to a neighboring shape for each interval.
4. The method of claim 1, wherein the dimension is a function of another dimension.
5. The method of claim 1, further comprising using the at least one dimension to evaluate a check rule.
6. The method of claim 5, wherein the check rule involves at least one of: a single edge, a pair of neighboring edges, and edges within more than one layer of the IC design.
7. The method of claim 1, wherein each concave vertex of the shape is an interval.

1. A semiconductor memory cell comprising:
a first bipolar device having a floating base region, a collector, and an emitter, and
a second bipolar device having a floating base region, a collector, and an emitter,
wherein the floating base region of said first bipolar device is common to the floating base region of said second bipolar device,
wherein the collector of said first bipolar device is common to the collector of said second bipolar device, and
wherein a state of said memory cell is maintained through a back-bias applied to said collector.
2. The semiconductor memory cell of claim 1, wherein said floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;
each said emitter has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and
said collector has said second conductivity type.
3. The semiconductor memory cell of claim 1, wherein said back-bias applied to said collector is a constant voltage bias.
4. The semiconductor memory cell of claim 1, wherein said back-bias applied to said collector is a periodic pulse of voltage.
5. The semiconductor memory cell of claim 1, further comprising a gate region above said floating base region.
6. The memory cell of claim 1, wherein a maximum potential that can be stored in said floating base region is increased by said applying back bias to the cell, resulting in a relatively larger memory window.
7. The memory cell of claim 1, comprising a fin structure extending from a substrate.
8. A semiconductor memory cell comprising:
a first bipolar device having a floating base region, a collector, and an emitter, and
a second bipolar device having a floating base region, a collector, and an emitter,
wherein the floating base region of said first bipolar device is common to the floating base region of said second bipolar device,
wherein the collector of said first bipolar device is common to the collector of said second bipolar device, and
wherein application of back-bias to said collector results in at least two stable floating base region charge levels.
9. The semiconductor memory cell of claim 8, wherein said floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;
each said emitter has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and
said collector has said second conductivity type.
10. The semiconductor memory cell of claim 8, wherein said back-bias applied to said collector is a constant voltage bias.
11. The semiconductor memory cell of claim 8, wherein said back-bias applied to said collector is a periodic pulse of voltage.
12. The semiconductor memory cell of claim 8, further comprising a gate region above said floating base region.
13. The memory cell of claim 8, wherein a maximum potential that can be stored in said floating base region is increased by said applying back bias to the cell, resulting in a relatively larger memory window.
14. The memory cell of claim 8, comprising a fin structure extending from a substrate.
15. A semiconductor memory cell comprising:
a first bipolar device having a floating base region, a collector, and an emitter, and
a second bipolar device having a floating base region, a collector, and an emitter,
wherein the floating base region of said first bipolar device is common to the floating base region of said second bipolar device, and
wherein the collector of said first bipolar device is common to the collector of said second bipolar device, and
wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell.
16. The semiconductor memory cell of claim 15, wherein said floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;
each said emitter has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and
said collector has said second conductivity type.
17. The semiconductor memory cell of claim 15, wherein said back-bias applied to said collector is a constant voltage bias.
18. The semiconductor memory cell of claim 15, wherein said back-bias applied to said collector is a periodic pulse of voltage.
19. The memory cell of claim 15, wherein a maximum potential that can be stored in said floating base region is increased by said applying back bias to the cell, resulting in a relatively larger memory window.
20. The memory cell of claim 15, comprising a fin structure extending from a substrate.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A portable self-attached sanitary cover for toilet seats, the portable self-attached sanitary cover being a flexible and annular pad and comprising:
a loop-shaped outer edge section;
a loop-shaped inner edge section surrounded by the outer edge section;
a seat recess formed in the portable self-attached sanitary cover and located between the outer edge section and the inner edge section;
a loop-shaped weighted section mounted securely on the outer edge section;
an excreting hole formed through a central area of the portable self-attached sanitary cover and surrounded by the inner edge section; and
a folding gap formed in the portable self-attached sanitary cover to facilitate the portable self-attached sanitary cover to be folded.
2. The portable self-attached sanitary cover for toilet seats as claimed in claim 1, wherein the weighted section is integrally connected with an outer surface of the outer edge section.
3. The portable self-attached sanitary cover for toilet seats as claimed in claim 2, wherein the portable self-attached sanitary cover has multiple folding gaps formed in the weighted section at intervals to facilitate the portable self-attached sanitary cover to be folded.
4. The portable self-attached sanitary cover for toilet seats as claimed in claim 3, wherein portable self-attached sanitary cover further has multiple auxiliary gaps; and the auxiliary gaps are formed in the outer edge section and are respectively opposite to the folding gaps to facilitate the portable self-attached sanitary cover to be folded.
5. The portable self-attached sanitary cover for toilet seats as claimed in claim 2, wherein the portable self-attached sanitary cover has three folding gaps.
6. The portable self-attached sanitary cover for toilet seats as claimed in claim 2, wherein the portable self-attached sanitary cover has five folding gaps.
7. The portable self-attached sanitary cover for toilet seats as claimed in claim 2, wherein the weighted section has a body and a metal rod embedded in the body.