1. A semiconductor memory cell comprising:
a first bipolar device having a floating base region, a collector, and an emitter, and
a second bipolar device having a floating base region, a collector, and an emitter,
wherein the floating base region of said first bipolar device is common to the floating base region of said second bipolar device,
wherein the collector of said first bipolar device is common to the collector of said second bipolar device, and
wherein a state of said memory cell is maintained through a back-bias applied to said collector.
2. The semiconductor memory cell of claim 1, wherein said floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;
each said emitter has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and
said collector has said second conductivity type.
3. The semiconductor memory cell of claim 1, wherein said back-bias applied to said collector is a constant voltage bias.
4. The semiconductor memory cell of claim 1, wherein said back-bias applied to said collector is a periodic pulse of voltage.
5. The semiconductor memory cell of claim 1, further comprising a gate region above said floating base region.
6. The memory cell of claim 1, wherein a maximum potential that can be stored in said floating base region is increased by said applying back bias to the cell, resulting in a relatively larger memory window.
7. The memory cell of claim 1, comprising a fin structure extending from a substrate.
8. A semiconductor memory cell comprising:
a first bipolar device having a floating base region, a collector, and an emitter, and
a second bipolar device having a floating base region, a collector, and an emitter,
wherein the floating base region of said first bipolar device is common to the floating base region of said second bipolar device,
wherein the collector of said first bipolar device is common to the collector of said second bipolar device, and
wherein application of back-bias to said collector results in at least two stable floating base region charge levels.
9. The semiconductor memory cell of claim 8, wherein said floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;
each said emitter has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and
said collector has said second conductivity type.
10. The semiconductor memory cell of claim 8, wherein said back-bias applied to said collector is a constant voltage bias.
11. The semiconductor memory cell of claim 8, wherein said back-bias applied to said collector is a periodic pulse of voltage.
12. The semiconductor memory cell of claim 8, further comprising a gate region above said floating base region.
13. The memory cell of claim 8, wherein a maximum potential that can be stored in said floating base region is increased by said applying back bias to the cell, resulting in a relatively larger memory window.
14. The memory cell of claim 8, comprising a fin structure extending from a substrate.
15. A semiconductor memory cell comprising:
a first bipolar device having a floating base region, a collector, and an emitter, and
a second bipolar device having a floating base region, a collector, and an emitter,
wherein the floating base region of said first bipolar device is common to the floating base region of said second bipolar device, and
wherein the collector of said first bipolar device is common to the collector of said second bipolar device, and
wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell.
16. The semiconductor memory cell of claim 15, wherein said floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;
each said emitter has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and
said collector has said second conductivity type.
17. The semiconductor memory cell of claim 15, wherein said back-bias applied to said collector is a constant voltage bias.
18. The semiconductor memory cell of claim 15, wherein said back-bias applied to said collector is a periodic pulse of voltage.
19. The memory cell of claim 15, wherein a maximum potential that can be stored in said floating base region is increased by said applying back bias to the cell, resulting in a relatively larger memory window.
20. The memory cell of claim 15, comprising a fin structure extending from a substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A portable self-attached sanitary cover for toilet seats, the portable self-attached sanitary cover being a flexible and annular pad and comprising:
a loop-shaped outer edge section;
a loop-shaped inner edge section surrounded by the outer edge section;
a seat recess formed in the portable self-attached sanitary cover and located between the outer edge section and the inner edge section;
a loop-shaped weighted section mounted securely on the outer edge section;
an excreting hole formed through a central area of the portable self-attached sanitary cover and surrounded by the inner edge section; and
a folding gap formed in the portable self-attached sanitary cover to facilitate the portable self-attached sanitary cover to be folded.
2. The portable self-attached sanitary cover for toilet seats as claimed in claim 1, wherein the weighted section is integrally connected with an outer surface of the outer edge section.
3. The portable self-attached sanitary cover for toilet seats as claimed in claim 2, wherein the portable self-attached sanitary cover has multiple folding gaps formed in the weighted section at intervals to facilitate the portable self-attached sanitary cover to be folded.
4. The portable self-attached sanitary cover for toilet seats as claimed in claim 3, wherein portable self-attached sanitary cover further has multiple auxiliary gaps; and the auxiliary gaps are formed in the outer edge section and are respectively opposite to the folding gaps to facilitate the portable self-attached sanitary cover to be folded.
5. The portable self-attached sanitary cover for toilet seats as claimed in claim 2, wherein the portable self-attached sanitary cover has three folding gaps.
6. The portable self-attached sanitary cover for toilet seats as claimed in claim 2, wherein the portable self-attached sanitary cover has five folding gaps.
7. The portable self-attached sanitary cover for toilet seats as claimed in claim 2, wherein the weighted section has a body and a metal rod embedded in the body.