Author: claimsbot

1. A controller configured to determine a measurable capacitance, the controller configured to:
apply a pre-determined voltage to a first sensing electrode of a plurality of sensing electrodes using a first switch;
apply a first guard voltage to a guarding electrode using a second switch;
share charge between the first sensing electrode and a passive network, such that shared charge is accumulated on a filter capacitance of the passive network;
apply a second guard voltage different from the first guard voltage to the guarding electrode;
measure a voltage on the filter capacitance for a number of measurements equal to at least one to produce at least one result; and
determine the measurable capacitance using the at least one result.
2. The controller of claim 1 wherein the first guard voltage comprises a voltage selected to approximate the pre-determined voltage.
3. The controller of claim 1 wherein the second guard voltage comprises a voltage selected to be in a range between and including a threshold voltage and a reset voltage.
4. The controller of claim 1 wherein the second guard voltage comprises part of a variable voltage waveform, the variable voltage waveform changing with a time constant selected to approximate the voltage on the filter capacitance.
5. The controller of claim 1 wherein the wherein the second guard voltage comprises a pulse modulated signal.
6. The controller of claim 1 wherein the second guard voltage comprises a voltage approximating an average voltage on the filter capacitance.
7. The controller of claim 1 wherein the controller is further configured to share charge between the first sensing electrode and the passive network using a third switch.
8. A controller adapted to determine a capacitance value associated with a sensor electrode, the controller configured to:
apply a guard signal to a guarding electrode, the guard signal comprising a waveform having at least two different voltages;
determine the capacitance value by
repeatedly applying a voltage to the sensor electrode,
accumulating charge on an integrating capacitance by repeatedly sharing charge between the sensor electrode and the integrating capacitance,
generating quantized values by repeatedly measuring a voltage on the integrating capacitance using a quantizer of the controller,
repeatedly changing charge on the integrating capacitance based on the quantized values, and
determining the capacitance value associated with the sensor electrode using the quantized values.
9. The controller of claim 8 wherein a first voltage of the at least two different voltages of the guard signal approximates the voltage applied to the sensor electrode.
10. The controller of claim 8 wherein the waveform of the guard signal has a time constant such that the waveform of the guard signal approximates a waveform of the voltage on the integrating capacitance.
11. The controller of claim 8 wherein a second voltage of the at least two different voltages of the guard signal approximates an average of the waveform of the voltage on the integrating capacitance.
12. The controller of claim 8 wherein the at least two different voltages of the guard signal span a range substantially similar to a range defined by the voltage applied to the sensor electrode and a reset voltage of the integrating capacitance.
13. The controller of claim 8 wherein the at least two different voltages of the guard signal span a range substantially less than a range defined by the voltage applied to the sensor electrode and a reset voltage of the integrating capacitance.
14. The controller of claim 8 wherein the at least two different voltages of the guard signal comprise voltages that extend beyond the voltage applied to the sensor electrode and a reset voltage of the integrating capacitance.
15. A controller including a memory, the memory including executable instructions for determining a measurable capacitance associated with a sensing electrode by:
applying a guard signal to a guarding electrode, the guard signal comprising a waveform having at least two different voltages;
applying a voltage to the sensing electrode;
sharing charge between the sensing electrode and a passive network such that shared charge is accumulated on an integrating capacitance of the passive network;
measuring a voltage on the integrating capacitance for a number of measurements equal to at least one to produce at least one result; and
determining the measurable capacitance using the at least one result.
16. The controller of claim 15 wherein the at least two different voltages of the guard signal span a range substantially similar to a range defined by the voltage applied to the sensing electrode and a reset voltage of the integrating capacitance.
17. The controller of claim 15 wherein the at least two different voltages of the guard signal span a range substantially less than a range defined by the voltage applied to the sensing electrode and a reset voltage of the integrating capacitance.
18. The controller of claim 15 wherein the at least two different voltages of the guard signal comprise voltages that extend beyond the voltage applied to the sensing electrode and a reset voltage of the integrating capacitance.
19. The controller of claim 15, wherein the at least two different voltages of the guard signal comprises a voltage approximating the voltage applied to the sensing electrode.
20. The controller of claim 15, wherein the guard signal averages to a voltage approximating an average voltage on the integrating capacitance.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A printhead assembly comprising:
a plurality of printhead modules each having a plurality of modular printhead tiles each having a plurality of micro-electromechanical nozzle assemblies for operatively printing on a printing medium;
a ducting assembly having a laminated stack of layers, each layer of the stack having a number of apertures which, when the layers are stacked, provide ducts whereby ink is able to flow from an ink reservoir to the nozzle assemblies;
a number of electrical connector assemblies for operatively connecting the respective printhead tiles together; and
a casing in which the printhead modules are arranged so as to be removably mounted in linearly aligned relationship through removable engagement of each printhead module with the casing.
2. A printhead assembly as claimed in claim 1, in which each printhead module has a support member and the casing has a support frame, the support member having a first tab received in a recess of the support frame and a second tab clamped between the support frame and a mounting element mounted to the support frame so as to allow constrained movement of the relevant printhead module relative to the casing.
3. The printhead assembly of claim 2, wherein the support member defines a raised portion and a recessed portion at an end thereof, each printhead tile having electrical connecting strips which overlie the respective recessed portions, the assembly including a connecting member having a series of parallel spaced conducting strips, said connecting member being shaped and configured for fitment into a cavity defined by the raised and recessed portions of two abutting support members to connect the connecting strips of two tiles via said conducting strips.
4. The printhead assembly of claim 3, having a sealing adhesive provided at an interface of the support members.
5. The printhead assembly of claim 4, wherein the sealing adhesive is an epoxy.
6. The printhead assembly of claim 3, which includes a printhead controller integrated circuit for controlling operation of the printhead tiles via the connecting strips.
7. The printhead assembly of claim 3, wherein the connecting member is a rectangular block having the series of conducting strips on each surface thereof.
8. The printhead assembly of claim 3, wherein the connecting member is formed of a strip of silicone rubber printed to provide sequentially spaced conductive and non-conductive material strips.
9. The printhead assembly of claim 3, wherein the conducting strips of the connecting member are provided in a 2:1 relationship with the connecting strips of the tiles.

I claim:

1. In a computer having a processor and a computer readable memory coupled to each other, a method of generating a configuration for a configurable communication device to implement a desired function, the method comprising the steps of:
a) receiving, at the computer, an input identifying a desired operation to be implemented by the configurable communication device;
b) generating, on the computer, a signal flow path of the desired operation; and
c) mapping, via the computer, the desired operation onto a computing element within the configurable communication device, the computing element having localized control and being function-specific.
2. The method recited in claim 1 further comprising the step of:
d) repeating step c) for each of a plurality of computing elements within the configurable communication device capable of the desired operation.
3. The method recited in claim 1 further comprising the step of:
d) repeating steps a) through c) as necessary to satiate a plurality of operations that enable the desired function.
4. The method recited in claim 3 further comprising the step of:
d) translating the signal flow path into configuration mappings for each of the computing elements used to implement plurality of operations for the desired function.
5. The method recited in claim 4 further comprising the step of:
e) configuring a configurable interconnect of the configurable communication device to enable the signal flow path across computing elements for each of the plurality of operations that enable the desired function.
6. The method recited in claim 1 further comprising the step of:
d) receiving, at the computer, the desired function to be performed on the configurable communication device; and
e) dividing the function into a set of discrete operations able to be performed on at least one of a plurality of computing elements of the configurable communication device.
7. The method recited in claim 6 further comprising the step of:
f) repeating the receiving step d) and the dividing step e) as necessary to satiate multiple functions required for the application.
8. The method recited in claim 1 further comprising the step of:
d) defining a timing sequence for activating each of the plurality of computing elements required to satiate the desired operation.
9. The method recited in claim 1 further comprising the step of:
d) time-sharing resources of the computing elements to accommodate a plurality of operations.
10. The method recited in claim 9 further comprising the step of:
e) scheduling the configuration download to computing elements of the configurable communication device based upon time-sharing step d).
11. The method recited in claim 9 wherein time-sharing step d) shares resources across multiple channels in a wireless communication application.
12. The method recited in claim 9 wherein the time-sharing in time-sharing step d) comprises the following steps:
d1) identifying a plurality of operations desired to occur within a given system cycle;
d2) dividing the system cycle into a plurality of sections; and
d3) assigning each of the plurality of operations to a respective one of the plurality of sections of the system cycle.
13. The method recited in claim 3 wherein mapping step c) comprises the following sub steps:
c1) creating an original system dataflow;
c2) identifying specific algorithm thread;
c3) identifying a range and types of operations contained in the algorithm thread; and
c4) categorizing and mapping the operations into a plurality of processor groups, the processor groups representing major islands of dataflow in the reconfigurable architecture.
14. The method recited in claim 13 wherein the dataflow, control flow, or interconnect configuration is configured to change dynamically, while the configurable communication device is in operation.
15. The method recited in claim 1 wherein the configurable communication device is applicable to spread spectrum protocols.
16. An electronic device for configuring a configurable communication device, the electronic device comprising:
a computer readable memory;
a processor coupled to the computer readable memory, the computer readable memory containing instructions and data, that when executed on the processor, implement a method for configuring the configurable communication device, the method comprising the steps of:
a) receiving, at the computer, an input identifying a desired operation to be implemented by the configurable communication device;
b) generating, on the computer, a signal flow path of the desired operation; and
c) mapping, via the computer, the desired operation onto a computing element within the configurable communication device, the computing element having localized control and being function-specific.
17. The electronic device recited in claim 16 wherein the method further comprises the step of:
d) repeating step c) for each of a plurality of computing elements within the configurable communication device capable of the desired operation.
18. The electronic device recited in claim 16 wherein the method further comprises the step of:
d) repeating steps a) through c) as necessary to implement a plurality of operations that enable a desired function.
19. The electronic device recited in claim 18 wherein the method further comprises the step of:
e) translating the signal flow path into configuration mappings for each of the computing elements used to implement the plurality of operations for the desired function.
20. The electronic device recited in claim 19 wherein the method further comprises the step of:
f) configuring a configurable interconnect of the configurable communication device to enable the signal flow path across computing elements for each of the plurality of operations that enable the desired function.
21. The electronic device recited in claim 16 wherein the method further comprises the step of:
d) receiving, at the computer, the desired function to be performed on the configurable communication device; and
e) dividing the function into a set of discrete operations able to be performed on at least one of a plurality of computing elements of the configurable communication device.
22. The electronic device recited in claim 21 wherein the method further comprises the step of:
f) repeating the receiving step d) and the dividing step e) as necessary to satiate multiple functions required for the application.
23. The electronic device recited in claim 16 wherein the method further comprises the step of:
d) defining a timing sequence for activating each of the plurality of computing elements required to implement the desired operation.
24. The electronic device recited in claim 16 wherein the method further comprises the step of:
d) time-sharing resources of the computing elements to accommodate a plurality of operations.
25. The electronic device recited in claim 24 wherein the method further comprises the step of:
e) scheduling the configuration download to computing elements of the configurable communication device based upon time-sharing step d).
26. The electronic device recited in claim 24 wherein time-sharing step d) shares resources across multiple channels in a wireless communication application.
27. The electronic device recited in claim 24 wherein the time-sharing in time-sharing step d) comprises the following steps:
d1) identifying a plurality of operations desired to occur within a given system cycle;
d2) dividing the system cycle into a plurality of sections; and
d3) assigning each of the plurality of operations to a respective one of the plurality of sections of the system cycle.
28. The electronic device recited in claim 27 wherein the method further comprises the step of: mapping step c) comprises the following sub steps:
c1) creating an original system dataflow;
c2) identifying specific algorithm thread;
c3) identifying a range and types of operations contained in the algorithm thread; and
c4) categorizing and mapping the operations into a plurality of processor groups, the processor groups representing major islands of dataflow in the reconfigurable architecture.
29. The electronic device recited in claim 24 wherein the dataflow, control flow, or interconnect configuration is configured to change dynamically, while the configurable communication device is in operation.
30. The method recited in claim 16 wherein the configurable communication device being configured is applicable to a spread spectrum protocol.
31. A computer readable medium containing therein computer readable codes that enable an electronic device to implement a method for configuring a configurable communication device, the method comprising:
a) receiving, at the computer, an input identifying a desired operation to be implemented by the configurable communication device;
b) generating, on the computer, a signal flow path of the desired operation; and
c) mapping, via the computer, the desired operation onto a computing element within the configurable communication device, the computing element having localized control and being function-specific.
32. The computer readable medium recited in claim 31 further comprising the step of:
d) repeating step c) for each of a plurality of computing elements within the configurable communication device capable of the desired operation.
33. The computer readable medium recited in claim 31 further comprising the step of:
d) repeating steps a) through c) as necessary to satiate a plurality of operations that enable a desired function.
34. The computer readable medium recited in claim 33 further comprising the step of:
e) translating the signal flow path into configuration mappings for each of the computing elements used to implement the plurality of operations for the desired function.
35. The computer readable medium recited in claim 34 further comprising the step of:
f) configuring a configurable interconnect of the configurable communication device to enable the signal flow path across computing elements for each of the plurality of operations that enable the desired function.
36. The computer readable medium recited in claim 31 further comprising the step of:
d) receiving, at the computer, the desired function to be performed on the configurable communication device; and
e) dividing the function into a set of discrete operations able to be performed on at least one of a plurality of computing elements of the configurable communication device.
37. The computer readable medium recited in claim 36 further comprising the step of:
f) repeating the receiving step d) and the dividing step e) as necessary to implement multiple functions required for the application.
38. The computer readable medium recited in claim 31 further comprising the step of:
d) defining a timing sequence for activating each of the plurality of computing elements required to implement the desired operation.
39. The computer readable medium recited in claim 31 further comprising the step of:
d) time-sharing resources of the computing elements to accommodate a plurality of operations.
40. The computer readable medium recited in claim 39 further comprising the step of:
e) scheduling the configuration download to computing elements of the configurable communication device based upon time-sharing step d).
41. The computer readable medium recited in claim 39 wherein time-sharing step d) shares resources across multiple channels in a wireless communication application.
42. The computer readable medium recited in claim 39 wherein the timesharing in time-sharing step d) comprises the following steps:
d1) identifying a plurality of operations desired to occur within a given system cycle;
d2) dividing the system cycle into a plurality of sections; and
d3) assigning each of the plurality of operations to a respective one of the plurality of sections of the system cycle.
43. The computer readable medium recited in claim 33 wherein mapping step c) comprises the following sub steps:
c1) creating an original system dataflow;
c2) identifying specific algorithm thread;
c3) identifying a range and types of operations contained in the algorithm thread; and
c4) categorizing and mapping the operations into a plurality of processor groups, the processor groups representing major islands of dataflow in the reconfigurable architecture.
44. The computer readable medium recited in claim 43 wherein the dataflow, control flow, or interconnect configuration is configured to change dynamically, while the configurable communication device is in operation.
45. The computer readable medium recited in claim 9 wherein the configurable communication device is applicable to spread spectrum protocols.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for decoding comprising the step of:
using information known to a channel decoder and providing same to a source decoder to determine a path between two data points, whereby reducing error or bad data effects.
2. The method of claim 1 further comprising the step of using the determined path for further channel decoding.
3. The method of claim 1, wherein the information comprises at least one bad data location or position known to the channel decoder.
4. The method of claim 1, wherein the channel decoder comprises a forward error correction (FEC) decoder using Reed-Solomon (RS) code, low density parity check (LDPC) code, or other types of error correction codes.
5. The method of claim 1, wherein the path spans over sub-blocks of data.
6. The method of claim 1, wherein the two data points comprise a first start code and a second start code subsequence to the first start code.
7. The method of claim 1, wherein variable length code (VLC) in a bit stream for decoding.