Author: claimsbot

1. A memory device comprising:
multiple memory units electrically connected to a bus; and
a controller, connected to one end of said bus, for controlling a reading operation and a writing operation relative to said memory units,
wherein the controller includes an active terminating circuit that is rendered active only during said reading operation.
2. A memory device according to claim 1, wherein said memory units are connected to said bus through stubs and connectors.
3. A memory device according to claim 2, wherein reflection prevention means, for preventing a reflected wave during said reading operation performed for said multiple memory units, is provided between said controller and the nearest one of said connectors that connects said multiple memory units to said bus and that is located nearest to said controller.
4. A memory device according to claim 3, wherein said reflection prevention means is formed by a circuit wherein a characteristic impedance between said nearest connector and said controller is smaller than another characteristic impedance of a connection on each memory unit.
5. A memory device according to claim 4, wherein said circuit includes a capacitor connected between said nearest connector and said controller.
6. A memory device according to claim 5, wherein said circuit has a bus connection length adjusted to the characteristic impedance between the nearest connector and said controller.
7. A memory device according to claim 1, wherein the bus has one end connected to said controller and the other end connected to a terminator unit while the terminator unit has a pair of terminal resistors that are connected in series between a predetermined power terminal and a reference power terminal through a common point of connection; and wherein the other end of said bus is jointed to the common point of connection of both the terminal resistors.
8. A memory device according to claim 1, wherein said bus is either a data bus or a command bus.
9. A memory device according to claim 1, wherein said memory units are terminated by an active terminator unit.
10. A memory device according to claim 1, wherein said bus is shielded.
11. A memory device according to claim 1, wherein said memory units are DRAMs.
12. A memory device comprising:
a clock controller for transmitting complementary clocks;
a pair of clock buses, connected at the ends thereof to said clock controller to transmit said complementary clocks; and
multiple memory units, electrically connected to said pair of clock buses,
wherein the pair of clock buses have one ends connected to the clock controller and opposite ends connected to a terminal resistor so that the pair of the clock buses are terminated by differential coupling.
13. A memory device according to claim 12, wherein said memory units are connected through a pair of connectors to said pair of clock buses; and wherein a clock bus segment between said terminal resistor and said pair of connectors that are nearest to the terminal resistor has a satisfactory length so as to serve substantially as a distributed constant circuit.
14. A memory device according to claim 13, wherein the impedance for said clock bus segment having said length is defined substantially as a characteristic impedance for said distributed constant circuit.
15. A memory device according to claim 13, wherein a clock bus segment between said controller and a pair of connectors that are nearest to said controller is longer than a clock bus segment between the other connectors.
16. A memory device according to claim 15, wherein a capacitor for reflection prevention is connected at said clock bus segment for said pair of connectors nearest to said controller.
17. A memory device according to claim 12, further comprising:
a data bus for connecting said multiple memory units through multiple connectors; and
a data bus controller, connected to one end of said data bus, for carrying out data transmission with said memory units through said data bus.
18. A memory device according to claim 17, wherein said data bus controller has an active terminator unit that is rendered active when data is to be read from said memory units, and that is maintained inactive when data is to be written to said memory units.
19. A memory device according to claim 18, wherein a terminal resistor circuit is constituted by a pair of resistors connected in series to each other and is connected to the other end of said data bus opposite to the end connected to the bus controller; and wherein the other end of said data bus is connected to a common point of connection of the pair of registers to terminate the other end of said data bus.
20. A memory device according to claim 19, further comprising a capacitor connected between said data bus controller and a connector nearest to the data bus controller so as to reduce reflection.
21. A memory device comprising:
a clock controller for transmitting complementary clocks;
a pair of clock buses, connected at the ends thereof to said clock controller to transmit said complementary clocks; and
multiple memory units, electrically connected to said pair of clock buses,
wherein each of said memory units includes a differential coupling termination circuit for terminating said pair of clock buses.
22. A memory device according to claim 21, wherein a differential coupling termination circuit is incorporated in each of said memory units.
23. A memory device according to claim 21, wherein said differential coupling terminating circuit is externally attached to each of said memory units.
24. A memory device according to claim 21, wherein said pair of clock buses have branches connected to said memory units, and wherein said differential coupling termination circuit is connected between said branches of said clock buses of each of said memory units.
25. A memory device comprising:
a clock controller for transmitting complementary clocks;
a pair of clock buses, connected at the ends thereof to said clock controller to transmit said complementary clocks; and
multiple memory units, electrically connected to said pair of clock buses,
wherein each of said memory units includes an active terminator unit for terminating said pair of clock buses.
26. A memory device according to claim 21, further comprising:
a data bus controller for performing data writing and reading relative to said multiple memory units; and
a data bus for connecting said data bus controller and said memory units.
27. A memory device according to claim 26, wherein said data bus controller has an active terminator unit that is rendered active when data is to be read from said memory units, and that is maintained inactive when data is to be written to said memory units.
28. A memory device according to claim 27, wherein each of said memory units includes an active terminator unit that is rendered inactive for data reading, and is rendered active for data writing, and wherein said data bus is terminated by said active terminator unit.
29. A memory device according to claim 27, wherein multiple slots, along a bus, for which memory units are provided; wherein said memory units include active terminator units that are rendered inactive for data reading; wherein an active terminator unit, which is included in a memory unit in a slot from which data is to be read, is rendered active while active terminator units for all other memory units are rendered inactive; and wherein said active terminator unit terminates said data bus.
30. A memory device comprising:
multiple memory units, electrically connected to a bus while being branched through connectors and stubs thereof; and
a controller, electrically connected to one end of said bus, for controlling a reading operation and a writing operation relative to said memory units,
wherein said bus between said controller and said multiple memory units, connectors, resistors and stubs is connected so that a substantially equal impedance is obtained along said bus relative to said controller and said memory units.
31. A memory device according to claim 30, wherein said controller and said multiple memory units are joined together along said bus by star connection such that n lines of the same characteristic impedance ZO are connected at branching points respectively through resistors baying a resistance of ZOn, where n is a positive integer.
32. A memory device according to claim 30, wherein said bus is either a data bus or a command address bus.
33. device according to claim 30, wherein the controller and the memory units each have an active terminator unit to terminate said bus.
34. A memory device according to claim 30, wherein said controller and said memory units are connected through a pair of clock buses for providing complementary clocks.
35. A memory device according to claims 30, wherein said controller and said memory units are connected through a clock bus.
36. A memory device according to claim 30, wherein said bus is a clock bus.
37. A memory device according to claim 35, wherein said controller and said memory units are joined together through said pair of clock buses to form star connection.
38. A memory device according to claim 35, wherein said clock bus is terminated a terminating resistor connected on the memory unit side.
39. A memory device comprising:
a clock controller for transmitting complementary clocks;
a pair of clock buses, connected at the ends thereof to said clock controller to transmit said complementary clocks; and
multiple memory units, electrically connected to said pair of clock buses,
wherein the configuration of said clock bus is as described in claim 30.
40. A memory device according to claim 39, wherein said controller and said multiple memory units are joined together by said star connection through said pair of clock buses.
41. A memory device according to claim 39, wherein each of said memory units includes a differential coupling termination circuit for terminating said pair of clock buses.
42. A memory device according to claim 12, further comprising:
a command address bus for connecting said memory units to multiple connectors; and
a bus controller, connected to one end of said command address bus, for carrying out data transmission with said memory units through said command address bus.
43. A memory device according to claim 42, wherein said bus controller includes an active terminator unit that is rendered active when data is to be received from said memory units, and that is maintained inactive when command address data is to be sent to said memory units.
44. A memory device comprising:
multiple memory units electrically connected to a command address bus; and
a bus controller, connected to one end of said command address bus to control a reading operation and a writing operation relative to said memory units,
wherein said bus controller includes an active terminator unit and a controller for controlling said active terminator unit,
wherein each of said memory units also includes an active terminator unit for terminating said command address bus, and
wherein, when data is to be received from said memory units that are mounted in memory modules connected to connectors, said controller renders inactive only the active terminator unit of the memory unit from which data is to be read, and renders active the active terminator units of the other memory units and said bus controller.
45. A memory device comprising:
multiple memory units electrically connected to a command address bus; and a bus controller connected to one end of said command address bus to control a reading operation and a writing operation relative to said memory units,
wherein said bus controller includes an active terminator unit and a controller for controlling said active terminator unit
wherein each of said memory units also includes an active terminator unit for terminating said command address bus, and
wherein, when command address data is to be written in said memory units, said controller renders said active terminator unit of said data bus controller inactive and renders said active terminator units of said memory units active.
46. A memory device comprising:
multiple memory units electrically connected to a command address bus; and
a bus controller, connected to one end of said command address bus to control a reading operation and a writing operation relative to said memory units.
wherein said bus controller includes an active terminator unit and a controller for controlling said active terminator unit,
wherein each of said memory units also includes an active terminator unit for terminating said command address bus,
wherein there are multiple slots for which memory units are provided, and
wherein, when command address data is to be transmitted to the memory unit in a specific slot, said controller renders inactive said active terminator unit of said data bus controller, and also renders inactive the active terminator unit of said memory unit in said specific slot, with the active terminator units of the other memory units kept active.
47. A memory device comprising:
multiple memory units electrically connected to a command address bus; and
a bus controller, connected to one end of said command address bus to control a reading operation and a writing operation relative to said memory units,
wherein said bus controller includes an active terminator unit and a controller for controlling said active terminator unit,
wherein each of said memory units also includes an active terminator unit for terminating said command address bus,
wherein there are multiple slots for which memory units are provided, and
wherein, when command address data is to be transmitted to a memory unit in a specific slot, said controller renders inactive said active terminator unit of said data bus controller, and also renders inactive an active terminator unit of a command address register in said specific slot, while rendering the active terminator units of the other command address registers.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A memory system comprising:
a memory hub device integrated in a memory module;
a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module;
a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces;
a memory hub controller integrated into the memory hub device;
a link interface integrated into the memory hub device, wherein the link interface provides a communication path between the memory controller and the memory hub controller and the first and second set of memory devices such that the memory hub controller receives memory access commands from the memory controller via the link interface, and wherein the memory devices receive and send data via the link interface;
a first multiplexer integrated into the memory hub device, the first multiplexer being coupled to the link interface, the memory hub controller, the first memory device data interface, and the second memory device data interface, the first multiplexer being provided so as to provide read data from the first and second set of memory devices to the link interface based on a control signal from the memory hub controller;
second multiplexer integrated into the memory hub device the second multiplexer being coupled to the link interface, the memory hub controller, and the first memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the first set of memory devices based on a control signal from the memory hub controller; and
a third multiplexer integrated into the memory hub device, the third multiplexer being coupled to the link interface, the memory hub controller, and the second memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the second set of memory devices based on a control signal from the memory hub controller.
2. The memory system of claim 1, wherein the memory system further comprises:
a memory channel for communicating with the first set of memory devices and the second set of memory devices via the memory hub device; and
a memory controller in communication with the memory channel, wherein the memory controller generates memory access requests, receives memory access requests, and responds to memory access requests.
3. The memory system of claim 1, wherein the
memory hub controller is coupled to the first memory device data interface and the second memory device data interface.
4. The memory system of claim 3, wherein the memory hub controller responds to access request packets from one of a memory controller external to the memory module or a downstream memory hub device of another memory module by responsively driving one or more of the first set of memory devices or the second set of memory devices using a memory device address and control bus and directing one of a read data flow selector or a write data flow selector.
5. The memory system of claim 4, wherein the memory hub controller drives the read data flow selector to a multiplexer of the memory hub device to select outputting read data directly, from one of the first memory device data interface or the second memory device data interface, or outputting read data from a read data queue.
6. The memory system of claim 4, wherein the memory hub controller drives the write data flow selector to a first multiplexer and a second multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device.
7. The memory system of claim 6, wherein the first multiplexer provides an output to the first memory device data interface and the second multiplexer provides an output to the second memory device data interface.
8. The memory system of claim 3, wherein the memory hub controller, in response to a write access request packet, issues a first memory write access request to the first set of memory devices via the first memory device data interface and substantially immediately issues a second memory write access request to the second set of memory devices via the second memory device data interface.
9. The memory system of claim 3, wherein the memory hub controller, in response to a read access request packet, issues a first memory read access request to the first set of memory devices via the first memory device data interface and substantially immediately issues a second memory read access request to the second set of memory devices via the second memory device data interface.
10. The memory system of claim 9, wherein read data from the first memory read access request and the second memory read access request are directly transferred to the memory controller.
11. The memory system of claim 9, wherein read data from the first memory read access request and the second memory read access request are queued prior to be transferred to the memory controller.
12. The memory system of claim 1, wherein a first memory access request is processed via the first memory device data interface and a second memory access request is processed via the second memory device data interface at substantially a same time in a parallel manner.
13. A memory module, comprising:
a memory hub device integrated into the memory module;
a first set of memory devices integrated in the memory module and coupled to the memory hub device;
a second set of memory devices integrated in the memory module and coupled to the memory hub device;
a first memory device data interface integrated in the memory hub device through which the first set of memory devices are coupled to internal logic of the memory hub device;
a second memory device data interface integrated in the memory hub device through which the second set of memory devices are coupled to internal logic of the memory hub device, wherein the first set of memory devices are separate from the second set of memory devices and the first and the second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces;
a memory hub controller integrated into the memory hub device;
a link interface integrated into the memory hub device, wherein the link interface provides a communication path between an external memory controller and the memory hub controller and the first and second set of memory devices such that the memory hub controller receives memory access commands from the memory controller via the link interface, and wherein the memory devices receive and send data via the link interface,
a first multiplexer integrated into the memory hub device, the first multiplexer being coupled to the link interface, the memory hub controller, the first memory device data interface, and the second memory device data interface, the first multiplexer being provided so as to provide read data and second set of memory devices to the link interface based on a control signal from the memory hub controller;
a second multiplexer integrated into the memory hub device, the second multiplexer being coupled to the link interface, the memory hub controller, and the first memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the first set of memory devices based on a control signal from the memory hub controller; and
a third multiplexer integrated into the memory hub device, the third multiplexer being coupled to the link interface, the memory hub controller, and the second memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the second set of memory devices based on a control signal from the memory hub controller.
14. The memory module of claim 13, further comprising:
a memory hub controller integrated into the memory hub device;
a link interface integrated into the memory hub device, wherein the link interface provides a communication path between an external memory controller and the memory hub controller and the first and second set of memory devices such that the memory hub controller receives memory access commands from the memory controller via the link interface, and wherein the memory devices receive and send data via the link interface;
a first multiplexer integrated into the memory hub device, the first multiplexer being coupled to the link interface, the memory hub controller, the first memory device data interface, and the second memory device data interface, the first multiplexer being provided so as to provide read data from the first and second set of memory devices to the link interface based on a control signal from the memory hub controller;
a second multiplexer integrated into the memory hub device, the second multiplexer being coupled to the link interface, the memory hub controller, and the first memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the first set of memory devices based on a control signal from the memory hub controller; and
a third multiplexer integrated into the memory hub device, the third multiplexer being coupled to the link interface, the memory hub controller, and the second memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the second set of memory devices based on a control signal from the memory hub controller.
15. A data processing system, comprising:
a processor; and
a memory coupled to the processor, wherein the memory comprises at least one memory module, and wherein the at least one memory module comprises:
a memory hub device integrated in a memory module;
a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and
a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interface, wherein the at least one memory module further comprises:
a memory hub controller integrated into the memory hub device; and
a link interface integrated into the memory hub device, wherein the link interface provides a communication oath between the memory controller and the memory hub controller and the first and second set of memory devices such that the memory hub controller receives memory access commands from the memory controller via the link interface, and wherein the memory devices receive and send data via the link interface, wherein the at least one memory module further comprises:
a first multiplexer integrated into the memory hub device, the first multiplexer being coupled to the link interface, the memory hub controller, the first memory device data interface, and the second memory device data interface, the first multiplexer being provided so as to provide read data from the first and second set of memory devices to the link interface based on a control signal from the memory hub controller,
a second multiplexer integrated into the memory hub device, the second multiplexer being coupled to the link interface, the memory hub controller, and the first memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the first set of memory devices based on a control signal from the memory hub controller; and
a third multiplexer integrated into the memory hub device, the third multiplexer being coupled to the link interface, the memory hub controller, and the second memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the second set of memory devices based on a control signal from the memory hub controller.
16. The data processing system of claim 15, wherein the memory further comprises:
a memory channel for communicating with the first set of memory devices and the second set of memory devices via the memory hub device; and
a memory controller in communication with the memory channel, wherein the memory controller generates memory access requests, receives memory access requests, and responds to memory access requests.
17. The data processing system of claim 15, wherein
memory hub controller is coupled to the first memory device data interface and the second memory device data interface.
18. The data processing system of claim 17, wherein the memory hub controller responds to access request packets from one of a memory controller external to the memory module or a downstream memory hub device of another memory module by responsively driving one or more of the first set of memory devices or the second set of memory devices using a memory device address and control bus and directing one of a read data flow selector or a write data flow selector.
19. The data processing system of claim 18, wherein the memory hub controller drives the read data flow selector to a multiplexer of the memory hub device to select outputting read data directly, from one of the first memory device data interface or the second memory device data interface, or outputting read data from a read data queue, wherein the memory hub controller drives the write data flow selector to a first multiplexer and a second multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device and wherein the first multiplexer provides an output to the first memory device data interface and the second multiplexer provides an output to the second memory device data interface.
20. The data processing system of claim 17, wherein the memory hub controller, in response to a write access request packet, issues a first memory write access request to the first set of memory devices via the first memory device data interface and substantially immediately issues a second memory write access request to the second set of memory devices via the second memory device data interface.
21. The data processing system of claim 17, wherein the memory hub controller, in response to a read access request packet, issues a first memory read access request to the first set of memory devices via the first memory device data interface and substantially immediately issues a second memory read access request to the second set of memory devices via the second memory device data interface, wherein read data from the first memory read access request and the second memory read access request are directly transferred to the memory controller and wherein read data from the first memory read access request and the second memory read access request are queued prior to be transferred to the memory controller.

1. A vehicle transporter comprising:
(a) a vehicular frame;
(b) a vehicle support member movable relative to said vehicular frame; and
(c) a screw actuator having elongate members connected to said vehicular frame and said vehicle support member and slidable longitudinally in a partially coextensive relationship to each other to vary a length of a portion of one member that is coextensive longitudinally with a portion of another member and thereby cause said vehicle support member to move relative to said vehicular frame, said screw actuator having a longitudinally extending rotatable screw whose rotation forces said elongate members to slide longitudinally relative to each other.
2. The vehicle transporter of claim 1 wherein said screw actuator further comprises a motor including a frame connected to an elongate member and a shaft rotatable in said frame and drivingly connected to rotate said screw.
3. The vehicle transporter of claim 1 wherein said screw comprises a screw thread that is self-locking to prevent forces tending to slide said members relative to each other from rotating said screw.
4. The vehicle transporter of claim 1 wherein said screw comprises an Acme screw thread having a lead angle not exceeding five degrees.
5. The vehicle transporter of claim 1 wherein said connections of said screw actuator to said vehicular frame and to said vehicle support member are pivotable connections.
6. The vehicle transporter of claim 5 wherein said screw actuator further comprises a motor including a frame connected to an elongate member enabling said motor and said elongate member to pivot in unison and a shaft rotatable in said frame and drivingly connected to rotate said screw.
7. The vehicle transporter of claim 5 wherein said motor shaft is rotatable on a common axis with said screw.
8. The vehicle transporter of claim 1 wherein said vehicle support member is pivotally connected to said frame at a location distal of said connection to said screw actuator and relative movement of said elongate members causes said vehicle support member to pivot relative to said frame.
9. A screw actuator comprising:
(a) a tubular shell connectible to a first member; said tubular shell comprising a wall defining an exterior and an interior;
(b) a slide tube comprising a slide tube wall defining a slide tube interior and a slide tube exterior, said slide tube exterior being slidably arranged in said interior of said tubular shell, said slide tube connectible to a second member;
(c) a screw arranged for rotation in said interior of said tubular shell and including a threaded portion;
(d) a nut in threaded engagement with said threaded portion of said screw and constrained to said slide tube so that rotation of said screw will cause said slide tube to translate in said tubular shell altering a length of said screw actuator; and
(e) a guide constraining radial movement of said screw in said slide tube interior.
10. The screw actuator of claim 9 further comprising a follower nut in threaded engagement with said screw and spaced apart from said nut.
11. The screw actuator of claim 10 further comprising an indicator of contact between said follower nut and at least one of said nut and said slide tube.
12. The screw actuator of claim 9 further comprising a motor including a frame connected to said tubular shell and a shaft rotatable in said frame and drivingly connected to rotate said screw.
13. The vehicle transporter of claim 12 wherein said motor shaft is rotatable on a common axis with said screw.
14. The screw actuator of claim 9 wherein said threaded portion of said screw is arranged so that a force tending to displace said slide tube will not cause rotation of said screw.
15. The screw actuator of claim 9 wherein said threaded portion of said screw comprises an Acme thread having a lead angle not exceeding five degrees.
16. The screw actuator of claim 9 wherein at least one of said tubular shell and said slide tube is pivotally connectible, respectively, to one of said first member and said second member.
17. A screw actuator comprising:
(a) an elongate tubular first member;
(b) an elongate tubular second member slidable longitudinally in an interior of said tubular first member to vary a length of a portion of said second member longitudinally coextensive with said first member; and
(c) a screw rotatably supported by said first member and radially constrained in an interior of said tubular second member, rotation of said screw forcing said first and said second members to slide longitudinally relative to each other.
18. The screw actuator of claim 17 further comprising a motor including a frame connected to said first member and a shaft rotatable in said frame and drivingly connected to rotate said screw.
19. The screw actuator of claim 18 wherein said motor shaft is rotatable on a common axis with said screw.
20. The screw actuator of claim 17 wherein said screw comprises a threaded portion arranged so that a force tending to slide said members relative to each other will not cause rotation of said screw.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A compound represented by the general formula (1),
(Yq)n-m-M\u2514Xp-Rp-SH\ue8a0m\u2003\u2003(1)

wherein, in the formula, M represents an Sn atom, an Si atom, a Zr atom, a Ti atom or a Ge atom; Rp each independently represents a divalent organic group; Xp each independently represents a sulfur atom or an oxygen atom; Yq each independently represents a monovalent inorganic or organic group; m represents an integer of 2 to n; n represents a valency of a metal atom M; and when m is not less than 2, -(-Xp-Rp-SH) may be bonded to one another for forming a group of a ring structure.
2. The compound as set forth in claim 1, wherein when m is not less than 2, -(-Xp-Rp-SH) is bonded to one another for forming a group of a ring structure.
3. The compound as set forth in claim 1, wherein at least one of Rp contains a S atom.
4. A polythiol composition comprising the compound as set forth in claim 1.
5. A polymerizable composition comprising the compound as set forth in claim 1.
6. A polymerizable composition comprising the polythiol composition as set forth in claim 4.
7. A resin obtained by polymerization of the polymerizable composition as set froth in claim 5.
8. A resin obtained by reacting and curing the compound as set forth in claim 1 with a polyisocyanate compound.
9. A resin obtained by reacting and curing the polythiol composition as set forth in claim 4 with a polyisocyanate compound.