Author: claimsbot

1. A nonvolatile memory device, comprising:
a memory cell array including a plurality of cell strings, wherein each of the cell strings comprises memory cells stacked in a direction perpendicular to a substrate; and
a peripheral circuit connected to the memory cell array through a plurality of conductive lines, wherein the peripheral circuit comprises a plurality of transistors,
wherein each of the transistors is formed on the substrate,
wherein each of the transistors includes first and second regions, wherein the first and second regions comprise a conductive material different from a material included in the substrate, and wherein a gate electrode is disposed between the first and second regions,
wherein in at least one of the transistors, the first region is connected to at least one of the conductive lines through a plurality of first contact plugs extending in the direction perpendicular to the substrate, and a plurality of second contact plugs extending in the direction perpendicular to the substrate,
wherein each of the second contact plugs is disposed on a respective first contact plug, and
wherein a contact area of each of the first contact plugs is different from a contact area of each of the second contact plugs.
2. The nonvolatile memory device of claim 1, wherein the contact area of each of the first and second contact plugs is an upper surface of each contact plug that is parallel with the substrate.
3. The nonvolatile memory device of claim 1, wherein a first end of each of the first contact plugs is connected to the at least one conductive line and a second end of each of the first contact plugs is connected to a first end of each of the second contact plugs, and
wherein a second end of each of the second contact plugs is connected to the first region.
4. The nonvolatile memory device of claim 3, wherein a length of each of the first contact plugs is shorter than a length of each of the second contact plugs, and wherein the length extends in the direction perpendicular to the substrate.
5. The nonvolatile memory device of claim 3, wherein the contact area of each of the plurality of first contact plugs is smaller than the contact area of each of the plurality of second contact plugs.
6. The nonvolatile memory device of claim 3, wherein the number of the first contact plugs is greater than the number of the second contact plugs, and
wherein the first end of the second contact plugs is connected to the second end of each of at least two of the first contact plugs.
7. The nonvolatile memory device of claim 2, wherein a first length of each of the first contact plugs is shorter than a second length of each of the second contact plugs, wherein the first and second lengths extend in the direction perpendicular to the substrate.
8. The nonvolatile memory device of claim 1, wherein the second region of the at least one transistor is connected to at least one of the conductive lines through a plurality of third contact plugs and a plurality of fourth contact plugs, wherein the fourth contact plugs extend in the direction perpendicular to the substrate, and wherein the fourth contact plugs are disposed on the third contact plugs.
9. The nonvolatile memory device of claim 8, wherein a second end of each of the fourth contact plugs is connected to the second region and a first end of each of the fourth contact plugs is connected to a second end of each of the third contact plugs, and
wherein a first end of each of the third contact plugs is connected to the at least one conductive line.
10. The nonvolatile memory device of claim 9, wherein the contact area of each of the plurality of second contact plugs is greater than a contact area of each of the plurality of fourth contact plugs.
11. The nonvolatile memory device of claim 9, wherein the number of the second contact plugs is less than the number of the fourth contact plugs.
12. The nonvolatile memory device of claim 1, wherein a metal layer is disposed on the memory cell array and the peripheral circuit, and
wherein the metal layer includes the plurality of conductive lines.
13. The nonvolatile memory device of claim 1, wherein a length of the peripheral circuit extending in the direction perpendicular to the substrate is shorter than a length of the memory cell array extending in the direction perpendicular to the substrate.
14. A nonvolatile memory device, comprising:
a memory cell array including a plurality of cell strings, wherein each of the cell strings comprises memory cells stacked in a direction perpendicular to a substrate; and
a peripheral circuit connected to the memory cell array through a plurality of conductive lines, wherein the peripheral circuit comprises a plurality of transistors,
wherein at least one of the transistors includes a source region and a drain region,
wherein the source region is connected to a first conductive line of the plurality of conductive lines through a plurality of source contact plugs extending in a direction perpendicular to the substrate, wherein the drain region is connected to a second conductive line of the plurality of conductive lines through a plurality of drain contact plugs extending in the direction perpendicular to the substrate,
wherein a contact area of each of the source contact plugs is different from a contact area of each of the drain contact plugs, and
wherein the contact area of each of the source and drain contact plugs is an area parallel with the substrate.
15. The nonvolatile memory device of claim 14, wherein each of the source contact plugs includes:
a lower source contact plug comprising a second end connected to the source region; and
an upper source contact plug comprising a second end connected to a first end of the lower source contact plug, wherein a first end of the upper source contact plug is connected to the first conductive line, and
wherein each of the drain contact plugs includes:
a lower drain contact plug comprising a second end connected to the drain region; and
an upper drain contact plug comprising a second end connected to a first end of the lower drain contact plug, wherein a first end of the upper drain contact plug is connected to the second conductive line.
16. The nonvolatile memory device of claim 15, wherein a contact area of the lower source contact plug of each source contact plug is larger than a contact area of the upper source contact plug of each source contact plug.
17. The nonvolatile memory device of claim 15, wherein a contact area of the lower drain contact plug of each drain contact plug is larger than a contact area of the upper drain contact plug of each drain contact plug.
18. The nonvolatile memory device of claim 14, wherein the number of the source contact plugs is greater than the number of the drain contact plugs.
19. The nonvolatile memory device of claim 14, wherein each of the source contact plugs includes:
a lower source contact plug having a second end connected to the source region;
an intermediate source contact plug having a second end connected to a first end of the lower source contact plug; and
an upper source contact plug having a second end connected to a first end of the intermediate source contact plug, wherein a first end of the upper source contact plug is connected to the first conductive line, and
wherein each of the drain contact plugs includes:
a lower drain contact plug having a second end connected to the drain region;
an intermediate drain contact plug having a second end connected to a first end of the lower drain contact plug; and
an upper drain contact plug having a second end connected to a first end of the intermediate drain contact plug, wherein a first end of the upper drain contact plug is connected to the second conductive line.
20. The nonvolatile memory device of claim 19, wherein a contact area of the lower source contact plug of each source contact plug is larger than a contact area of the intermediate source contact plug of each source contact plug and a contact area of the upper source contact plug of each source contact plug.
21-30. (canceled)

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A dispensing system, comprising:
a base having one or more cavities therein;
a plurality of chutes configured to align within a subset of the cavities, wherein each of the chutes comprises an inlet that provides access to an open interior that facilitates storage of a plurality of items, and wherein the plurality of chutes are capable of dispensing the plurality of items in a \u201cfirst-in first out\u201d manner; and
an ice chest capable of cooling the plurality of chutes.
2. The system of claim 1, wherein at least one of the plurality of chutes comprises a curved inner surface that facilitates dispensing the plurality of items in the \u201cfirst-in first out\u201d manner.
3. The system of claim 1, wherein at least one of the plurality of chutes comprises a door capable of providing access to the plurality of items in the \u201cfirst-in first out\u201d manner.
4. The system of claim 1, wherein each of one or more of the chutes comprises a cap capable of covering the inlet.
5. The system of claim 1, wherein each of one or more of the chutes comprises one or more of a drip tray or a false bottom that enables fluids to escape the chute.
6. The system of claim 1, further comprising a sleeve mountable on the base and at least one side storage container, wherein the at least one side storage is attachable to the sleeve.
7. The system of claim 1, wherein the base comprises at least one of raised portions or dividers, wherein the raised portions or dividers facilitate alignment of the plurality of chutes within the base.
8. The system of claim 1, wherein the base comprises one or more of a drawer or a tray capable of storing at least one of fluids or items.
9. The system of claim 1, wherein the ice chest comprises a powered cooling device.
10. The system of claim 1, wherein the ice chest comprises at least one of a drain, a nipple, or a tap that facilitates drainage of the ice chest.
11. The system of claim 1, further comprising a plurality of candy trays capable of being aligned within the inlets of the plurality of chutes, wherein the plurality of candy trays are capable of storing a second plurality of items.
12. The system of claim 1, wherein at least one of the plurality of chutes is constructed at least in part from metal to facilitate cooling of the plurality of items.
13. The system of claim 1, further comprising a thermometer that indicates a temperature associated with one or more of the ice chest or at least one of the plurality of chutes.
14. A method of dispensing items, comprising:
placing a plurality of items into one or more chutes via an inlet of each chute;
storing the plurality of items in the plurality of chutes;
cooling the plurality of items stored in the plurality of chutes via an ice chest; and
dispensing the plurality of items in a \u201cfirst-in, first-out\u201d manner.
15. The method of claim 14, further comprising determining a temperature of at least one of the ice chest or the plurality of chutes.
16. The method of claim 14, further comprising storing a second plurality of items in one or more candy trays, wherein the one or more candy trays are aligned with inlets of the plurality of chutes.
17. The method of claim 14, wherein cooling the plurality of items comprises cooling the plurality of items via a powered cooling mechanism.
18. The method of claim 14, further comprising separating fluid from the plurality of items via one or more of drip trays or false bottoms.
19. A system for dispensing items, comprising:
a base comprising a plurality of cavities;
a plurality of chutes aligned in a subset of the cavities, wherein each of the chutes comprises an inlet that provides access to an open interior capable of storage of a plurality of items, a door that provides access to the plurality of items, at least one of a drip tray or false bottom for separation of juice from the plurality of items, and a curved inner surface that facilitates access to the plurality of items in a \u201cfirst-in, first-out\u201d manner;
and an ice chest arranged in an ice chest slot of the plurality of cavities, wherein the ice chest is arranged adjacent to the plurality of chutes and facilitates cooling of the plurality of items.
20. The system of claim 19, further comprising a thermometer that indicates a temperature associated with one or more of the ice chest or at least one of the plurality of chutes.

1. A dock leveler sealing system, comprising:
a barrier configured to be attached to a dock leveler;
a hinged region located in the barrier and configured to facilitate one portion of the barrier moving with respect to a second portion of the barrier; and
a biasing apparatus attached to the barrier and configured to position the first portion of the barrier at a bias relative to the second portion of the barrier.
2. The dock leveler sealing system of claim 1, wherein the barrier comprises a compressible pad.
3. The dock leveler sealing system of claim 2, wherein the barrier further comprises fabric substantially surrounding the compressible pad and wherein the hinged region comprises stitching through the pad and the fabric.
4. The dock leveler sealing system of claim 1, wherein the biasing apparatus comprises a weight.
5. The dock leveler sealing system of claim 4, wherein the weight extends substantially continuously across substantially across an entire dimension of the barrier.
6. The dock leveler sealing system of claim 4, wherein the weight is incorporated into a sleeve that is attached to the barrier at a first end of the sleeve and that is detached from the barrier at a second end of the sleeve.
7. The dock leveler sealing system of claim 4, wherein the barrier comprises a compressible pad and a fabric that substantially surrounds the compressible pad and wherein the weight is substantially surrounded by the fabric.
8. The dock leveler system of claim 1, wherein the biasing apparatus comprises:
a first rigid portion attached to first portion of the barrier; and
a second rigid portion attached to the second portion of the barrier and positioned in contact with the first rigid portion.
9. The dock leveler system of claim 8, wherein the first rigid portion comprises a fiberglass core substantially surrounded by a fabric.
10. The dock leveler system of claim 1, wherein the biasing apparatus extends substantially continuously across substantially an entire width of the barrier.
11. The dock leveler system of claim 8, wherein the first rigid portion and the second rigid portion are attached to each other.
12. The dock leveler system of claim 8, further comprising:
a spacer attached to the first rigid portion and in contact with the second rigid portion.
13. A method of providing a seal between a loading dock and an area outside of the loading dock, the method comprising:
attaching a barrier to a dock leveler;
including a hinged region in the barrier to facilitate one portion of the barrier moving with respect to a second portion of the barrier; and
biasing the first portion of the barrier relative to the second portion of the barrier.
14. The method of claim 13, wherein the including step comprises providing a compressible pad and a fabric substantially surrounding the compressible pad and stitching through the pad and the fabric to locally compress the pad and thereby form the hinged region.
15. The method of claim 13, wherein the biasing step comprises attaching a weight to the barrier.
16. The method of claim 13, wherein the biasing step comprises:
attaching a first rigid portion to a first portion of the barrier and a second rigid portion to the second portion of the barrier; and
positioning the first rigid portion to be in contact with the second rigid portion.
17. The method of claim 16, wherein the biasing step further comprises:
attaching the first rigid portion and the second rigid portion to each other.
18. The method of claim 16, wherein the biasing step further comprises:
attaching a spacer to the first rigid portion, wherein the spacer is also in contact with the second rigid portion.
19. The method of claim 13, wherein the biasing step causes the barrier to fold away from components of the dock leveler that come into contact with a pit floor when the dock leveler is in operation.
20. A dock leveler sealing system, comprising:
sealing means for providing a seal between a dock leveler and a pit floor, wherein the sealing means is configured to be attached to the dock leveler;
facilitating means for facilitating one portion of the sealing means moving with respect to a second portion of the sealing means, wherein the facilitating means is located in the sealing means; and
biasing means for positioning the first portion of the sealing means at a bias relative to the second portion of the sealing means, wherein the biasing means is attached to the sealing means.
21. A dock leveler sealing system, comprising:
a barrier configured to be attached to a dock leveler; and
a biasing apparatus attached to the barrier and configured to position a first portion of the barrier at a bias relative to a second portion of the barrier, wherein the biasing apparatus is further configured to bias the barrier even when not directly attached to the dock leveler.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A display controller comprising:
a graphic memory having a storage capacity defined by a first directional size multiplied by a second directional size;
a graphic memory control unit configured to convert two-dimensional (2-D) addresses to one-dimensional (1-D) addresses based on an input clock signal and first directional total pixel number of a display panel for displaying input data, configured to convert the 1-D addresses to physical 2-D addresses based on the first directional size and configured to control the graphic memory to store the input data, the display panel having a resolution corresponding to the first directional total pixel number multiplied by a second directional total pixel number of the display panel; and
a scan control unit configured to increase scan addresses one line by one line to display data stored in the graphic memory according to a display resolution.
2. The display controller of claim 1, wherein the graphic memory control unit comprises:
an address counter configured to generate the 2-D addresses based on the input clock signal and a control signal; and
an address converter configured to convert the 2-D addresses to the 1-D addresses based on the first directional total pixel number and configured to convert the 1-D addresses to the physical 2-D addresses based on the first directional size.
3. The display controller of claim 2, where the 2-D addresses are converted to the 1-D addresses based on a following equation 1:
LADDR=VXA\xd7HRES+VYA, \u2003\u2003equation 1

where VXA denotes page addresses of the 2-D addresses, VYA denotes column addresses of the 2-D addresses, HRES denotes the first directional total pixel number and LADDR denotes the 1-D addresses.
4. The display controller of claim 3, where the 1-D addresses are converted to the physical 2-D addresses based on a following equation 2:
PXA=LADDRHSIZE,
PYA=LADDR % HSIZE, \u2003\u2003equation 2

where HSIZE denotes the first directional size, PXA denotes physical page addresses of the physical 2-D addresses and PYA denotes physical column addresses of the physical 2-D addresses.
5. The display controller of claim 1, wherein the graphic memory includes a plurality of memory areas separate from each other.
6. The display controller of claim 5, further comprising an address mapper configured to interleave the physical 2-D addresses such that each input of a plurality of consecutive input data is not consecutively written to the same memory areas of the plurality memory areas.
7. The display controller of claim 1, further comprising a control register configured to receive a control signal to provide information of the first directional total pixel number and the first directional size to the graphic memory control unit and to the scan control unit.
8. The display controller of claim 7, wherein the control register is configured to receive the control signal to provide rotation information of an image indicating a display mode of the display panel to the graphic memory control unit and to the scan control unit.
9. The display controller of claim 1, wherein the scan control unit comprises:
an address counter configured to generate 2-D scan addresses based on an internal clock signal and a control signal; and
an address converter configured to convert the 2-D scan addresses to 1-D scan addresses based on the first directional total pixel number and configured to convert the 1-D scan addresses to physical 2-D scan addresses based on the first directional size.
10. The display controller of claim 9, where the 2-D scan addresses are converted to the 1-D addresses based on a following equation 3:
SLADDR=SVXA\xd7HRES+SVYA, \u2003\u2003equation 3

where SVXA denotes scan page addresses of the 2-D scan addresses, SVYA denotes scan column addresses of the 2-D scan addresses, HRES denotes the first directional total pixel number and SLADDR denotes the 1-D scan addresses.
11. The display controller of claim 10, where the 1-D scan addresses are converted to the physical 2-D scan addresses based on a following equation 4:
SPXA=SLADDRHSIZE,
SPYA=LADDR % HSIZE, \u2003\u2003equation 4

where HSIZE denotes the first directional size, SPXA denotes physical scan page addresses of the physical 2-D scan addresses and SPYA denotes physical scan column addresses of the physical 2-D scan addresses.
12. A display device comprising:
a display panel; and
a display controller configured to control the display panel, the display panel comprising:
a graphics memory having a storage capacity defined by a first directional size multiplied by a second directional size;
a graphic memory control unit configured to convert two-dimensional (2-D) addresses to one-dimensional (1-D) addresses based on an input clock signal and first directional total pixel number of the display panel, configured to the 1D addresses to physical 2D addresses based on the first directional size and configured to control the graphic memory to store the input data, the display panel having a resolution corresponding to the first directional total pixel number multiplied by second directional total pixel number of the display panel; and
a scan control unit configured to increase scan addresses one line by one line to display data stored in the graphic memory according to a display resolution.
13. The display device of claim 12, wherein the display controller further comprises a control register configured to receive a control signal to provide information of the first directional total pixel number and the first directional size to the graphic memory control unit and to the scan control unit.
14. A display controller comprising:
a graphic memory control unit configured to convert first two-dimensional (2-D) addresses to physical 2-D addresses based on an input clock signal, a first directional total pixel number of a display panel for displaying input data and a first directional size of a graphic memory, the graphic memory control unit configured to control the graphic memory to store the input data, the display panel having a resolution corresponding to the first directional total pixel number multiplied by a second directional total pixel number of the display panel, a graphic memory having a storage capacity defined by the first directional size multiplied by a second directional size; and
a scan control unit configured to increase scan addresses one line by one line to display data stored in the graphic memory.
15. The display controller of claim 14, wherein the graphic memory control unit comprises:
an address counter configured to generate the first 2-D addresses based on the input clock signal and a control signal; and
an address converter configured to convert the 2-D addresses to the physical 2-D addresses based on the first directional total pixel number and the first directional size.
16. The display controller of claim 15, where the first 2-D addresses are converted to the physical 2-D addresses based on a following equation 5:
PXA=(VXA\xd7HRES+VYA)HSIZE,
PYA=(VXA\xd7HRES+VYA)% HSIZE, \u2003\u2003equation 5

where VXA denotes page addresses of the first 2-D addresses, VYA denotes column addresses of the first 2-D addresses, HRES denotes the first directional total pixel number, HSIZE denotes the first directional size, PXA denotes physical page addresses of the physical 2-D addresses and PYA denotes physical column addresses of the physical 2-D addresses.
17. The display controller of claim 14, wherein the scan control unit comprises:
an address counter configured to generate 2-D scan addresses based on an internal clock signal and a control signal; and
an address converter configured to convert the 2-D scan addresses to physical 2-D scan addresses based on the first directional total pixel number and the first directional size.
18. The display controller of claim 17, where the 2-D scan addresses are converted to the physical 2-D scan addresses based on a following equation 6:
SPXA=(SVXA\xd7HRES+VYA)HSIZE,
SPYA=(SVXA\xd7HRES+VYA)% HSIZE, \u2003\u2003equation 6

where SVXA denotes scan page addresses of the 2-D scan addresses, SVYA denotes scan column addresses of the 2-D scan addresses, HRES denotes the first directional total pixel number, HSIZE denotes the first directional size, SPXA denotes physical scan page addresses of the physical 2-D scan addresses and SPYA denotes physical scan column addresses of the physical 2-D scan addresses.