1. A dock leveler sealing system, comprising:
a barrier configured to be attached to a dock leveler;
a hinged region located in the barrier and configured to facilitate one portion of the barrier moving with respect to a second portion of the barrier; and
a biasing apparatus attached to the barrier and configured to position the first portion of the barrier at a bias relative to the second portion of the barrier.
2. The dock leveler sealing system of claim 1, wherein the barrier comprises a compressible pad.
3. The dock leveler sealing system of claim 2, wherein the barrier further comprises fabric substantially surrounding the compressible pad and wherein the hinged region comprises stitching through the pad and the fabric.
4. The dock leveler sealing system of claim 1, wherein the biasing apparatus comprises a weight.
5. The dock leveler sealing system of claim 4, wherein the weight extends substantially continuously across substantially across an entire dimension of the barrier.
6. The dock leveler sealing system of claim 4, wherein the weight is incorporated into a sleeve that is attached to the barrier at a first end of the sleeve and that is detached from the barrier at a second end of the sleeve.
7. The dock leveler sealing system of claim 4, wherein the barrier comprises a compressible pad and a fabric that substantially surrounds the compressible pad and wherein the weight is substantially surrounded by the fabric.
8. The dock leveler system of claim 1, wherein the biasing apparatus comprises:
a first rigid portion attached to first portion of the barrier; and
a second rigid portion attached to the second portion of the barrier and positioned in contact with the first rigid portion.
9. The dock leveler system of claim 8, wherein the first rigid portion comprises a fiberglass core substantially surrounded by a fabric.
10. The dock leveler system of claim 1, wherein the biasing apparatus extends substantially continuously across substantially an entire width of the barrier.
11. The dock leveler system of claim 8, wherein the first rigid portion and the second rigid portion are attached to each other.
12. The dock leveler system of claim 8, further comprising:
a spacer attached to the first rigid portion and in contact with the second rigid portion.
13. A method of providing a seal between a loading dock and an area outside of the loading dock, the method comprising:
attaching a barrier to a dock leveler;
including a hinged region in the barrier to facilitate one portion of the barrier moving with respect to a second portion of the barrier; and
biasing the first portion of the barrier relative to the second portion of the barrier.
14. The method of claim 13, wherein the including step comprises providing a compressible pad and a fabric substantially surrounding the compressible pad and stitching through the pad and the fabric to locally compress the pad and thereby form the hinged region.
15. The method of claim 13, wherein the biasing step comprises attaching a weight to the barrier.
16. The method of claim 13, wherein the biasing step comprises:
attaching a first rigid portion to a first portion of the barrier and a second rigid portion to the second portion of the barrier; and
positioning the first rigid portion to be in contact with the second rigid portion.
17. The method of claim 16, wherein the biasing step further comprises:
attaching the first rigid portion and the second rigid portion to each other.
18. The method of claim 16, wherein the biasing step further comprises:
attaching a spacer to the first rigid portion, wherein the spacer is also in contact with the second rigid portion.
19. The method of claim 13, wherein the biasing step causes the barrier to fold away from components of the dock leveler that come into contact with a pit floor when the dock leveler is in operation.
20. A dock leveler sealing system, comprising:
sealing means for providing a seal between a dock leveler and a pit floor, wherein the sealing means is configured to be attached to the dock leveler;
facilitating means for facilitating one portion of the sealing means moving with respect to a second portion of the sealing means, wherein the facilitating means is located in the sealing means; and
biasing means for positioning the first portion of the sealing means at a bias relative to the second portion of the sealing means, wherein the biasing means is attached to the sealing means.
21. A dock leveler sealing system, comprising:
a barrier configured to be attached to a dock leveler; and
a biasing apparatus attached to the barrier and configured to position a first portion of the barrier at a bias relative to a second portion of the barrier, wherein the biasing apparatus is further configured to bias the barrier even when not directly attached to the dock leveler.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A display controller comprising:
a graphic memory having a storage capacity defined by a first directional size multiplied by a second directional size;
a graphic memory control unit configured to convert two-dimensional (2-D) addresses to one-dimensional (1-D) addresses based on an input clock signal and first directional total pixel number of a display panel for displaying input data, configured to convert the 1-D addresses to physical 2-D addresses based on the first directional size and configured to control the graphic memory to store the input data, the display panel having a resolution corresponding to the first directional total pixel number multiplied by a second directional total pixel number of the display panel; and
a scan control unit configured to increase scan addresses one line by one line to display data stored in the graphic memory according to a display resolution.
2. The display controller of claim 1, wherein the graphic memory control unit comprises:
an address counter configured to generate the 2-D addresses based on the input clock signal and a control signal; and
an address converter configured to convert the 2-D addresses to the 1-D addresses based on the first directional total pixel number and configured to convert the 1-D addresses to the physical 2-D addresses based on the first directional size.
3. The display controller of claim 2, where the 2-D addresses are converted to the 1-D addresses based on a following equation 1:
LADDR=VXA\xd7HRES+VYA, \u2003\u2003equation 1
where VXA denotes page addresses of the 2-D addresses, VYA denotes column addresses of the 2-D addresses, HRES denotes the first directional total pixel number and LADDR denotes the 1-D addresses.
4. The display controller of claim 3, where the 1-D addresses are converted to the physical 2-D addresses based on a following equation 2:
PXA=LADDRHSIZE,
PYA=LADDR % HSIZE, \u2003\u2003equation 2
where HSIZE denotes the first directional size, PXA denotes physical page addresses of the physical 2-D addresses and PYA denotes physical column addresses of the physical 2-D addresses.
5. The display controller of claim 1, wherein the graphic memory includes a plurality of memory areas separate from each other.
6. The display controller of claim 5, further comprising an address mapper configured to interleave the physical 2-D addresses such that each input of a plurality of consecutive input data is not consecutively written to the same memory areas of the plurality memory areas.
7. The display controller of claim 1, further comprising a control register configured to receive a control signal to provide information of the first directional total pixel number and the first directional size to the graphic memory control unit and to the scan control unit.
8. The display controller of claim 7, wherein the control register is configured to receive the control signal to provide rotation information of an image indicating a display mode of the display panel to the graphic memory control unit and to the scan control unit.
9. The display controller of claim 1, wherein the scan control unit comprises:
an address counter configured to generate 2-D scan addresses based on an internal clock signal and a control signal; and
an address converter configured to convert the 2-D scan addresses to 1-D scan addresses based on the first directional total pixel number and configured to convert the 1-D scan addresses to physical 2-D scan addresses based on the first directional size.
10. The display controller of claim 9, where the 2-D scan addresses are converted to the 1-D addresses based on a following equation 3:
SLADDR=SVXA\xd7HRES+SVYA, \u2003\u2003equation 3
where SVXA denotes scan page addresses of the 2-D scan addresses, SVYA denotes scan column addresses of the 2-D scan addresses, HRES denotes the first directional total pixel number and SLADDR denotes the 1-D scan addresses.
11. The display controller of claim 10, where the 1-D scan addresses are converted to the physical 2-D scan addresses based on a following equation 4:
SPXA=SLADDRHSIZE,
SPYA=LADDR % HSIZE, \u2003\u2003equation 4
where HSIZE denotes the first directional size, SPXA denotes physical scan page addresses of the physical 2-D scan addresses and SPYA denotes physical scan column addresses of the physical 2-D scan addresses.
12. A display device comprising:
a display panel; and
a display controller configured to control the display panel, the display panel comprising:
a graphics memory having a storage capacity defined by a first directional size multiplied by a second directional size;
a graphic memory control unit configured to convert two-dimensional (2-D) addresses to one-dimensional (1-D) addresses based on an input clock signal and first directional total pixel number of the display panel, configured to the 1D addresses to physical 2D addresses based on the first directional size and configured to control the graphic memory to store the input data, the display panel having a resolution corresponding to the first directional total pixel number multiplied by second directional total pixel number of the display panel; and
a scan control unit configured to increase scan addresses one line by one line to display data stored in the graphic memory according to a display resolution.
13. The display device of claim 12, wherein the display controller further comprises a control register configured to receive a control signal to provide information of the first directional total pixel number and the first directional size to the graphic memory control unit and to the scan control unit.
14. A display controller comprising:
a graphic memory control unit configured to convert first two-dimensional (2-D) addresses to physical 2-D addresses based on an input clock signal, a first directional total pixel number of a display panel for displaying input data and a first directional size of a graphic memory, the graphic memory control unit configured to control the graphic memory to store the input data, the display panel having a resolution corresponding to the first directional total pixel number multiplied by a second directional total pixel number of the display panel, a graphic memory having a storage capacity defined by the first directional size multiplied by a second directional size; and
a scan control unit configured to increase scan addresses one line by one line to display data stored in the graphic memory.
15. The display controller of claim 14, wherein the graphic memory control unit comprises:
an address counter configured to generate the first 2-D addresses based on the input clock signal and a control signal; and
an address converter configured to convert the 2-D addresses to the physical 2-D addresses based on the first directional total pixel number and the first directional size.
16. The display controller of claim 15, where the first 2-D addresses are converted to the physical 2-D addresses based on a following equation 5:
PXA=(VXA\xd7HRES+VYA)HSIZE,
PYA=(VXA\xd7HRES+VYA)% HSIZE, \u2003\u2003equation 5
where VXA denotes page addresses of the first 2-D addresses, VYA denotes column addresses of the first 2-D addresses, HRES denotes the first directional total pixel number, HSIZE denotes the first directional size, PXA denotes physical page addresses of the physical 2-D addresses and PYA denotes physical column addresses of the physical 2-D addresses.
17. The display controller of claim 14, wherein the scan control unit comprises:
an address counter configured to generate 2-D scan addresses based on an internal clock signal and a control signal; and
an address converter configured to convert the 2-D scan addresses to physical 2-D scan addresses based on the first directional total pixel number and the first directional size.
18. The display controller of claim 17, where the 2-D scan addresses are converted to the physical 2-D scan addresses based on a following equation 6:
SPXA=(SVXA\xd7HRES+VYA)HSIZE,
SPYA=(SVXA\xd7HRES+VYA)% HSIZE, \u2003\u2003equation 6
where SVXA denotes scan page addresses of the 2-D scan addresses, SVYA denotes scan column addresses of the 2-D scan addresses, HRES denotes the first directional total pixel number, HSIZE denotes the first directional size, SPXA denotes physical scan page addresses of the physical 2-D scan addresses and SPYA denotes physical scan column addresses of the physical 2-D scan addresses.