1. An ejection apparatus for ejecting material from a liquid at a plurality of ejection locations, the apparatus comprising a printhead having
a plurality of channels through each of which liquid flows in use to supply liquid to a respective ejection location at an open end of the channel, and a plurality of channels through each of which liquid flows in use to remove depleted liquid from the respective ejection location at an open end of the channel, wherein each channel is one of a pair of co-operating channels, the two cooperating channels thus having a common end,
an ejection electrode disposed at each ejection location and by means of which an electric field is created in use to cause the ejection of material from the liquid, and
an electrically conductive path to each ejection electrode for supplying a voltage to the ejection electrode in use,
wherein
the channels are isolated from one another and separated from the electrically conductive paths over substantially the whole of the length of the electrically conductive paths.
2. Apparatus according to claim 1, wherein the channels have longitudinal axes which are disposed at an angle to one another so that liquid is brought to the ejection location and removed from it from the sides, the electrically conductive paths being provided substantially along a central axis bisecting the axes of the channels.
3. Apparatus according to claim 2, wherein the channels are formed along the edges of a pair of prismatic bodies separate from a component which forms the ejection locations.
4. Apparatus according to claim 1, wherein the individual channels are separated from one another by a plurality of walls and isolation of the individual channels is achieved by closing the tops of the channels over a majority of their length.
5. Apparatus according to claim 4, wherein the individual channels are closed, over a majority of their length, by means of a pair of side covers, each of which is common to all of the channels on a respective side and which engages the walls.
6. Apparatus according to claim 4, wherein, at the open end of the channels, lands separate the ejection locations from one another.
7. Apparatus according to claim 6, wherein protrusions are also defined by lands between the lands which separate individual ejection locations from one another, the protrusions of the ejection location-defining lands being smaller in width and defining, on each side thereof, passages for liquid flow between the ejection location-separating lands.
8. Apparatus according to claim 7, wherein, in order to separate the ejection location-defining lands from the ejection location-separating lands, spacers are provided on the flanks of the ejection location-defining lands at least over most of their length, the separators being formed integrally with the protrusion-defining lands, the channel-separating lands or both.
9. Apparatus according to claim 7, wherein the lands and separators are formed by a component located between prismatic bodies in which the channels are formed.
10. Apparatus according to claim 9, wherein the separators are metallised to provide the electrically conducting paths to the ejection electrodes.
11. An ejection apparatus according to claim 1, wherein each electrically conductive path is disposed so as to be out of contact with the liquid, in use, over substantially the whole of its length.
12. An ejection apparatus according to claim 1, wherein each electrically conductive path is disposed so as to be in contact with the liquid, in use, solely at the region of the corresponding ejection location.
13. An ejection apparatus for ejecting material from a liquid at a plurality of ejection locations, the apparatus comprising a printhead having
a plurality of channels through each of which liquid flows in use to supply liquid to a respective ejection location at an open end of the channel, and a plurality of channels through each of which liquid flows in use to remove depleted liquid from the respective ejection location at an open end of the channel, wherein each channel is one of a pair of co-operating channels, the two cooperating channels thus having a common end,
an ejection electrode disposed at each ejection location and by means of which an electric field is created in use to cause the ejection of material from the liquid, and
an electrically conductive path to each ejection electrode disposed so as to be out of contact with the liquid, in use, over substantially the whole of its length, for supplying a voltage to the ejection electrode in use,
wherein
the channels are isolated from one another and separated from the electrically conductive paths over substantially the whole of the length of the electrically conductive paths.
14. An ejection apparatus for ejecting material from a liquid at a plurality of ejection locations, the apparatus comprising a printhead having
a plurality of channels through each of which liquid flows in use to supply liquid to a respective ejection location at an open end of the channel, and a plurality of channels through each of which liquid flows in use to remove depleted liquid from the respective ejection location at an open end of the channel, wherein each channel is one of a pair of co-operating channels, the two cooperating channels thus having a common end,
an ejection electrode disposed at each ejection location and by means of which an electric field is created in use to cause the ejection of material from the liquid, and
an electrically conductive path to each ejection electrode disposed as to be in contact with the liquid, in use, solely at the region of the corresponding ejection location for supplying a voltage to the ejection electrode in use,
wherein
the channels are isolated from one another and separated from the electrically conductive paths over substantially the whole of the length of the electrically conductive paths.
15. An ejection apparatus for ejecting material from a liquid at a plurality of ejection locations, the apparatus comprising a printhead having
a plurality of channels through each of which liquid flows in use to or from a respective ejection location at an open end of the channel, each channel being one of two co-operating channels, one of which supplies liquid to a respective ejection location and the other of which removes depleted liquid from the same ejection location, the two cooperating channels thus having a common open end,
an ejection electrode disposed at each ejection location and by means of which an electric field is created in use to cause the ejection of material from the liquid, and
an electrically conductive path to each ejection electrode for supplying a voltage to the ejection electrode in use; wherein
the channels are isolated from one another and separated from the electrically conductive paths over substantially the whole of the length of the electrically conductive paths; and wherein
the channels have longitudinal axes which are disposed at an angle to one another so that liquid is brought to the ejection location and removed from it from the sides, the electrically conductive paths being provided substantially along a central axis bisecting the axes of the channels.
16. Apparatus according to claim 15, wherein the channels are formed along the edges of a pair of prismatic bodies separate from a component which forms the ejection locations.
17. Apparatus according to claim 15, wherein the individual channels are separated from one another by a plurality of walls and isolation of the individual channels is achieved by closing the tops of the channels over a majority of their length.
18. Apparatus according to claim 17, wherein the individual channels are closed, over a majority of their length, by means of a pair of side covers, each of which is common to all of the channels on a respective side and which engages the walls.
19. Apparatus according to claim 17, wherein, at the open end of the channels, lands separate the ejection locations from one another.
20. Apparatus according to claim 19, wherein protrusions are also defined by lands between the lands which separate individual ejection locations from one another, the protrusions of the ejection location-defining lands being smaller in width and defining, on each side thereof, passages for liquid flow between the ejection location-separating lands.
21. Apparatus according to claim 20, wherein, in order to separate the ejection location-defining lands from the ejection location-separating lands, spacers are provided on the flanks of the ejection location-defining lands at least over most of their length, the separators being formed integrally with the protrusion-defining lands, the channel-separating lands or both.
22. Apparatus according to claim 20, wherein the lands and separators are formed by a component located between prismatic bodies in which the channels are formed.
23. Apparatus according to claim 22, wherein the separators are metallised to provide the electrically conducting paths to the ejection electrodes.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor integrated circuit device having a plurality of clock driver circuits dispersedly arranged in a core region in a semiconductor integrated circuit, the clock driver circuits supplying appropriate clock signals to a plurality of cells using the clock signals arranged in the core region through clock signal supply lines interconnected in a mesh-like form in the core region,
wherein said plurality of clock driver circuits are arranged by increasing or decreasing the number of rows of transistors in each of the clock driver circuits based on the density of said cells using the clock signals in the neighboring regions of each of said dispersedly arranged clock driver circuits, by using MOS transistors of MOS transistor groups arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which said core region is divided.
2. A semiconductor integrated circuit device having clock driver circuits dispersedly arranged in a core region in a semiconductor integrated circuit, the clock driver circuits supplying appropriate clock signals to a plurality of cells using the clock signals arranged in the core region through clock signal supply lines interconnected in a mesh-like form in the core region,
wherein said plurality of clock driver circuits are arranged by increasing or decreasing the number of clock driver circuits in the neighboring regions based on the density of said cells using the clock signals in the neighboring regions of each of said dispersedly arranged clock driver circuits, by using MOS transistors of MOS transistor groups arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which said core region is divided.
3. A semiconductor integrated circuit device having clock driver circuits dispersedly arranged in a core region in a semiconductor integrated circuit, the clock driver circuits supplying appropriate clock signals to a plurality of cells using the clock signals arranged in the core region through clock signal supply lines interconnected in a mesh-like form in the core region,
wherein said plurality of clock driver circuits are arranged by shifting each of the clock driver circuits based on the density of said cells using the clock signals in the neighboring regions of each of said dispersedly arranged clock driver circuits, by using MOS transistors of MOS transistor groups arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which said core region is divided.
4. A semiconductor integrated circuit device having clock driver circuits dispersedly arranged in a core region in a semiconductor integrated circuit, the clock driver circuits supplying appropriate clock signals to a plurality of cells using the clock signals arranged in the core region through clock signal supply lines interconnected in a mesh-like form in the core region,
wherein said plurality of clock driver circuits are arranged by making a combination of increasing or decreasing the number of rows of transistors in each of the clock driver circuits, increasing or decreasing the number of clock driver circuits, andor shifting each of the clock driver circuits based on the density of said cells using the clock signals in the neighboring regions of each of said dispersedly arranged clock driver circuits, by using MOS transistors of MOS transistor groups arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which said core region is divided.
5. A layout method of clock driver circuits used in a semiconductor integrated circuit device having a plurality of clock driver circuits dispersedly arranged in a core region in a semiconductor integrated circuit, the clock driver circuits supplying appropriate clock signals to a plurality of cells using the clock signals arranged in the core region through clock signal supply lines interconnected in a mesh-like form in the core region, the method comprising the steps of:
arranging MOS transistors of MOS transistor groups in an array in the peripheral region and bounded region portions in a plurality of divided regions into which said core region is divided;
performing a layout process for cells in said divided regions; and
increasing or decreasing the number of rows of transistors in each of the clock driver circuits based on the density of said cells using the clock signals in the neighboring regions of each of said dispersedly arranged clock driver circuits, by using the MOS transistors of the MOS transistor groups in an array in said arrangement step.
6. A layout method of clock driver circuits used in a semiconductor integrated circuit device having a plurality of clock driver circuits dispersedly arranged in a core region in a semiconductor integrated circuit, the clock driver circuits supplying appropriate clock signals to a plurality of cells using the clock signals arranged in the core region through clock signal supply lines interconnected in a mesh-like form in the core region, the method comprising the steps of:
arranging MOS transistors of MOS transistor groups in an array in the peripheral region and bounded region portions in a plurality of divided regions into which said core region is divided;
performing a layout process for cells in said divided regions; and
increasing or decreasing the number of clock driver circuits in the neighboring regions based on the density of said cells using the clock signals in the neighboring regions of each of said dispersedly arranged clock driver circuits, by using the MOS transistors of the MOS transistor groups in an array in said arrangement step.
7. A layout method of clock driver circuits used in a semiconductor integrated circuit device having a plurality of clock driver circuits dispersedly arranged in a core region in a semiconductor integrated circuit, the clock driver circuits supplying appropriate clock signals to a plurality of cells using the clock signals arranged in the core region through clock signal supply lines interconnected in a mesh-like form in the core region, the method comprising the steps of:
arranging MOS transistors of MOS transistor groups in an array in the peripheral region and bounded region portions in a plurality of divided regions into which said core region is divided;
performing a layout process for cells in said divided regions; and
shifting each of the clock driver circuits based on the density of said cells using the clock signals in the neighboring regions of each of said dispersedly arranged clock driver circuits, by using the MOS transistors of the MOS transistor groups in an array in said arrangement step.
8. A layout method of clock driver circuits used in a semiconductor integrated circuit device having a plurality of clock driver circuits dispersedly arranged in a core region in a semiconductor integrated circuit, the clock driver circuits supplying appropriate clock signals to a plurality of cells using the clock signals arranged in the core region through clock signal supply lines interconnected in a mesh-like form in the core region, the method comprising the steps of:
arranging MOS transistors of MOS transistor groups in an array in the peripheral region and bounded region portions in a plurality of divided regions into which said core region is divided;
performing a layout process for cells in said divided regions; and
making a combination of increasing or decreasing the number of rows of transistors in each of the clock driver circuits, increasing or decreasing the number of clock driver circuits, andor shifting each of the clock driver circuits based on the density of said cells using the clock signals in the neighboring regions of each of said dispersedly arranged clock driver circuits, by using the MOS transistors of the MOS transistor groups in an array in said arrangement step.