1. A non-transitory program storage device, readable by a programmable control device and comprising instructions stored thereon to cause the programmable control device to:
receive non-linear encoded input data, wherein the received non-linear encoded input data has a first quantized bit-depth;
determine a first transfer function; and
transform the received non-linear encoded input data into linear output data having a second quantized bit-depth according to the first transfer function,
wherein the first transfer function comprises a piecewise linear function, the piecewise linear function defined by a first linear segment followed, after a first input value, by an offset curve,
wherein the first linear segment is continuous with the offset curve at the first input value, and
wherein the slopes of the first linear segment and the offset curve at the first input value are the same.
2. The non-transitory program storage device of claim 1, wherein the offset curve comprises a power function.
3. The non-transitory program storage device of claim 1, wherein the offset curve comprises a polynomial function.
4. The non-transitory program storage device of claim 1, wherein the instructions further comprise instructions to cause the programmable control device to apply a stochastic dither to the non-linear encoded input data before the instructions to transform the received non-linear encoded input data are performed.
5. The non-transitory program storage device of claim 1, wherein the first linear segment has a first slope value, and wherein the first slope value is limited, at least in part, by the difference between the second quantized bit-depth and the first quantized bit-depth.
6. The non-transitory program storage device of claim 1, wherein the first transfer function is determined based, at least in part, on an area under an ideal power function curve defined over the same range of input values as the first transfer function.
7. The non-transitory program storage device of claim 1, wherein the first transfer function is determined based, at least in part, on minimizing an error between an ideal power function curve defined over the same range of input values as the first transfer function and the first transfer function.
8. A system, comprising:
a memory having, stored therein, computer program code; and
a programmable control device operatively coupled to the memory and comprising instructions stored thereon to cause the programmable control device to:
receive non-linear encoded input data, wherein the received non-linear encoded input data has a first quantized bit-depth;
determine a first transfer function; and
transform the received non-linear encoded input data into linear output data having a second quantized bit-depth according to the first transfer function,
wherein the first transfer function comprises a piecewise linear function, the piecewise linear function defined by a first linear segment followed, after a first input value, by an offset curve,
wherein the first linear segment is continuous with the offset curve at the first input value, and
wherein the slopes of the first linear segment and the offset curve at the first input value are the same.
9. The system of claim 8, wherein the offset curve comprises a power function.
10. The system of claim 8, wherein the offset curve comprises a polynomial function.
11. The system of claim 8, wherein the instructions further comprise instructions to cause the programmable control device to apply a stochastic dither to the non-linear encoded input data before the instructions to transform the received non-linear encoded input data are performed.
12. The system of claim 8, wherein the first linear segment has a first slope value, and wherein the first slope value is limited, at least in part, by the difference between the second quantized bit-depth and the first quantized bit-depth.
13. The system of claim 8, wherein the first transfer function is determined based, at least in part, on an area under an ideal power function curve defined over the same range of input values as the first transfer function.
14. The system of claim 8, wherein the first transfer function is determined based, at least in part, on minimizing an error between an ideal power function curve defined over the same range of input values as the first transfer function and the first transfer function.
15. A method, comprising:
receiving non-linear encoded input data, wherein the received non-linear encoded input data has a first quantized bit-depth;
determining a first transfer function; and
transforming the received non-linear encoded input data into linear output data having a second quantized bit-depth according to the first transfer function,
wherein the first transfer function comprises a piecewise linear function, the piecewise linear function defined by a first linear segment followed, after a first input value, by an offset curve,
wherein the first linear segment is continuous with the offset curve at the first input value, and
wherein the slopes of the first linear segment and the offset curve at the first input value are the same.
16. The method of claim 15, wherein the offset curve comprises a power function or a polynomial function.
17. The method of claim 15, further comprising applying a stochastic dither to the non-linear encoded input data before the act of transforming the received non-linear encoded input data is performed.
18. The method of claim 15, wherein the first linear segment has a first slope value, and wherein the first slope value is limited, at least in part, by the difference between the second quantized bit-depth and the first quantized bit-depth.
19. The method of claim 15, wherein the first transfer function is determined based, at least in part, on an area under an ideal power function curve defined over the same range of input values as the first transfer function.
20. The method of claim 15, wherein the first transfer function is determined based, at least in part, on minimizing an error between an ideal power function curve defined over the same range of input values as the first transfer function and the first transfer function.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1.-51. (canceled)
52. A method for performing vector operations in parallel in one step, the method comprising the steps of:
providing a vector register file including a plurality of vector registers;
storing a first input vector in said vector register file;
storing a control vector in said vector register file, wherein said control vector is selected as a source operand of said vector operations;
selecting a condition flag from a plurality of condition flags for each vector element position in accordance with a condition select field from a vector instruction, said plurality of condition flags are derived from results of executing a prior instruction sequence;
mapping the elements of said first input vector to the elements of a first output vector, in accordance with a first field of respective element of said control vector; and
storing elements of said first output vector on an element-by-element basis conditionally, if mask bit of respective element of said control vector is interpreted as false and in accordance with respective said selected condition flag,
wherein said vector operations are performed in parallel in one instruction.
53. The method of claim 52, wherein one of said plurality of condition flags for each respective vector element position is defined as always true.
54. (canceled)
55. (canceled)
56. The method of claim 52, wherein each of said first input vector, said second input vector, said first output vector, said second output vector, and said control vector each have N vector elements.
57. The method of claim 56, wherein the number of said N vector elements is selected from the group consisting of {8, 16, 32, 64, 128, 256}.
58. The method of claim 56, wherein the number of said N vector elements is an integer value between 2 and 256, and each vector element is a fixed-point integer or a floating-point number.
59. An apparatus for performing vector operations in parallel in accordance with a control vector register and condition flags, the apparatus comprising:
a vector register file including a plurality of vector registers with a plurality of read data ports and at least one write data port, wherein some of said plurality of vector registers are accessed in parallel and at the same time, said control vector register is part of said vector register file;
a vector condition flag register for storing a plurality of condition flags for each vector element position, each element of said plurality of condition flags defining a true or false condition value, and a condition select logic that selects one of a plurality of condition flags for each vector element position in accordance with a condition select field from a vector instruction;
a first select logic coupled to said vector register file for mapping elements of a first vector register in accordance with said control vector register; and
an enable logic coupled to output of said first select logic for controlling storing elements of an output vector register in said vector register file on an element-by-element basis in accordance with a user-defined mask bit for each vector element position of said control vector register and output of said condition select logic for each vector element position,
wherein said vector operations are performed in parallel by one instruction.
60. The apparatus of claim 59, wherein one of said plurality of condition flags for each vector element position of said vector condition flag register is hard wired to always true.
61. (canceled)
62. (canceled)
63. The apparatus of claim 59, wherein each element of a vector register is a floating-point number or a fixed-point integer.
64. The apparatus of claim 59, wherein all vector registers have N vector elements, N being an integer value between 2 and 256.
65. A method for performing vector operations in parallel in one step, the method comprising:
storing a first input vector;
storing a control vector;
selecting a condition flag from a plurality of condition flags for each vector element position, said plurality of condition flags are derived from results of executing a prior instruction sequence;
mapping the elements of said first input vector to the elements of a first output vector, in accordance with a first field of respective element of said control vector; and
storing elements of said first output vector on an element-by-element basis conditionally in accordance with mask bit of respective element of said control vector is interpreted as false and in accordance with respective said selected condition flag, wherein one of said plurality of condition flags for each respective vector element position is defined as always true.