Author: claimsbot

1. A bottle and cap assembly for containing a liquid nutrient having a pH equal to or greater than about 2.5, said bottle having an interior surface having a polymeric layer thereon, said polymeric layer having a metal-ion sequestering agent for removing a designated metal ion from said liquid nutrient for inhibiting growth of microbes in said liquid nutrient, said metal-ion sequestering agent comprises derivatized nanoparticles comprising inorganic nanoparticles having an attached metal-ion sequestrant, wherein said inorganic nanoparticles have an average particle size of less than 200 nm and the derivatized nanoparticles have a stability constant greater than 1010 with iron (III), said metal-ion sequestering agent is immobilized in said polymeric layer and comprises 0.1 to 50.0% by weight of the polymeric layer, and the polymeric layer contacts the liquid contained therein and is permeable to water.
2. A bottle and cap assembly according to claim 1 wherein said metal-ion sequestering agent is immobilized on the surface of said bottle and has a stability constant greater than 1010 with iron (III).
3. A bottle and cap assembly according to claim 1 wherein said sequestering agent is immobilized on the surface of said bottle and has a high-affinity for biologically important metal ions.
4. A bottle and cap assembly according to claim 1 wherein said sequestering agent is immobilized on the surface of said bottle and has a high-selectivity for biologically important metal ions.
5. A bottle and cap assembly according to claim 1 wherein said sequestering agent has a high-selectively for certain metal ions but a low-affinity for at least one other ions.
6. A bottle and cap assembly according to claim 1 wherein said certain metal ions comprises Mn, Zn, Cu and Fe and said other at least one ion comprises calcium.
7. A bottle and cap assembly according to claim 1 wherein said metal-ion sequestering agent is immobilized on the surface of said bottle and has a stability constant greater than 1020 with iron (III).
8. A bottle and cap assembly according to claim 1 wherein said metal-ion sequestering agent is immobilized on the surface of said bottle and has a stability constant greater than 1030 with iron (III).
9. A bottle and cap assembly according to claim 1 wherein said inorganic nanoparticles have an average particle size of less than 100 nm.
10. A bottle and cap assembly according to claim 1 wherein said metal-ion sequestrant comprises an alpha amino carboxylate, a hydroxamate, or a catechol functional group.
11. A bottle and cap assembly according to claim 1 wherein said metal-ion sequestrant is attached to to inorganic nanoparticle by reacting the inorganic nanoparticle with a silicon alkoxide intermediate of the sequestrant having the general formula:
Si(OR)4\u2212xR\u2032x;

wherein x is an integer from from 1 to 3
R is an alkyl group; and
R\u2032 is an organo group containing an alpha amino carboxylate, a hydroxamate, or a catechol.
12. A bottle and cap assembly according to claim 1 wherein said bottle is made of a plastic material.
13. A bottle and cap assembly according to claim 1 wherein said liquid nutrient comprises a beverage.
14. A bottle and cap assembly according to claim 1 wherein said bottle is made of a material that includes said sequestering agent.
15. A bottle and cap assembly for containing a liquid nutrient having a pH equal to or freater than about 2.5 said cap having an interior surface having a polymeric layer thereon, said polymeric layer having a metal-ion sequestering agent for removing a designated metal ion from said liquid nutrient for inhibiting growth of microbes in said liquid nutrient, said metal-ion sequestering agent comprises derivatized nanoparticles comprising inorganic nanoparticles having an attached metal-ion sequestrant, wherein said inorganic nanoparticles have an average particle size of less than 200 nm and the derivatized nanoparticles have a stability constant greater than 1010 with iron (III), said metal-ion sequestering agent is immobilized in said polymeric layer and comprises 0.1 to 50.0% by weight of the polymeric layer, and the polymeric layer is capable of contacting the liquid contained therein and is permeable to water.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A lighting structure for a recessed lighting fixture, the lighting structure comprising:
a lighting fixture housing having an opening, the opening including a horizontal slot and a vertical slot, the vertical slot intersecting the horizontal slot; and
a retention structure attached to the housing, the retention structure to retain the lighting structure recessed into a ceiling, wherein the retention structure includes:
a wall segment positioned within the housing;
a tension spring segment positioned outside of the housing, the tension spring segment extending out from a first end portion of the wall segment; and
an end segment having a wide segment and a narrow segment, the narrow segment coupled to a second end portion of the wall segment, wherein the wide segment of the end segment is positioned outside of the housing by extending the wide segment of the end segment through the horizontal slot of the opening of the housing, and wherein the narrow segment of the end segment extends through the vertical slot of the opening of the housing.
2. The lighting structure of claim 1, wherein the wall segment is positioned against an inner wall of the housing.
3. The lighting structure of claim 1, wherein the wide segment of the substantially T-shaped segment is wider than the vertical slot of the opening of the housing.
4. The lighting structure of claim 1, wherein the tension spring segment curves down from the first end portion of the wall segment.
5. The lighting structure of claim 1, wherein a flange of the tension spring segment rests on the back side of the ceiling below the horizontal slot of the opening of the housing.
6. The lighting structure of claim 1, wherein the housing includes a second opening having a second horizontal slot and a second vertical slot and wherein the second vertical slot intersects the second horizontal slot.
7. The lighting structure of claim 1, wherein a torsion spring receiver extends out from the wall segment toward a center of the housing.
8. The lighting structure of claim 1, wherein the narrow segment of the end segment includes a first vertical segment, a horizontal segment, and a second vertical segment, wherein the first vertical segment extends from the second end portion of the wall segment, wherein the horizontal segment extends between the first vertical segment and the second vertical segment, and wherein the second vertical segment is coupled to the wide segment of the end segment.
9. The lighting structure of claim 1, wherein the horizontal slot of the opening of the housing is above the vertical slot of the opening of the housing when the lighting structure is recessed in a ceiling.
10. A lighting structure for a recessed lighting fixture, the lighting structure comprising:
a lighting fixture housing having an opening, the opening including a horizontal slot and a vertical slot, the vertical slot intersecting the horizontal slot; and
a retention structure to retain the lighting structure recessed into a ceiling, wherein the retention structure includes:
a wall segment to be positioned inside the housing;
a tension spring segment extending out from a first end portion of the wall segment, the tension spring segment to be positioned outside of the housing, wherein the tension spring segment is sized to pass through the horizontal slot of the opening of the housing from within the housing; and
an end segment having a wide segment and a narrow segment, the narrow segment coupled to a second end portion of the wall segment, wherein the wide segment of the end segment is to be positioned outside of the housing by passing the wide segment of the end segment through the horizontal slot of the opening of the housing from within the housing, and wherein the narrow segment of the end segment is sized to extend through the vertical slot of the opening of the housing.
11. The lighting structure of claim 10, wherein the wall segment is positioned against an inner wall of the housing.
12. The lighting structure of claim 10, wherein the wide segment of the substantially T-shaped segment is wider than the vertical slot of the opening of the housing.
13. The lighting structure of claim 10, wherein the tension spring segment curves down from the first end portion of the wall segment.
14. A lighting structure for a recessed lighting fixture, the lighting structure comprising:
a lighting fixture housing; and
a junction box attached to a lighting fixture housing, wherein a first portion of the junction box proximal to the housing is vertically narrower than a second portion of the junction box distal from the lighting fixture housing, wherein a proximal end of the junction box is attached to the lighting fixture housing, and wherein the junction box is tapered between a distal end of the junction box and the proximal end of the junction box.
15. The lighting structure of claim 14, wherein the junction box includes a first side wall and a second side wall, wherein a bottom edge of the first side wall is slanted angularly upwards as the first side wall extends towards the lighting fixture housing, and wherein a bottom edge of the second side wall is slanted angularly upwards as the second side wall extends towards the lighting fixture housing.
16. The lighting structure of claim 14, wherein the junction box includes a bottom wall and a back wall, wherein the bottom wall and the back wall extend between the first side wall and the second side wall, and wherein the back wall is at the distal end of the junction box.
17. The lighting structure of claim 16, wherein a cavity of the junction box is accessible via the back wall.
18. The lighting structure of claim 16, wherein a first portion of the bottom wall that is proximal to the lighting fixture housing is elevated relative to a second portion of the bottom wall that is distal from the lighting fixture housing.
19. The lighting structure of claim 14, wherein the proximal end of the junction box is attached to a housing top of the lighting fixture housing.
20. The lighting structure of claim 19, wherein the lighting fixture housing is cylindrical.

1. An integrated circuit on a single chip, comprising:
a module for digital IQ generation;
a module for LO synthesis;
a digital mixing module;
a multi-stage filtering and decimation module;
a passband equalization module;
an integrate & dump module; and
a DC offset adjustment module.
2. The integrated circuit of claim 1, wherein filtering operations have fully programmable coefficients that are double-buffered to provide near instantaneous selection between a pair of coefficient sets and to allow a second set of coefficients to be loaded while a first set of coefficients are in use.
3. The integrated circuit of claim 1, comprising a plurality of electrical interfaces to allow the chip to be used with single-ended or differential signals at a plurality of voltage levels.
4. The integrated circuit of claim 1, configured to process intermediate frequency (IF) sampled signals from a single AD converter and to process baseband IQ samples from a receiver that employs analog IQ generation via an radio-frequency (RF) quadrature mixer and pair of AD converters.
5. An integrated circuit on a single chip, comprising:
input MUX means for providing front-end interface to the input signals and clock signals;
control Interface means for providing electrical interfaces to allow an external controller to reset the chip, load coefficients, configure the chip by enabling or disabling bypass setting on a plurality of functions, switch between at least two processing modes, switch between at least two AD inputs, and test the chip;
clock distribution means for accepting a selected input and distributing copies of the selected input throughout the chip, generating a utility clock signal (UTILCLK) output from the chip to be used by other external devices to synchronize to output data of the chip;
output MUX means for providing an electric interface to external circuits that receive signals from the chip, and selectively providing either single-ended or differential signals for all outputs; and
tuner filter means for accepting demuxed data from the input MUX means and performing digital tuning and filtering.
6. The integrated circuit of claim 5, wherein the tunable filter means provides at least one function from the group comprising Digital IQ (DIQ) Generation, DIQBaseband MUX, Coarse Time Delay, Fixed Decimation, Digital Tuning via Numerically Controlled Oscillator (NCO), Digital Mixer, Two-Stage FIR Filtering, IQ Balance, IQ Swap, and Complex Channel Equalization.
7. The integrated circuit of claim 5, wherein said output MUX means ouptuts IQ signals (Data-I, Data-Q), Data Valid (DVALID) and Last IPP (DV-LIPP) (delayed to match the IQ data delay), Saturation Bit (SAT-OUT) (delayed to align with the IQ data), Overflow Detection Bit (OVFLOW), Data Clock (DATACLK) at the same rate and synchronized with the output data, and Utility Clock UTILCLK).
8. A reconfigurable filter and decimate circuit, comprising:
a signal input;
an adder coupled having a plurality of signal inputs and a signal output;
means for demultiplexing a signal received into a plurality of sampled signals;
a plurality of FIR filters each having a number of taps; and
switching means for coupling said plurality of sampled signals with said plurality of FIR filters and with said plurality of signal inputs to said adder, and for decimating said input signal a number of times, and for each number of times, the output of said adder is filtered by the same number of taps.
9. The filter and decimate circuit as recited in claim 8, wherein said means for demultiplexing said signal separates said input signal into four signals comprising first and second odd sampled signals and first and second even sampled signals.
10. The filter and decimate circuit as recited in claim 8, wherein the number of taps in said FIR filters combines to be 36 taps, and each of said FIR filters comprise 3, 6 or 9 taps.
11. The filter and decimate circuit as recited in claim 9, wherein the number of taps in said FIR filters combines to be 36 taps, and each of said FIR filters comprise 3, 6 or 9 taps.
12. The integrated circuit as recited in claim 1, wherein said multi-stage filtering and decimation module includes a reconfigurable filter and decimate circuit, comprising:
a signal input;
an adder coupled having a plurality of signal inputs and a signal output;
means for demultiplexing a signal received into a plurality of sampled signals;
a plurality of FIR filters each having a number of taps; and
switching means for coupling said plurality of sampled signals with said plurality of FIR filters and with said plurality of signal inputs to said adder, and for decimating said input signal a number of times, and for each number of times, the output of said adder is filtered by the same number of taps.
13. The integrated circuit as recited in claim 5, wherein said tuner filter means includes a reconfigurable filter and decimate circuit, comprising:
a signal input;
an adder coupled having a plurality of signal inputs and a signal output;
means for demultiplexing a signal received into a plurality of sampled signals;
a plurality of FIR filters each having a number of taps; and
switching means for coupling said plurality of sampled signals with said plurality of FIR filters and with said plurality of signal inputs to said adder, and for decimating said input signal a number of times, and for each number of times, the output of said adder is filtered by the same number of taps.
14. A fast FIR filter comprising:
a demultiplexer configured to receive an input signal and to separate the signal into a plurality of signals;
filter means for filtering the plurality of signals and outputting a plurality of filtered signals; and
a multiplexer for combing the plurality of filtered signals into a single output signal;
wherein said filter means processes each said plurality of signals at a rate a plurality of times slower than the input rate of said input signal without decimation of said input signal and without loss of bandwidth of said input signal.
15. The fast FIR filter as recited in claim 14, wherein said input signal has a data rate of 4R, said demultiplexer splits said input signal into four signals, said filter means processes each of said four signals at a data rate of R, and said single output signal has a data rate of 4R.
16. The integrated circuit as recited in claim 1, wherein said multi-stage filtering and decimation module includes a fast FIR filter comprising:
a demultiplexer configured to receive an input signal and to separate the signal into a plurality of signals;
filter means for filtering the plurality of signals and outputting a plurality of filtered signals; and
a multiplexer for combing the plurality of filtered signals into a single output signal;
wherein said filter means processes each said plurality of signals at a rate a plurality of times slower than the input rate of said input signal without decimation of said input signal and without loss of bandwidth of said input signal.
17. The fast FIR filter as recited in claim 14, further comprising splitting circuitry for splitting said plurality of signals into a plurality of groups of signals; said filter means includes, for each of groups of signals being filtered, a group of filters.
18. The fast FIR filter as recited in claim 17, wherein said demultiplexer splits said input signal into first, second, third and fourth input signals; and
wherein said plurality of groups of signals includes first, second, third and fourth groups, and each of said groups includes first, second, third and fourth signals corresponding respectively to said first, second, third and fourth input signals; and
wherein for each group of signals, said first, second, third and fourth signals are filtered by one of first, second, third and fourth FIR filters, the output of the filters is combined into a single filtered signal for each group and input into said multiplexer.
19. The fast FIR filter of claim 18, wherein for said first group, said first signal is filtered by said first filter, said second signal is filtered by said second filter, said third signal is filtered by said third filter, and said fourth signal is filtered by said fourth filter; and
wherein for said second group, said first signal is filtered by said fourth filter, said second signal is filtered by said first filter, said third signal is filtered by said second filter, and said fourth signal is filtered by said third filter; and
wherein for said third group, said first signal is filtered by said third filter, said second signal is filtered by said fourth filter, said third signal is filtered by said first filter, and said fourth signal is filtered by said second filter; and
wherein for said fourth group, said first signal is filtered by said second filter, said second signal is filtered by said third filter, said third signal is filtered by said second filter, and said fourth signal is filtered by said first filter.
20. The fast FIR filter of claim 19, further comprising delay means for delaying some of said filtered signals in order to generate a homogenous filtered output signal.
21. A digital IQ signal generation circuit, comprising:
demultiplexing means for separating a real input signal into first, second, third and fourth signals;
inverter means for inverting said third and fourth signals;
low pass FIR filter means for filtering said first, second, third and fourth signals; and
multiplexing means for combining the filtered first and third signals and for combining said second and fourth signals, in order to generate I and Q sampled signals at one half an input data rate of said real input signal; wherein
said low pass FIR filter means processes signals at one quarter the input data rate of said real input signal.
22. The integrated circuit as recited in claim 1, wherein said module for digital IQ generation includes a fast FIR filter comprising:
a demultiplexer configured to receive an input signal and to separate the signal into a plurality of signals;
filter means for filtering the plurality of signals and outputting a plurality of filtered signals; and
a multiplexer for combing the plurality of filtered signals into a single output signal;
wherein said filter means processes each said plurality of signals at a rate a plurality of times slower than the input rate of said input signal without decimation of said input signal and without loss of bandwidth of said input signal.
23. The integrated circuit of claim 1, wherein each function includes a bypass mode that effectively disables the function to conserve power in applications where one or more functions are not required.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

We claim:

1. A method for manufacturing a trench capacitor, the method which comprises:
(a) providing a substrate;
(b) forming a trench with a lower region and an upper region in the substrate;
(c) filling the lower region of the trench with a first filler material;
(d) forming an insulation collar in the upper region of the trench;
(e) removing the first filler material from the lower region of the trench;
(f) forming a buried plate as a first capacitor plate in the substrate such that the buried plate is disposed adjacent to the lower region of the trench and using a low-pressure gas phase doping for forming the buried plate;
(g) forming a dielectric layer as a capacitor dielectric lining the lower region of the trench and an inner side of the insulation collar; and
(h) filling the trench with a conductive second filler material as a second capacitor plate.
2. The method according to claim 1, which comprises forming the buried plate in step (f) by using a pressure between 66 Pascal and 200 Pascal for the low-pressure gas phase doping.
3. The method according to claim 1, which comprises forming the buried plate in step (f) at a temperature between 750 C. and 1050 C.
4. The method according to claim 1 which comprises forming the buried plate in step (f) by using a doping gas selected from the group consisting of AsH3 and PH3 and by using a carrier gas selected from the group consisting of H2 and He.
5. The method according to claim 1, which comprises forming the dielectric layer in step (g) and forming the buried plate in step (f) at substantially identical pressures and substantially identical temperatures.
6. The method according to claim 1, which comprises forming the dielectric layer in step (g) and forming the buried plate in step (f) at a pressure between 66 Pascal and 200 Pascal and a temperature between 750 C. and 1050 C.
7. The method according to claim 1, which comprises forming the dielectric layer by using a prenitridization step and a main nitridization step.
8. The method according to claim 7, which comprises carrying out the prenitridization step at a temperature of substantially 950 C. and a pressure of substantially 800 Pascal and by using NH3 for the prenitridization step.
9. The method according to claim 7, which comprises carrying out the main nitridization step at a temperature of substantially between 700 C. and 800 C. and a pressure between 26.6 Pascal and 46.7 Pascal and by using NH3 together with a compound selected from the group consisting of SiCl2H2 and SiH4 for the main nitridization step.
10. The method according to claim 1, which comprises forming the buried plate self-aligned with respect to the insulating collar.
11. The method according to claim 1, which comprises forming, from a third, conductive filler material, a bridge above the insulating collar on the conductive, second filler material for forming a buried contact to the substrate.
12. The method according to claim 1, which comprises forming an etch stop layer on walls of the trench such that the etch stop layer is disposed under the first filler material.
13. The method according to claim 1, which comprises widening the lower region of the trench with respect to the upper region of the trench for forming a bottle shaped trench.
14. A method for manufacturing a trench capacitor, the method which comprises:
(a) providing a substrate;
(b) forming a trench with a lower region and an upper region in the substrate;
(c) filling the lower region of the trench with a first filler material;
(d) forming an insulation collar in the upper region of the trench;
(e) removing the first filler material from the lower region of the trench;
(f) forming a buried plate as a first capacitor plate in the substrate such that the buried plate is disposed adjacent to the lower region of the trench and using a gas phase doping at a pressure below 200 Pascal for forming the buried plate;
(g) forming a dielectric layer as a capacitor dielectric lining the lower region of the trench and an inner side of the insulation collar; and
(h) filling the trench with a conductive second filler material as a second capacitor plate.