Author: claimsbot

What is claimed is:

1. A method for fabricating dynamic random access memory (DRAM) cells on and in an epitaxial silicon layer formed over a first insulating layer on a semiconductor substrate comprising the steps of:
forming said first insulating layer on said substrate;
depositing a hard-mask layer on said first insulating layer;
patterning said hard-mask layer and leaving portions over device areas, and using said hard mask for etching shallow trenches in said substrate;
depositing a second insulating layer to fill said shallow trenches and polishing back to said hard-mask layer to form shallow trench isolation;
selectively removing said hard-mask layer and forming recesses over and self-aligned to said device areas and exposing said first insulating layer in said recesses;
etching openings in said first insulating layer over said device areas to said substrate;
growing, selectively said epitaxial layer from said openings and extending laterally over said first insulating layer in said recesses;
forming a gate oxide on said epitaxial layer;
forming a doped polysilicon layer on said substrate;
patterning said polysilicon layer to form FET gate electrodes over said openings, and implanting to form lightly doped sourcedrain areas in said epitaxial layer adjacent to said gate electrodes;
forming insulating sidewall spacers on said gate electrodes, and implanting to form first and second sourcedrain contact areas adjacent to said sidewall spacers;
forming capacitors electrically contacting said first sourcedrain contact areas and bit lines electrically contacting said second sourcedrain contact areas to complete said DRAM cells.
2. The method of claim 1, wherein said semiconductor substrate is a P doped single-crystal silicon substrate.
3. The method of claim 1, wherein said first insulating layer is silicon oxide formed by thermal oxidation to a thickness of between about 100 and 200 Angstroms.
4. The method of claim 1, wherein said hard-mask layer is silicon nitride deposited by low-pressure chemical vapor deposition to a thickness of between about 1600 and 2000 Angstroms.
5. The method of claim 1, wherein said shallow trenches are etched to a depth of between about 2000 and 3300 Angstroms.
6. The method of claim 1, wherein said second insulating layer is silicon oxide deposited by low-pressure chemical vapor deposition and is polished back to form a field oxide which is coplanar with top surface of said hard mask.
7. The method of claim 1, wherein said epitaxial layer is farmed in a reactor using a reactant gas selected from the group that includes SiH4 and SiH2Cl2 at a temperature of between about 950 and 1100 C., and said epitaxial layer is formed to a thickness of between about 1000 and 5000 Angstroms.
8. The method of claim 1, wherein said gate oxide is formed by a dry thermal oxidation and is grown to a thickness of between about 15 and 35 Angstroms.
9. The method of claim 1, wherein said doped polysilicon layer is deposited by low-pressure chemical vapor deposition using a reactant gas of SiH4 and is doped N by ion implantation to a final concentration of between about 1.0 E 19 and 4.0 E 21 atomscm3.
10. The method of claim 1, wherein said sidewall spacers are silicon oxidesilicon nitride.
11. A method for fabricating dynamic random access memory (DRAM) cells on and in an epitaxial silicon layer formed over a first insulating layer on a semiconductor substrate comprising the steps of:
forming said first insulating layer on said substrate;
depositing a hard-mask layer on said first insulating layer;
patterning said hard-mask layer and leaving portions over device areas, and using said hard mask for etching shallow trenches in said substrate;
depositing a second insulating layer to fill said shallow trenches and polishing back to said hard-mask layer to form shallow trench isolation;
selectively removing said hard-mask layer and forming recesses over and self-aligned to said device areas and exposing said first insulating layer in said recesses;
etching openings in said first insulating layer over said device areas to said substrate;
growing selectively said epitaxial layer from said openings and extending laterally over said first insulating layer in said recesses;
forming capacitor bottom electrodes in a portion of said epitaxial layer by doping;
forming a gate oxide on said epitaxial layer;
forming a doped polysilicon layer on said substrate;
patterning said polysilicon layer to form FET gate electrodes over said openings and to form capacitor top electrodes for said capacitors over said capacitor bottom electrodes and patterning said polysilicon layer to form resistors over said shallow trench isolation;
implanting to form lightly doped sourcedrain areas in said epitaxial layer adjacent to said gate electrodes;
forming insulating sidewall spacers on said gate electrodes, and implanting to form first and second sourcedrain contact areas adjacent to said sidewall spacers, wherein said first sourcedrain contact areas are contiguous with said capacitor bottom electrodes;
forming bit lines electrically contacting said second sourcedrain contact areas to complete said DRAM cells.
12. The method of claim 11, wherein said semiconductor substrate is a P doped single-crystal silicon substrate.
13. The method of claim 11, wherein said first insulating layer is silicon oxide formed by thermal oxidation to a thickness of between about 100 and 200 Angstroms.
14. The method of claim 11, wherein said hard-mask layer is silicon nitride deposited by low-pressure chemical vapor deposition to a thickness of between about 1600 and 2000 Angstroms.
15. The method of claim 11, wherein said shallow trenches are etched to a depth of between about 2000 and 3300 Angstroms.
16. The method of claim 11, wherein said second insulating layer is silicon oxide deposited by low-pressure chemical vapor deposition and is polished back to form a field oxide which is coplanar with top surface of said hard mask.
17. The method of claim 11, wherein said epitaxial layer is formed in a reactor using a reactant gas selected from the group that includes SiH4 and SiH2Cl2 at a temperature of between about 950 and 1100 C., and said epitaxial layer is formed to a thickness of between about 1000 and 5000 Angstroms.
18. The method of claim 11, wherein said capacitor bottom electrodes are formed by doping using an ion implantation of phosphorus ions to achieve a final dopant concentration of between about 1.0 E 19 and 4.0 E 21 atomscm3.
19. The method of claim 11, wherein said gate oxide is formed by a dry thermal oxidation and is grown to a thickness of between about 15 and 35 Angstroms.
20. The method of claim 11, wherein said doped polysilicon layer is deposited by low-pressure chemical vapor deposition using a reactant gas of SiH4 and is doped N by ion implantation to a final concentration of between about 1.0 E 19 and 4.0 E 21 atomscm3.
21. The method of claim 11, wherein said sidewall spacers are silicon oxidesilicon nitride.
22. A method for fabricating dynamic random access memory (DRAM) cells on and in an epitaxial silicon layer formed over a first insulating layer on a semiconductor substrate comprising the steps of:
forming said first insulating layer on said substrate;
depositing a hard-mask layer on said first insulating layer;
patterning said hard-mask layer and leaving portions over device areas, and using said hard mask for etching shallow trenches in said substrate;
depositing a second insulating layer to fill said shallow trenches and polishing back to said hard-mask layer to form shallow trench isolation;
selectively removing said hard-mask layer and forming recesses over and self-aligned to said device areas and exposing said first insulating layer in said recesses;
etching openings in said first insulating layer over said device areas to said substrate;
growing selectively said epitaxial layer from said openings and extending laterally over said first insulating layer in said recesses;
forming a gate oxide on said epitaxial layer;
forming a doped polysilicon layer on said substrate;
patterning said polysilicon layer to form FET gate electrodes over said openings, and implanting to form lightly doped sourcedrain areas in said epitaxial layer adjacent to said gate electrodes;
forming insulating sidewall spacers on said gate electrodes, and implanting to form first and second sourcedrain contact areas adjacent to said sidewall spacers;
depositing a first interpolysilicon oxide (IPO1) layer and etching first contact openings to said first sourcedrain contact areas and forming stacked capacitors having node contacts in said first contact openings;
depositing a second interpolysilicon oxide (IPO2) layer and etching second contact openings to said second sourcedrain contact areas and forming bit line contact plugs in said second contact openings and forming bit lines to complete said DRAM cells.
23. The method of claim 22, wherein said semiconductor substrate is a P doped single-crystal silicon substrate.
24. The method of claim 22, wherein said first insulating layer is silicon oxide formed by thermal oxidation to a thickness of between about 100 and 200 Angstroms.
25. The method of claim 22, wherein said hard-mask layer is silicon nitride deposited by low-pressure chemical vapor deposition to a thickness of between about 1600 and 200 Angstroms.
26. The method of claim 22, wherein said shallow trenches are etched to a depth of between about 2000 and 3300 Angstroms.
27. The method of claim 22, wherein said second insulating layer is silicon oxide deposited by low-pressure chemical vapor deposition and is polished back to form a field oxide which is coplanar with top surface of said hard mask.
28. The method of claim 22, wherein said epitaxial layer is formed in a reactor using a reactant gas selected from the group that includes SiH4 and SiH2Cl2 at a temperature of between about 950 and 1100 C., and said epitaxial layer is formed to a thickness of between about 1000 and 5000 Angstroms.
29. The method of claim 22, wherein said gate oxide is formed by a dry thermal oxidation and is grown to a thickness of between about 15 and 35 Angstroms.
30. The method of claim 22, wherein said doped polysilicon layer is deposited by low-pressure chemical vapor deposition using a reactant gas of SiH4 and is doped N by ion implantation to a final concentration of between about 1.0 E 19 and 4.0 E 21 atomscm3.
31. The method of claim 22, wherein said sidewall spacers are silicon oxidesilicon nitride.
32. The method of claim 22, wherein said first interpolysilicon oxide layer is silicon oxide deposited by chemical vapor deposition and planarized to a thickness sufficient to insulate said gate electrodes.
33. The method of claim 22, wherein said node contacts are formed from an N doped polysilicon.
34. The method of claim 22, wherein said second interpolysilicon oxide layer is silicon oxide deposited by chemical vapor deposition and planarized to a thickness sufficient to insulate said capacitors.
35. The method of claim 22, wherein said bit lines are formed from an electrically conducting layer.
36. Dynamic random access memory (DRAM) cells on and in an epitaxial silicon layer over an insulating layer on a semiconductor substrate comprised of:
a shallow trench isolation around device areas having recesses over and aligned to said device areas;
said insulating layer on said substrate in said recesses, each of said recesses having an opening in said insulating layer to said substrate;
an epitaxial layer in each of said recesses extending from said opening and laterally over said insulating layer;
a gate oxide on said epitaxial layer in each of said recesses;
FET gate electrodes on said gate oxide and over said openings in said insulating layer, and including lightly doped sourcedrain areas and sourcedrain contact areas in said epitaxial layer adjacent to said gate electrodes;
capacitor node contacts to said sourcedrain contact areas in said epitaxial layer over said insulating layer;
bit line contacts in said epitaxial layer over said insulating layer;
capacitors over and contacting said capacitor node contacts, and bit lines over and contacting said bit line contacts.
37. The structure of claim 36, wherein said semiconductor substrate is a P doped single-crystal silicon substrate.
38. The structure of claim 36, wherein said insulating layer is silicon oxide having a thickness of between about 100 and 200 Angstroms.
39. The structure of claim 36, wherein said epitaxial layer is single-crystal silicon and has a thickness of between about 1000 and 5000 Angstroms.
40. The structure of claim 36, wherein said gate oxide is a silicon oxide having a thickness of between about 15 and 35 Angstroms.
41. The structure of claim 36, wherein said gate electrodes are conductively doped polysilicon.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

We claim:

1. A method for the mass production of substantially identical microstructures, said method comprising the steps of:
(a) fabricating a first micromold insert having a size and shape that are generally complementary to the size and shape of the desired microstructures;
(b) fabricating at least one inverse replication of the first micromold insert by depositing a polymeric precursor onto the first micromold insert, and curing the polymeric precursor into a polymeric inverse replication, wherein the accuracy of the polymeric inverse replication is at least about 10 microns;
(c) coating the inverse replication with an electrically conductive layer;
(d) electroplating a metallic form complementary to the inverse replication, using the electrically conductive layer as a cathode;
(e) etching away the electrically conductive layer from the form to produce a second, metallic micromold insert, whose dimensions differ from the dimensions of the first micromold by an amount corresponding to the thickness of the electrically conductive layer.
(f) repeating steps (c) through (e) a plurality of times to produce a plurality of second micromold inserts; and
(g) molding a plurality of substantially identical, polymeric microstructures from the second micromold inserts.
2. A method as recited in claim 1, wherein the first micromold insert is fabricated using a LIGA process.
3. A method as recited in Claim 1, wherein the inverse replication comprises polydimethylsiloxane.
4. A method as recited in claim 3, wherein the polymeric precursor comprises about a 10:1 ratio of dimethylsiloxane and a curing agent.
5. A method as recited in claim 1, wherein the electrically conducting layer is deposited by electron beam evaporation.
6. A method as recited in Claim 1, wherein the electrically conducting layer is deposited by sputtering.
7. A method as recited in claim 1, wherein the electrically conducting layer comprises copper.
8. A method as recited in claim 1, wherein the electrically conducting layer comprises chromium.
9. A method as recited in claim 1, wherein the electrically conducting layer comprises gold.
10. A method as recited in claim 1, wherein the accuracy of the polymeric inverse replication is 100 nanometers.

1. A method comprising:
sending a computer program for compressing and sending media files to a client computer, the computer program comprising program code for:
identifying information about a media file in response to receiving a request to send a media file;
determining whether the media file is compressible based on the identified information;
identifying a compression algorithm based on the identified information;
compressing the media file using the compression algorithm; and
sending the compressed media file to one or more server computers; and

receiving the compressed media file sent from the client computer.
2. The method of claim 1, wherein the program code for identifying the information about the media file comprises program code for identifying a location of the media file on the client computer, a file format of the media file, and selected configuration options of how to compress the media file.
3. The method of claim 2, wherein the program code for determining whether the media file is compressible comprises program code for determining whether the file format is supported by the computer program.
4. The method of claim 1, wherein the program code for identifying the compression algorithm based on the identified information comprises program code for identifying the compression algorithm based on at least one of a file format of the media file, a size of the media file, and a type of content included in the media file.
5. The method of claim 1, wherein the program code for sending the compressed media file comprises program code for:
separating, while the media file is being compressed, portions of the media file that have been compressed into a plurality of compressed segments of the media file; and
sending, while the media file is being compressed, one or more of the compressed segments of the media file to the one or more server computers.
6. The method of claim 5, wherein receiving the compressed media file comprises receiving the plurality of compressed segments of the media file, the method further comprising combining the plurality of compressed segments to form the media file.
7. The method of claim 1, wherein the computer program is sent to the client computer from a first server computer and the compressed media file is received by a second server computer.
8. A system comprising:
one or more server computers configured to send a computer program for compressing and sending media files to a client computer, the computer program comprising program code for:
identifying information about a media file in response to receiving a request to send a media file;
determining whether the media file is compressible based on the identified information;
identifying a compression algorithm based on the identified information;
compressing the media file using the compression algorithm; and
sending the compressed media file to one or more server computers.
9. The system of claim 8, wherein the program code for identifying the information about the media file comprises program code for identifying a location of the media file on the client computer, a file format of the media file, and selected configuration options of how to compress the media file.
10. The system of claim 9, wherein the program code for determining whether the media file is compressible comprises program code for determining whether the file format is supported by the computer program.
11. The system of claim 8, wherein the program code for identifying the compression algorithm based on the identified information comprises program code for identifying the compression algorithm based on at least one of a file format of the media file, a size of the media file, and a type of content included in the media file.
12. The system of claim 8, wherein the program code for sending the compressed media file comprises program code for:
separating, while the media file is being compressed, portions of the media file that have been compressed into a plurality of compressed segments of the media file; and
sending, while the media file is being compressed, one or more of the compressed segments of the media file to the one or more server computers.
13. The system of claim 12, wherein the one or more server computers are configured to receive the plurality of compressed segments of the media file and combine the plurality of compressed segments to form the media file.
14. A non-transitory computer-readable medium embodying a computer program, the computer program comprising computer-readable program code for:
identifying information about a media file in response to receiving a request to send a media file;
determining whether the media file is compressible based on the identified information;
identifying a compression algorithm based on the identified information;
compressing the media file using the compression algorithm; and
sending the compressed media file to one or more server computers.
15. The computer-readable medium of claim 14, wherein the program code for identifying the information about the media file comprises program code for identifying a location of the media file on the client computer, a file format of the media file, and selected configuration options of how to compress the media file.
16. The computer-readable medium of claim 15, wherein the program code for determining whether the media file is compressible comprises program code for determining whether the file format is supported by the computer program.
17. The computer-readable medium of claim 14, wherein the program code for identifying the compression algorithm based on the identified information comprises program code for identifying the compression algorithm based on at least one of a file format of the media file, a size of the media file, and a type of content included in the media file.
18. The computer-readable medium of claim 14, wherein the program code for sending the compressed media file comprises program code for:
separating, while the media file is being compressed, portions of the media file that have been compressed into a plurality of compressed segments of the media file; and
sending, while the media file is being compressed, one or more of the compressed segments of the media file to the one or more server computers.
19. The computer-readable medium of claim 18, wherein the computer program further comprises program code for:
receiving the plurality of compressed segments of the media file sent from a client computer; and
combining the plurality of compressed segments to form the media file.
20. The computer-readable medium of claim 14, wherein the computer program further comprises program code for:
sending a computer program for compressing and sending media files to a client computer; and
receiving the compressed media file sent from the client computer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A process of regeneration of spent catalysts from hydrocarbon conversion, the catalyst comprising at least one precious metal selected from the group consisting of elements of group VIII, silver, and gold, at least one halogen and at least one porous support, process comprising at least the two following steps:
at least one step for combustion of coke present on said catalyst in the presence of a gas comprising molecular oxygen, at a temperature between 300 and 680\xb0 C., for a duration between 0.5 and 10 hours,
at least one oxyhalogenation step, in the presence of a halogenated compound under controlled atmosphere of humid air, at a temperature between 300 and 650\xb0 C., these two steps being performed in the same, single regeneration zone in which the catalyst to be regenerated is found in the form of a fluidized bed, not circulating or moving.
2. A process according to claim 1, wherein the steps of combustion and oxyhalogenation are performed separately and successively.
3. A process according to claim 1, wherein the oxyhalogenation step is partially mixed with the end of the combustion step.
4. A process according to claim 1, wherein the step of combustion and oxyhalogenation are performed simultaneously.
5. A process according to claim 1, wherein the spent catalyst is subjected to a stripping step before the coke combustion step.
6. A process according to one of the preceding claims claim 1, wherein the spent catalyst is subjected to progressive combustion by heating to 250-450\xb0 C.
7. A process according to claim 1, wherein the catalyst obtained at the end of the oxyhalogenation step is subjected to at least one of the following steps:
calcination
reduction
sulfurization.
8. A process according to claim 1, applied to the regeneration of a reforming catalyst and comprising the following steps:
(1) optional stripping under air, under nitrogen, or a mixture of these two gases,
(2) progressive combustion,
(3) oxychlorination, optionally followed by calcination,
(4) reduction under hydrogen,
(5) optional sulfurization.
9. A process according to claim 8, wherein all the steps are performed in the same reactor.
10. A process according to claim 1, wherein the spent catalyst is subjected to an optional stripping, a combustion step, an oxychlorination step, a reduction step, optionally a sulfurization step, and wherein one proceeds to a shampooing of said catalyst.