1. An apparatus for use with plastics material pre-forms and with respect to a dwell period, the apparatus comprising:
a tempering space for receiving a plurality of plastics material pre-forms,
a supply device in order to supply the plastics material pre-forms to the tempering space,
a removal device in order to remove the plastics material pre-forms out of the tempering space, and
a conveying device which conveys the plastics material pre-forms from the supply device to the removal device in such a way that each plastics material pre-form remains in the tempering space for a pre-set duration of the dwell period, wherein a temperature of the plastics material pre-forms leaving the removal device is substantially constant irrespective of a duration of the dwell period of the plastics material pre-forms in the tempering space and the conveying device is designed in such a way that each plastics material pre-form remains in the tempering space for a period of time of at least 5 minutes.
2. The apparatus according to claim 1, wherein the conveying device conveys the plastics material pre-forms non-sorted at least locally through the tempering space.
3. The apparatus according to claim 1, wherein the temperature of the plastics material pre-forms leaving the removal device is independent of a temperature of the plastics material pre-forms supplied to the tempering space by way of the supply device.
4. The apparatus according to claim 1, wherein the apparatus has a flow generation device which in the tempering space generates an air flow with which it is possible to act upon the plastics material pre-forms.
5. The apparatus according to claim 1, wherein the apparatus has a sensor device for determining a temperature inside the tempering space.
6. The apparatus according to claim 1, wherein the conveying device has conveying regions extending adjacent to one another.
7. The apparatus according to claim 1, wherein the conveying device has a conveyor belt on which the plastics material pre-forms are conveyed through the tempering space.
8. The apparatus according to claim 1 further comprising a shaper, arranged downstream of the tempering device in a conveying direction of the plastics material pre-forms, for shaping the plastics material pre-forms to form plastics material containers, wherein a first heating device for heating the plastics material pre-forms is arranged between the apparatus for shaping the plastics material pre-forms and the tempering device.
9. The apparatus according to claim 8, further comprising a connecting line which conveys heated air from the heating device andor the apparatus for shaping the plastics material pre-forms to form plastics material containers to the apparatus.
10. The apparatus according to claim 8, further comprising a production device for producing the plastics material pre-forms.
11. A method of producing plastics material containers, wherein plastics material pre-forms are heated and are then shaped in a shaping device to form plastics material containers, wherein the plastics material pre-forms are conditioned thermally in an apparatus for the conditioning before the heating, and to this end the plastics material pre-forms are conveyed through a tempering space to this apparatus for the conditioning, wherein the plastics material pre-forms are present in the tempering space for a period of at least 5 minutes.
12. The method according to claim 11, wherein the tempering space has air flow through it.
13. The method according to claim 11, wherein the apparatus is acted upon with waste air from a heating device andor from the shaping device.
14. The method according to claim 11, wherein the plastics material pre-forms are conveyed non-sorted at least locally through the tempering space.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory device comprising:
a memory array comprising a plurality of non-volatile memory cells organized as a plurality of memory segments;
a plurality of data caches, coupled to the memory array; and
control circuitry coupled to the memory array and configured to control an access to the memory array, the control circuitry configured to control coupling of the plurality of data caches to a selected one of the plurality of memory segments wherein the control circuitry is further configured to switch each of the data lines of the selected memory segment to a respective one of the data caches.
2. The memory device of claim 1 wherein the memory array comprises a NAND architecture of flash memory cells.
3. The memory device of claim 1 wherein the plurality of data caches are coupled to the memory array through switching circuitry that is controlled by the control circuitry.
4. A memory system comprising:
a controller configured to control operation of the memory system; and
a non-volatile memory device, coupled to the controller, that operates in response to the controller, the non-volatile memory device comprising:
a memory array comprising a plurality of memory segments wherein each memory segment is comprised of a plurality of data lines;
a plurality of data caches for storing data from the controller to be stored in the memory array and for storing data from the memory array to be transferred to the controller;
a plurality of switches coupling the plurality of data caches to the memory array; and
control circuitry coupled to the memory array and configured to control accessing the memory array wherein the control circuitry is configured to control the switches wherein a selected memory segment is coupled to the plurality of data caches such that all the data lines of the selected memory segment are accessed substantially simultaneously and at least one data line of an unselected memory segment is switched to a source line.
5. The memory system of claim 4 wherein each data cache is configured to adjust bias voltages for a respective one of the data lines responsive to a distance of the data cache from its selected memory segment.
6. The memory system of claim 4 wherein the control circuitry is further configured to control reading of the data lines of the selected memory segment substantially simultaneously.
7. A memory device comprising:
a plurality of memory cells;
a data line connected to the memory cells; and
a read control circuit for reading out data stored in a selected memory cell of the memory cells through the data line by biasing the data line and by sensing the data line that has the stored data,
wherein the read control circuit changes at least one of the bias condition or the sensing condition depending on a location where the selected memory cell has been added.
8. A memory device comprising:
a plurality of memory cells;
a data line connected to the memory cells, the data line being divided into plurality of segments;
a read circuit coupled with the data line for reading out data stored in a selected memory cell of the memory cells through the data line by biasing the data line and by sensing the data line that reflects the stored data; and
a read control circuit for reconfiguring the data line by isolating parts of segments from the read circuit, the parts not contributing to transfer of data from the selected memory cell to the read circuit, and for changing at least one of the bias condition or the sensing condition depending on a location where the selected memory cell has been added.
9. A memory device comprising:
a memory cell array comprising:
a first group of memory cells;
a first data line connected to the first group, the first data line being divided into plural segments;
a second group of memory cells;
a second data line connected to the second group, the second data line being divided into plural segments; and
a plurality of word lines each connected to a pair of memory cells, one from the first group and another from the second group;
a first read circuit, connected to the first data line and located at one side of the array, for biasing the first data line and for sensing the first data line;
a second read circuit, connected to the second data line and located at an opposite side of the array, for biasing the second data line and for sensing the second data line; and
a read control circuit for selecting a pair of memory cells by selecting a word line, for reconfiguring the first and second data lines by isolating parts of segments from respective read circuits, the parts not contributing to transfer of data from the selected pair of memory cells to respective read circuits, for changing at least one of the bias condition and the sensing condition of the first read circuit depending on a location where the selected memory cells have been put in, and for changing at least one of the bias condition or the sensing condition of the second read circuit depending on a location where the selected memory cells have been added.
10. A memory device comprising:
a memory cell array comprising:
a first group of memory cells;
a first data line connected to the first group, the first data line being divided into plural segments;
a second group of memory cells;
a second data line connected to the second group, the second data line being divided into plural segments;
a plurality of word lines each connected to a pair of memory cells, one from the first group and another from the second group; and
a source line coupled with the first and second groups of the memory cells;
a first read circuit, connected to the first data line and located at one side of the array, for biasing the first data line and for sensing the first data line;
a second read circuit, connected to the second data line and located at an opposite side of the array, for biasing the second data line and for sensing the second data line; and
a read control circuit for selecting a pair of memory cells by selecting a word line, for reconfiguring the first and second data lines by isolating parts of segments from respective read circuits, the parts not contributing to transfer of data from the selected pair of memory cells to respective read circuits, for changing at least one of the bias condition and the sensing condition of the first read circuit depending on a location where the selected memory cells have been put in, for changing at least one of the bias condition or the sensing condition of the second read circuit depending on a location where the selected memory cells have been added, and for connecting the parts of segments to the source line.
11. The memory device of claim 10 wherein the first and second read circuits comprise data caches.
12. The memory device of claim 11 wherein each data cache comprises a bit line voltage control circuit and a data latch circuit.
13. The memory device of claim 12 wherein the data latch circuit is configured to input and output data on an IO path coupled to the data cache.
14. The memory device of claim 13 wherein the IO path comprises a serial IO bus.
15. The memory device of claim 12 wherein the bit line voltage control circuit comprises a precharge transistor coupled to a bit line voltage clamp transistor.
16. The memory device of claim 15 wherein the bit line voltage clamp transistor is a first bit line voltage clamp transistor that is coupled in series with a second bit line voltage clamp transistor wherein the first and second bit line voltage clamp transistors are configured to transfer data stored in the data latch circuit to a respective bit line.
17. The memory device of claim 13 wherein the data latch circuit is coupled to the IO path through enabling transistors.
18. The memory device of claim 15 wherein the bit line voltage control circuit is configured to control bit line precharge voltage levels and bit line sense levels during a read operation.
19. The memory device of claim 15 wherein the bit line voltage clamp transistor, in response to a bit line clamp voltage applied to the bit line voltage clamp transistor, is configured to generate various bit line precharge levels.
20. The memory device of claim 12 wherein the data latch circuit comprises a pair of inverters configured to sense a potential level of a respective bit line.