Author: claimsbot

1. A system comprising:
a mobile communications device;
a wireless headset including a speaker and a microphone; and
a switching unit comprising, separate from and detachably coupled to the mobile communication device through a cabled connection, the switching unit comprising:
a mobile communications device interface for transmitting signals to and receiving signals from the mobile communications device;
a wireless adapter for transmitting signals to and receiving signals from the wireless headset; and
a switch coupled to the mobile communications device interface, the wireless headset and the wireless adapter, wherein the switch is configured to automatically implement push-to-talk functionality by selectively connecting signals between the wireless adapter, the wireless headset, and the mobile communications device interface,
wherein a trigger signal generated when a signal level associated with the microphone exceeds a predetermined threshold causes the switch to be set to a first position in which a signal captured by the microphone is connected to the mobile communications device interface and a trigger signal generated when the signal level associated with the microphone falls below a predetermined threshold for a predetermined period of time causes the switch to be set to a second position in which a signal captured by the microphone is not connected to the mobile communications device interface and a signal is transmitted from the mobile communication device to the speaker of the wireless headset.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for retroactively converting the storage of a plurality of data clusters from a circular buffer to a linear buffer, comprising the steps of:
(A) determining a starting point in said circular buffer, wherein said circular buffer (i) comprises a plurality of linked data clusters and (ii) is accessed by moving directly from a first data cluster to a second data cluster in response to an address of said second data cluster being stored within said first data cluster;
(B) breaking said circular buffer before said starting point to convert said circular buffer to said linear buffer; and
(C) appending to an ending point of said linear buffer, wherein said method performs said conversion without duplicating any of said linked data clusters.
2. The method according to claim 1, wherein said method is used for storing an audiovideo program.
3. The method according to claim 1, wherein said data clusters in said linear buffer are marked to (i) not be overwritten and (ii) be available for future use.
4. The method according to claim 1, wherein (i) said circular buffer comprises a time-shifted circular buffer and (ii) said data clusters in said circular buffer are marked to be overwritten.
5. The method according to claim 1, wherein step (B) breaks said circular buffer without duplicating data stored in said circular buffer.
6. The method according to claim 1, wherein said starting point comprises a head and said ending point comprises a tail.
7. The method according to claim 6, wherein step (A) further comprises rotating said circular buffer to said head.
8. The method according to claim 1, wherein said data clusters comprise a plurality of bi-directionally linked data clusters.
9. The method according to claim 1, wherein data stored in said circular buffer is simultaneously accessible as a temporary linear buffer.
10. The method according to claim 1, wherein said step (A) is initiated in response to a user input defining a relative time.
11. The method according to claim 1, wherein said step (A) is initiated in response to a user input defining an absolute time.
12. The method according to claim 1, wherein said step (A) is initiated in response to a user input defining a program guide time.
13. A method for recording, comprising the steps of:
(A) recording to a plurality of data clusters configured as a circular buffer, wherein said data clusters (i) comprise linked data clusters arid (ii) are accessed by moving directly from one of said data clusters to another of said data cluster in response to an address of said another of data cluster being stored within said one of said data clusters;
(B) initiating a retroactive conversion of said data clusters to a linear buffer, wherein said conversion begins at a starting point representing a time within said data clusters;
(C) breaking said data clusters at said starting point to mark a beginning of said linear buffer; and
(D) marking said data clusters in said linear buffer to be saved for future use, wherein said method performs said conversion without duplicating any of said linked data clusters.
14. A computer readable medium encoded with a computer program containing one or more sets of executable instructions for performing the steps of claim 1.
15. The method according to claim 13, further comprising the step of:
appending additional material to an end of said data clusters configured as said linear buffer.
16. The method according to claim 13, wherein said data clusters comprise a plurality of bi-directionally linked data clusters.
17. The method according to claim 13, wherein step (B) further comprises rotating said data clusters to said starting point.
18. An apparatus comprising:
a plurality of bi-directionally linked data clusters wherein said plurality of data clusters are consecutively accessed (i) without referencing a central file table and (ii) by moving directly from a first data cluster to a second data cluster in response to an address of said second data cluster being stored within said first data cluster;
a first pointer configured to indicate a start of a window comprising a predetermined number of said data clusters; and
a second pointer configured to indicate an end of said window, wherein data stored in said data clusters is converted between a circular buffer configuration and a linear buffer configuration in response to a user input, wherein the data is converted without duplicating any of said linked data clusters.
19. The apparatus according to claim 18, wherein (i) during a first mode of operation of said apparatus a first of said plurality of data clusters is bi-directionally linked to a last of said data clusters such that said data clusters form said circular buffer and (ii) during a second mode of operation said first pointer is positioned to indicate a start of said linear buffer.
20. The apparatus according to claim 19, wherein during said second mode of operation said first pointer is rotated to one of said plurality of data clusters in response to a user selected time.

What is claimed is:

1. (Currently amended) A switch in bipolar technology, comprising:
a first main transistor (1) of a first type connecting an input terminal (IN), intended to be connected to a first terminal of application of a D.C. supply voltage (Vcc), to an output terminal (OUT) intended to be connected to a load (Q) to be supplied;
a second bipolar transistor (2) of the same type as the first one, connected between said input terminal and an input of a current mirror circuit (3, 4) having a copying output connected to the base of the first transistor, the bases of the first and second transistors being interconnected and the first transistor having an emitter surface area greater than the second one;
further comprising a circuit (6) for biasing the second transistor consisting in the copying of the output voltage of the switch on the collector of this second transistor.
2. (Currently amended) The switch of claim 1, wherein said current mirror circuit (3, 4) is formed of a third bipolar transistor (3) of a second type and of a fourth bipolar transistor (4) of the second type connecting the base of the first transistor (1) to a second terminal (M) of application of the supply voltage, the bases of the third and fourth transistors being interconnected to the collector of the third transistor connecting the collector of the second transistor via a fifth bipolar transistor (10) of the first type belonging to the biasing circuit (6).
3. (Currently amended) The switch of claim 2, wherein the fourth transistor (4) has an emitter surface area greater than that of the third transistor (3).
4. (Currently amended) The switch of claim 2 or 3, wherein the biasing circuit further comprises a sixth transistor (11) of the second type connected between said output terminal (OUT) by its emitter and a seventh bipolar transistor (12) of the second type mirror-assembled on said third (3) and fourth (4) transistors, the emitter surface area of the seventh transistor being, preferably, identical to that of the third transistor.
5. (Currently amended) The switch of any of claims 2 to 4 claim 2, wherein a starting current source (7) connects the base of the first transistor (1) to the second terminal of application of the supply voltage.
6. (Currently amended) The switch of any of claims 2 to 5 claim 2, wherein a start-up aid circuit (8) injects a current on the collector of the second transistor (2), the start-up aid circuit being preferably formed of a resistor (R8) in series with an eighth transistor (13) of the first type connected between the input terminal (IN) and said collector of the second transistor, the base of the eighth transistor being connected to the base of the first transistor (1) to inject a current which is an image of the output current.
7. (Currently amended) The switch of any of claims 2 to 6 claim 2, wherein a circuit for limiting the internal current formed, preferably, of a resistor (R9) interposed between the collectors of the fifth (10) and third (3) transistors, and of a ninth transistor (14) for branching the current to ground, is provided.
8. (Currently amended) The switch of any of claims 1 to 7 claim 1, wherein the transistors of the first type are PNP transistors, the transistors of the second type being NPN transistors.
9. (Currently amended) The switch of any of claims 1 to 7 claim 1, wherein the transistors of the first type are NPN-type transistors, the transistors of the second type being PNP-type transistors.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for controlling execution of multiple tasks in a processing circuit including several processing modules, comprising the steps of:
determining temperature-associated information at various areas of the processing circuit; and
in response to temperature-associated information indicating an excessive temperature at an area associated with a first of said processing modules, modifying parameters for executing tasks on one or more adjacent processing modules in order to reduce heat generated by the adjacent processing modules and contributing to the excessive temperature at the first processing module.
2. The method of claim 1 wherein said determining step comprises the step of monitoring operations executed by said modules.
3. The method of claim 1 wherein said determining step comprises the step of calculating power dissipation information at various locations in said processing circuit.
4. The method of claim 1 wherein said determining step comprises the step of calculating a current temperature at various locations in said processing circuit.
5. A method for controlling execution of multiple tasks in a processing circuit including a plurality of processing modules, comprising the steps of:
generating a task allocation scenario for allocating multiple tasks among the plurality of processing modules;
prior to executing the tasks, estimating temperature-associated information for various locations in the processing circuit as would occur if the tasks were executed according to the scenario;
determining whether a temperature threshold would be exceeded by executing the tasks according to the scenario.
6. The method of claim 5 wherein said step of generating a task allocation scenario comprises the step of receiving a task list describing the tasks to be executed and a task model describing the tasks.
7. The method of claim 6 wherein the task model includes initial area-specific power dissipation estimates for each task.
8. A processing circuit including a plurality of processing modules for executing multiple tasks comprising:
circuitry for determining temperature-associated information at various areas of the processing circuit; and
circuitry responsive to temperature-associated information indicating an excessive temperature at an area associated with a first of said processing modules for modifying parameters for executing tasks on one or more adjacent processing modules in order to reduce heat generated by the adjacent processing modules and contributing to the excessive temperature at the first processing module.
9. The processing circuit of claim 8 wherein said determining circuitry comprises circuitry for monitoring operations executed by said processing modules.
10. The processing circuit of claim 8 wherein said determining circuitry comprises circuitry for calculating power dissipation information at various locations in said processing circuit.
11. The processing circuit of claim 8 wherein said determining circuitry comprises circuitry for calculating a current temperature at various locations in said processing circuit.
12. A processing circuit comprising:
a plurality of processing modules for executing multiple tasks; and
circuitry for generating a task allocation scenario for allocating the tasks among the processing modules, estimating temperature-associated information for various locations in the processing circuit as would occur if the tasks were executed according to the scenario and determining whether a temperature threshold would be exceeded if the tasks were to be executed according to the scenario.
13. The processing circuit of claim 12 wherein said circuitry for generating a task allocation scenario comprises circuitry for receiving a task list describing the tasks to be executed and a task model describing the tasks.
14. The processing circuit of claim 13 wherein the task model includes initial area-specific power dissipation estimates for each task.
15. A mobile communications device comprising:
a plurality of processing modules for executing a plurality of tasks;
an antenna for receiving and transmitting signals; and
receivertransmitter circuitry coupled to said antenna for sending and receiving audio and data signals, said receivertransmitter circuitry including a processing circuit comprising:
circuitry for determining temperature-associated information at various areas of the processing circuit; and
circuitry responsive to temperature-associated information indicating an excessive temperature at an area associated with a first of said processing modules for modifying parameters for executing tasks on one or more adjacent processing modules in order to reduce heat generated by the adjacent processing modules and contributing to the excessive temperature at the first processing module.