Author: claimsbot

1. A structure comprising:
a substrate layer;
an array of posts, wherein the array of posts and the substrate layer are integrally formed from a single piece of material comprising a polymer material;
a corresponding array of laterally separate micro devices on the array of posts, wherein each micro device includes a bottom surface that is wider than a corresponding post top surface directly underneath the micro device; and
an array of laterally separate metallization layers between the array of laterally separate micro devices and the array of posts.
2. The structure of claim 1, wherein each of the micro devices are of 1-100 \u03bcm scale.
3. The structure of claim 1, wherein each micro device includes p-n diode layer comprising:
a p-doped layer;
an n-doped layer; and
a quantum well layer between the p-doped layer and the n-doped layer.
4. The structure of claim 1, wherein each of the posts has a height between 0.2-4 \u03bcm.
5. The structure of claim 1, further comprising a dielectric layer spanning the bottom surface of each micro device, side surfaces of each post, and a top surface of the substrate layer.
6. The structure of claim 1, wherein each metallization layer includes a bottom surface that is wider than the corresponding post top surface directly underneath the micro device.
7. The structure of claim 6, wherein the bottom surface of each micro device is wider than a top surface of each corresponding metallization layer.
8. The structure of claim 6, wherein each metallization layer makes ohmic contact with each corresponding micro device.
9. The structure of claim 6, wherein each metallization layer is reflective to light emission.
10. The structure of claim 6, wherein each micro device includes p-n diode layer comprising:
a p-doped layer;
an n-doped layer; and
a quantum well layer between the p-doped layer and the n-doped layer.
11. The structure of claim 1, further comprising an array of laterally separate bonding layers between the array of posts and the array of laterally separate metallization layers.
12. The structure of claim 11, wherein array of laterally separate bonding layers is formed of a metal or metal alloy.
13. The structure of claim 12, wherein the array of laterally separate bonding layers is in direct contact with the array of posts and the array of laterally separate metallization layers.
14. The structure of claim 11, wherein the bonding layer has a liquidus temperature such that the bonding layer melts at a temperature without substantially affecting other components of the laterally separate micro devices.
15. The structure of claim 1, further comprising a dielectric layer spanning the bottom surface of each micro device, a bottom surface of the laterally separate metallization layers, side surfaces of each post, and a top surface of the substrate layer.
16. The structure of claim 3, wherein the quantum well layer has a thickness of less than approximately 0.3 \u03bcm.
17. The structure of claim 3, wherein the p-doped layer has a thickness of approximately 0.1-1 \u03bcm.
18. The structure of claim 3, wherein the n-doped layer has a thickness of approximately 0.1-6 \u03bcm.
19. The structure of claim 3, wherein the p-n diode layer has a thickness of less than approximately 9.3 \u03bcm.
20. The structure of claim 2, comprising millions of laterally separate micro devices on a corresponding millions of posts.
21. The structure of claim 2, comprising hundreds of millions of laterally separate micro devices on a corresponding hundreds of millions of posts.
22. The structure of claim 3, wherein each p-n diode layer comprises a top surface, a bottom surface, and tapered sidewalls.
23. The structure of claim 22, wherein the bottom surface of the p-n diode layer is wider than the top surface of the p-n diode layer.
24. The structure of claim 22, wherein the top surface of the p-n diode layer is wider than the bottom surface of the p-n diode layer.
25. The structure of claim 3, wherein each p-n diode layer comprises a top surface, a bottom surface, and vertical sidewalls.
26. The structure of claim 1, wherein each micro device comprises a micro semiconductor device selected from the group consisting of a diode, transistor, or integrated circuit.
27. The structure of claim 1, wherein each micro device comprises a micro semiconductor device selected from the group consisting of a light emitting diode and laser.
28. The structure of claim 1, wherein the array of posts are formed of a dielectric material.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for processing signals, the method comprising:
performing by one or more processors andor circuits:
receiving a signal via a radio frequency (RF) channel, wherein said RF channel comprises a plurality of frequencies;
computing one or more channel estimate values for a portion of said plurality of frequencies based on said received signal; and
computing one or more subsequent channel estimate values for at least a subsequent portion of said plurality of frequencies by iteratively computing a time domain channel matrix and a frequency domain channel matrix based on said computed one or more channel estimate values and a channel noise value for said RF channel,
wherein iteratively computing the frequency domain channel matrix includes applying a time-to-frequency transformation matrix to the time domain channel matrix, the time-to-frequency transformation matrix being computed using non-pilot tone frequencies.
2. The method according to claim 1, wherein said portion of said plurality of frequencies comprises pilot tone frequencies.
3. The method according to claim 1, further comprising:
determining one or more initial values for said one or more subsequent channel estimate values.
4. The method according to claim 3, wherein said one or more initial values are each equal to 0.
5. The method according to claim 3, wherein computing one or more subsequent channel estimate values includes using a minimum mean square error algorithm.
6. A method for processing signals, the method comprising:
performing by one or more processors andor circuits:
receiving a signal via a radio frequency (RF) channel, wherein said RF channel comprises a plurality of frequencies;
computing one or more channel estimate values for a portion of said plurality of frequencies based on said received signal;
computing one or more subsequent channel estimate values for at least a subsequent portion of said plurality of frequencies based on said computed one or more channel estimate values and a channel noise value for said RF channel;
determining one or more initial values for said one or more subsequent channel estimate values;
computing one or more time domain current iteration values for said RF channel based on said one or more initial values, said one or more channel estimate values and said channel noise value; and
computing one or more frequency domain current iteration values for said at least said subsequent portion of said plurality of frequencies based on said one or more time domain current iteration values and a conversion matrix, wherein said conversion matrix is based on said at least said subsequent portion of said plurality of frequencies.
7. The method according to claim 6, further comprising:
computing one or more time domain subsequent iteration values for said RF channel based on said one or more frequency domain current iteration values, said one or more channel estimate values and said channel noise value.
8. The method according to claim 7, further comprising:
computing one or more frequency domain subsequent iteration values for said at least said subsequent portion of said plurality of frequencies based on said one or more time domain subsequent iteration values and said conversion matrix.
9. The method according to claim 8, further comprising:
computing said one or more subsequent channel estimate values based on said one or more frequency domain subsequent iteration values.
10. The method according to claim 8, further comprising:
computing a channel estimate matrix for said RF channel based on a matrix generated from said one or more frequency domain subsequent iteration values and a matrix generated from said one or more channel estimate values.
11. A system for processing signals, the system comprising:
one or more circuits that enable reception of a signal via a radio frequency (RF) channel, wherein said RF channel comprises a plurality of frequencies;
wherein said one or more circuits enable computation of one or more channel estimate values for a portion of said plurality of frequencies based on said received signal;
wherein said one or more circuits enable computation of one or more subsequent channel estimate values for at least a subsequent portion of said plurality of frequencies by iteratively computing a time domain channel matrix and a frequency domain channel matrix based on said computed one or more channel estimate values and a channel noise value for said RF channel, and
wherein iteratively computing the frequency domain channel matrix includes applying a time-to-frequency transformation matrix to the time domain channel matrix, the time-to-frequency transformation matrix being computed using non-pilot tone frequencies.
12. The system according to claim 11, wherein said portion of said plurality of frequencies comprises pilot tone frequencies.
13. The system according to claim 11, wherein said one or more circuits further enable determination of one or more initial values for said one or more subsequent channel estimate values.
14. The system according to claim 13, wherein said one or more initial values are each equal to 0.
15. The system according to claim 13, wherein said one or more circuits further enable computation of one or more subsequent channel estimate values by using a minimum mean square error algorithm.
16. A system for processing signals, the system comprising:
one or more circuits that enable reception of a signal via a radio frequency (RF) channel, wherein said RF channel comprises a plurality of frequencies;
wherein said one or more circuits enable computation of one or more channel estimate values for a portion of said plurality of frequencies based on said received signal;
wherein said one or more circuits enable computation of one or more subsequent channel estimate values for at least a subsequent portion of said plurality of frequencies based on said computed one or more channel estimate values and a channel noise value for said RF channel;
wherein said one or more circuits enable determination of one or more initial values for said one or more subsequent channel estimate values;
wherein said one or more circuits enable computation of one or more time domain current iteration values for said RF channel based on said one or more initial values, said one or more channel estimate values and said channel noise value; and
wherein said one or more circuits further enable computation of one or more frequency domain current iteration values for said at least said subsequent portion of said plurality of frequencies based on said one or more time domain current iteration values and a conversion matrix, wherein said conversion matrix is based on said at least said subsequent portion of said plurality of frequencies.
17. The system according to claim 16, wherein said one or more circuits further enable computation of one or more time domain subsequent iteration values for said RF channel based on said one or more frequency domain cur-ent iteration values, said one or more channel estimate values and said channel noise value.
18. The system according to claim 17, wherein said one or more circuits further enable computation of one or more frequency domain subsequent iteration values for said at least said subsequent portion of said plurality of frequencies based on said one or more time domain subsequent iteration values and said conversion matrix.
19. The system according to claim 18, wherein said one or more circuits further enable computation of said one or more subsequent charnel estimate values based on said one or more frequency domain subsequent iteration values.
20. The system according to claim 18, wherein said one or more circuits further enable computation of a channel estimate matrix for said RF channel based on a matrix generated from said one or more frequency domain subsequent iteration values and a matrix generated from said one or more channel estimate values.

1. A computer-implemented method for managing a plurality of processors as a virtual devices, said method comprising:
receiving a device request at a task queue manager running on a first processor in a computer system, wherein the computer system includes a plurality of heterogeneous processors that share a common memory and wherein the device request corresponds to a virtual device;
storing data corresponding to the request in the common memory;
identifying a second processor from the plurality of processors to handle the request;
signaling, from the first processor, the identified second processor;
receiving the data corresponding to the request at the second processor; and
processing the data by the second processor using software code stored in the second processor’s local memory.
2. The method as described in claim 1 wherein the identifying further comprises:
detecting a utilization of one or more processors from the plurality of processors; and
selecting the second processor based upon its low utilization.
3. The method as described in claim 1 wherein the identifying further comprises:
detecting that the software code is loaded in the second processor’s local memory.
4. The method as described in claim 1 further comprising:
creating, by the first processor, a task block in the common memory, the task block including a software code identifier; and
writing the address of the task block to a mailbox corresponding to the second processor.
5. The method as described in claim 4 further comprising:
receiving, at the second processor, the address of the task block from the second processor’s mailbox;
retrieving, at the second processor, the software code identifier from the task block;
determining whether the software code corresponding to the software code identifier is loaded in the second processor’s local memory; and
in response to determining that the software code corresponding to the software code identifier is not loaded in the second processor’s local memory:
reading the software code from the common memory into the second processor’s local memory, wherein the reading is performed using a DMA operation.
6. The method as described in claim 1 further comprising:
creating a plurality of queues, each of the queues corresponding to a virtual device;
writing the device request to a first queue from the plurality of queues, wherein the first queue corresponds to the virtual device; and
assigning the first queue to the second processor.
7. The method as described in claim 1 further comprising:
creating, by the first processor, a task block in the common memory, the task block including a software code identifier and an input buffer address; and
writing the address of the task block to a mailbox corresponding to the second processor.
8. The method as described in claim 7 further comprising:
receiving, at the second processor, the address of the task block from the second processor’s mailbox;
retrieving, at the second processor, the software code identifier from the task block;
reading data from an input buffer located in the common memory at a location corresponding to the input buffer address into the second processor’s local memory, wherein the reading is performed using a DMA operation;
determining whether the software code corresponding to the software code identifier is loaded in the second processor’s local memory; and
in response to determining that the software code corresponding to the software code identifier is not loaded in the second processor’s local memory:
reading the software code from the common memory into the second processor’s local memory, wherein the reading is performed using a DMA operation.
9. The method as described in claim 1 further comprising:
receiving, at the first processor, a notification that the second processor has completed the processing; and
notifying, by the first processor, a software process from which the device request was received in response to receiving the notification from the second processor.
10. The method as described in claim 1 wherein the first processor and the second processor are dislike processors, wherein the first processor is adapted to execute a first instruction set and wherein the second processor is adapted to execute a second instruction set.
11. A computer-implemented method for using a processor as a virtual device, said method comprising:
initializing a task queue in a common memory, the task queue corresponding to a device;
receiving a device request from a first processor of a plurality processors in a computer system, wherein the plurality of processors share the common memory;
storing the request in the task queue and storing the input data corresponding to the request in the common memory;
assigning the task queue to a second processor selected from the plurality of processors;
signaling the second processor regarding the assignment;
loading the input data into a local memory corresponding to the second processor; and
processing the loaded input data using software code executing on the second processor.
12. The method as described in claim 11 wherein the assigning further comprises:
detecting a utilization of one or more processors from the plurality of processors; and
selecting the second processor based upon its low utilization.
13. The method as described in claim 11 wherein the assigning further comprises:
detecting that the software code is loaded in the second processor’s local memory.
14. The method as described in claim 11 wherein the first processor and the second processor are dislike processors, wherein the first processor is adapted to execute a first instruction set and wherein the second processor is adapted to execute a second instruction set.
15. The method as described in claim 11 further comprising:
creating, by the first processor, a task block in the common memory, the task block including a software code identifier; and
writing the address of the task block to a mailbox corresponding to the second processor.
16. The method as described in claim 15 further comprising:
receiving, at the second processor, the address of the task block from the second processor’s mailbox;
retrieving, at the second processor, the software code identifier from the task block;
determining whether the software code corresponding to the software code identifier is loaded in the second processor’s local memory; and
in response to determining that the software code corresponding to the software code identifier is not loaded in the second processor’s local memory:
reading the software code from the common memory into the second processor’s local memory, wherein the reading is performed using a DMA operation.
17. The method as described in claim 11 further comprising:
creating, by the first processor, a task block in the common memory, the task block including a software code identifier and the address of the input data; and
writing the address of the task block to a mailbox corresponding to the second processor.
18. The method as described in claim 17 further comprising:
receiving, at the second processor, the address of the task block from the second processor’s mailbox; and
retrieving, at the second processor, the software code identifier and the address of the input data from the task block, wherein the loading includes reading the input data located at the input data address in the common memory into the second processor’s local memory using a DMA operation.
19. The method as described in claim 11 further comprising:
receiving, at the first processor, a notification that the second processor has completed the processing; and
notifying, by the first processor, a software process from which the device request was received in response to receiving the notification from the second processor.
20. The method as described in claim 19 wherein the notifying further comprises:
writing completion data resulting from the processing to a data structure; and
providing the data structure to software process.
21. An information handling system comprising:
a plurality of heterogeneous processors;
a common memory shared by the plurality of heterogeneous processors;
a first processor selected from the plurality of processors that sends a request to a second processor, the second processor also being selected from the plurality of processors;
a local memory corresponding to the second processor;
a DMA controller associated with the second processor, the DMA controller adapted to transfer data between the common memory and the second processor’s local memory; and
a virtual device tool for managing a plurality of processors as a virtual devices, the virtual device tool including software effective to:
receive a virtual device request at a task queue manager running on the first processor;
store data corresponding to the request in the common memory;
identify the second processor to handle the request from the plurality of processors;
signal, from the first processor, the identified second processor;
receive the data corresponding to the request at the second processor; and
process the data by the second processor using software code stored in the second processor’s local memory.
22. The information handling system as described in claim 21 wherein the identification of the second processor further comprises software effective to:
detect a utilization of one or more processors from the plurality of processors; and
select the second processor based upon its low utilization.
23. The information handling system as described in claim 21 wherein the identification of the second processor further comprises software effective to:
detect that the software code is loaded in the second processor’s local memory.
24. The information handling system as described in claim 21 further comprising software effective to:
create, by the first processor, a task block in the common memory, the task block including a software code identifier; and
write the address of the task block to a mailbox corresponding to the second processor.
25. The information handling system as described in claim 24 further comprising software effective to:
receive, at the second processor, the address of the task block from the second processor’s mailbox;
retrieve, at the second processor, the software code identifier from the task block;
determine whether the software code corresponding to the software code identifier is loaded in the second processor’s local memory; and
in response to determining that the software code corresponding to the software code identifier is not loaded in the second processor’s local memory, executing software effective to:
read the software code from the common memory into the second processor’s local memory, wherein the reading is performed using a DMA operation.
26. The information handling system as described in claim 21 further comprising software effective to:
create a plurality of queues, each of the queues corresponding to a virtual device;
write the device request to a first queue from the plurality of queues, wherein the first queue corresponds to the virtual device; and
assign the first queue to the second processor.
27. The information handling system as described in claim 21 further comprising software effective to:
create, by the first processor, a task block in the common memory, the task block including a software code identifier and an input buffer address; and
write the address of the task block to a mailbox corresponding to the second processor.
28. The information handling system as described in claim 27 further comprising software effective to:
receive, at the second processor, the address of the task block from the second processor’s mailbox;
retrieve, at the second processor, the software code identifier from the task block;
read data from an input buffer located in the common memory at a location corresponding to the input buffer address into the second processor’s local memory, wherein the reading is performed using a DMA operation;
determine whether the software code corresponding to the software code identifier is loaded in the second processor’s local memory; and
in response to determining that the software code corresponding to the software code identifier is not loaded in the second processor’s local memory, perform software effective to:
read the software code from the common memory into the second processor’s local memory, wherein the reading is performed using a DMA operation.
29. The information handling system as described in claim 21 further comprising software effective to:
receive, at the first processor, a notification that the second processor has completed the processing; and
notify, by the first processor, a software process from which the device request was received in response to receiving the notification from the second processor.
30. The information handling system as described in claim 21 wherein the first processor and the second processor are dislike processors, wherein the first processor is adapted to execute a first instruction set and wherein the second processor is adapted to execute a second instruction set.
31. An information handling system comprising:
a plurality of heterogeneous processors;
a common memory shared by the plurality of heterogeneous processors;
a first processor selected from the plurality of processors that sends a request to a second processor, the second processor also being selected from the plurality of processors;
a local memory corresponding to the second processor;
a DMA controller associated with the second processor, the DMA controller adapted to transfer data between the common memory and the second processor’s local memory; and
a virtual device tool for managing a plurality of processors as a virtual devices, the virtual device tool including software effective to:
initialize a task queue in the common memory, the task queue corresponding to a virtual device;
receive a virtual device request from the first processor;
store the request in the task queue and store the input data corresponding to the request in the common memory;
assign the task queue to the second processor selected from the plurality of processors;
signal the second processor regarding the assignment;
load the input data into a local memory corresponding to the second processor; and
process the loaded input data using software code executing on the second processor.
32. The information handling system as described in claim 31 wherein the assignment further comprises software effective to:
detect a utilization of one or more processors from the plurality of processors; and
select the second processor based upon its low utilization.
33. The information handling system as described in claim 31 wherein the assignment further comprises software effective to:
detect that the software code is loaded in the second processor’s local memory.
34. The information handling system as described in claim 31 wherein the first processor and the second processor are dislike processors, wherein the first processor is adapted to execute a first instruction set and wherein the second processor is adapted to execute a second instruction set.
35. The information handling system as described in claim 31 further comprising software effective to:
create, by the first processor, a task block in the common memory, the task block including a software code identifier; and
write the address of the task block to a mailbox corresponding to the second processor.
36. The information handling system as described in claim 35 further comprising software effective to:
receive, at the second processor, the address of the task block from the second processor’s mailbox;
retrieve, at the second processor, the software code identifier from the task block;
determine whether the software code corresponding to the software code identifier is loaded in the second processor’s local memory; and
in response to determining that the software code corresponding to the software code identifier is not loaded in the second processor’s local memory, perform software effective to:
read the software code from the common memory into the second processor’s local memory, wherein the reading is performed using a DMA operation.
37. The information handling system as described in claim 31 further comprising software effective to:
create, by the first processor, a task block in the common memory, the task block including a software code identifier and the address of the input data; and
write the address of the task block to a mailbox corresponding to the second processor.
38. The information handling system as described in claim 37 further comprising software effective to:
receive, at the second processor, the address of the task block from the second processor’s mailbox; and
retrieve, at the second processor, the software code identifier and the address of the input data from the task block, wherein the loading includes reading the input data located at the input data address in the common memory into the second processor’s local memory using a DMA operation.
39. The information handling system as described in claim 31 further comprising software effective to:
receive, at the first processor, a notification that the second processor has completed the processing; and
notify, by the first processor, a software process from which the device request was received in response to receiving the notification from the second processor.
40. The information handling system as described in claim 39 wherein the notification of the software process further comprises software effective to:
write completion data resulting from the processing to a data structure; and
provide the data structure to software process.
41. A computer program product stored on a computer operable media for managing a plurality of processors as a virtual devices, said computer program product comprising:
means for receiving a device request at a task queue manager running on a first processor in a computer system, wherein the computer system includes a plurality of heterogeneous processors that share a common memory and wherein the device request corresponds to a virtual device;
means for storing data corresponding to the request in the common memory;
means for identifying a second processor from the plurality of processors to handle the request;
means for signaling, from the first processor, the identified second processor;
means for receiving the data corresponding to the request at the second processor; and
means for processing the data by the second processor using software code stored in the second processor’s local memory.
42. The computer program product as described in claim 41 wherein the means for identifying further comprises:
means for detecting a utilization of one or more processors from the plurality of processors; and
means for selecting the second processor based upon its low utilization.
43. The computer program product as described in claim 41 wherein the means for identifying further comprises:
means for detecting that the software code is loaded in the second processor’s local memory.
44. The computer program product as described in claim 41 further comprising:
means for creating, by the first processor, a task block in the common memory, the task block including a software code identifier; and
means for writing the address of the task block to a mailbox corresponding to the second processor.
45. The computer program product as described in claim 44 further comprising:
means for receiving, at the second processor, the address of the task block from the second processor’s mailbox;
means for retrieving, at the second processor, the software code identifier from the task block;
means for determining whether the software code corresponding to the software code identifier is loaded in the second processor’s local memory; and
in response to determining that the software code corresponding to the software code identifier is not loaded in the second processor’s local memory:
means for reading the software code from the common memory into the second processor’s local memory, wherein the reading is performed using a DMA operation.
46. The computer program product as described in claim 41 further comprising:
means for creating a plurality of queues, each of the queues corresponding to a virtual device;
means for writing the device request to a first queue from the plurality of queues, wherein the first queue corresponds to the virtual device; and
means for assigning the first queue to the second processor.
47. The computer program product as described in claim 41 further comprising:
means for creating, by the first processor, a task block in the common memory, the task block including a software code identifier and an input buffer address; and
means for writing the address of the task block to a mailbox corresponding to the second processor.
48. The computer program product as described in claim 47 further comprising:
means for receiving, at the second processor, the address of the task block from the second processor’s mailbox;
means for retrieving, at the second processor, the software code identifier from the task block;
means for reading data from an input buffer located in the common memory at a location corresponding to the input buffer address into the second processor’s local memory, wherein the reading is performed using a DMA operation;
means for determining whether the software code corresponding to the software code identifier is loaded in the second processor’s local memory; and
in response to determining that the software code corresponding to the software code identifier is not loaded in the second processor’s local memory:
means for reading the software code from the common memory into the second processor’s local memory, wherein the reading is performed using a DMA operation.
49. The computer program product as described in claim 41 further comprising:
means for receiving, at the first processor, a notification that the second processor has completed the processing; and
means for notifying, by the first processor, a software process from which the device request was received in response to receiving the notification from the second processor.
50. The computer program product as described in claim 41 wherein the first processor and the second processor are dislike processors, wherein the first processor is adapted to execute a first instruction set and wherein the second processor is adapted to execute a second instruction set.
51. A computer program product stored on a computer operable media for managing a plurality of processors as a virtual devices, said computer program product comprising:
means for initializing a task queue in a common memory, the task queue corresponding to a device;
means for receiving a device request from a first processor of a plurality processors in a computer system, wherein the plurality of processors share the common memory;
means for storing the request in the task queue and storing the input data corresponding to the request in the common memory;
means for assigning the task queue to a second processor selected from the plurality of processors;
means for signaling the second processor regarding the assignment;
means for loading the input data into a local memory corresponding to the second processor; and
means for processing the loaded input data using software code executing on the second processor.
52. The computer program product as described in claim 51 wherein the means for assigning further comprises:
means for detecting a utilization of one or more processors from the plurality of processors; and
means for selecting the second processor based upon its low utilization.
53. The computer program product as described in claim 51 wherein the means for assigning further comprises:
means for detecting that the software code is loaded in the second processor’s local memory.
54. The computer program product as described in claim 51 wherein the first processor and the second processor are dislike processors, wherein the first processor is adapted to execute a first instruction set and wherein the second processor is adapted to execute a second instruction set.
55. The computer program product as described in claim 51 further comprising:
means for creating, by the first processor, a task block in the common memory, the task block including a software code identifier; and
means for writing the address of the task block to a mailbox corresponding to the second processor.
56. The computer program product as described in claim 55 further comprising:
means for receiving, at the second processor, the address of the task block from the second processor’s mailbox;
means for retrieving, at the second processor, the software code identifier from the task block;
means for determining whether the software code corresponding to the software code identifier is loaded in the second processor’s local memory; and
in response to determining that the software code corresponding to the software code identifier is not loaded in the second processor’s local memory:
means for reading the software code from the common memory into the second processor’s local memory, wherein the reading is performed using a DMA operation.
57. The computer program product as described in claim 51 further comprising:
means for creating, by the first processor, a task block in the common memory, the task block including a software code identifier and the address of the input data; and
means for writing the address of the task block to a mailbox corresponding to the second processor.
58. The computer program product as described in claim 57 further comprising:
means for receiving, at the second processor, the address of the task block from the second processor’s mailbox; and
means for retrieving, at the second processor, the software code identifier and the address of the input data from the task block, wherein the loading includes reading the input data located at the input data address in the common memory into the second processor’s local memory using a DMA operation.
59. The computer program product as described in claim 51 further comprising:
means for receiving, at the first processor, a notification that the second processor has completed the processing; and
means for notifying, by the first processor, a software process from which the device request was received in response to receiving the notification from the second processor.
60. The computer program product as described in claim 59 wherein the means for notifying further comprises:
means for writing completion data resulting from the processing to a data structure; and
means for providing the data structure to software process.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A food composition for recovery from fatigue, comprising an extract of migratory fish as an effective ingredient.
2. The food composition for recovery from fatigue according to claim 1, comprising, in addition to the extract of migratory fish, at least one additive selected from the group consisting of other nutritional components, anti-fatigue components, taste-improving components, diluting components, bacteriostatic components and coloring matters.
3. The food composition for recovery from fatigue according to claim 1 or 2, wherein the migratory fish is fish belonging to Perciformes Scombrina.
4. The food composition for recovery from fatigue according to claim 1 or 2, wherein the migratory fish is bonito.
5. The food composition for recovery from fatigue according to claim 1 or 2, wherein the migratory fish is tuna.
6. The food composition for recovery from fatigue according to claim 1 or 2, wherein the extract of migratory fish is an extract that is extracted from a cooked broth of bonito meat orand tuna meat.
7. The food composition for recovery from fatigue according to claim 1 or 2, wherein the extract of migratory fish is an extract that is obtained by enzymatic hydrolysis of a cooked broth of bonito meat orand tuna meat.
8. The food composition for recovery from fatigue according to claim 1 or 2, wherein the extract of migratory fish is an extract that is obtained by heat-concentrating a cooked broth orand a steam-cooked broth of bonito meat andor tuna meat.
9. The food composition for recovery from fatigue according to claim 1 or 2, wherein the extract of migratory fish is an extract that is obtained from a brew produced by brewing by-products from fish processing of bonito andor tuna, including heads, entrails andor abdominal skins, with the use of koji mold after mincing the by-products.
10. A food composition for recovery from fatigue, comprising, as an effective ingredient, a mixture of nutritional components, said mixture comprising (a) a total of 294 mg or more of nitrogen-containing compounds such as peptides, proteins, amino acids, and the like derived from a bonito extract orand a tuna extract, or (a\u2032) 4 mg or more of each of the amino acids consisting of taurine, asparatic acid, threonine, serine, glutamic acid, proline, glycine, alanine, valine, methionine, isoleucine, leucine, tyrosine, phenylalanine, lysine, histidine, anserine, carnosine and arginine (76 mg or more in terms of a total amino acid amount); (b) a total of 55 mg or more of the organic acids consisting of lactic acid, citric acid, malic acid and succinic acid; (c) 1 mg or more of nucleic acid-related compounds; and (d) a total of 16 mg or more of mineral components such as NaCl and KCl, at a ratio by weight of, when the amino acid amount is defined as 1, from 0.5 to 2 of the organic acid, from 0.001 to 0.5 of the nucleic acid-related compound and from 0.02 to 2 of the mineral components.