Author: claimsbot

1. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate including a first region in which a memory cell transistor is arranged, a second region in which an electrode that extracts a word line electrically connected to the memory cell transistor is arranged, and a third region in which a peripheral transistor is arranged, the semiconductor substrate including an element isolation layer which separates adjacent active regions;
first active regions provided in the first region and each having a first width;
a first stacked film including a tunnel insulating film and a floating gate electrode stacked on each of the first active regions;
second active regions provided in the second region and each having a second width greater than the first width;
a second stacked film including the tunnel insulating film and the floating gate electrode stacked on each of the second active regions;
third active regions provided in the third region and each having a third width greater than the first width;
a third stacked film including the tunnel insulating film and the floating gate electrode stacked on each of the third active regions;
an intergate insulating film provided on the floating gate electrode and the element isolation layer;
a control gate electrode provided on an intergate insulating film in the first and second regions and corresponding to the word line; and
a gate electrode provided on an intergate insulating film in the third region,
wherein an upper surface of an element isolation layer in the second region is higher than an upper surface of an element isolation layer in the first region, and
a curvature radius of a corner of an upper portion of the floating gate electrode of the second stacked film is greater than that of the floating gate electrode of the third stacked film.
2. The device according to claim 1, wherein an upper surface of an element isolation layer in the third region is higher than an upper surface of the element isolation layer in the second region.
3. The device according to claim 1, further comprising:
a selection transistor provided in the first region and configured to select the memory cell,
wherein the second region further includes an electrode that extracts a selection gate line electrically connected to the selection transistor,
the selection transistor includes a fourth stacked film in which a tunnel insulating film, a floating gate electrode, an intergate insulating film, and a gate electrode are stacked,
the intergate insulating film includes a slit that electrically connects the floating gate electrode and the gate electrode, and
an end of the slit is positioned between a boundary between the first region and the second region and a second active region included in the second active regions and closest to the first region.
4. The device according to claim 1, wherein
the upper surface of the element isolation layer in the first region is lower than an upper surface of the floating gate electrode of the first stacked film, and
the upper surface of the element isolation layer in the second region is lower than an upper surface of the floating gate electrode of the second stacked film.
5. The device according to claim 1, wherein an upper surface of an element isolation layer in the third region has a height same as a height of an upper surface of the floating gate electrode of the third stacked film.
6. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate including a first region in which a memory cell transistor is arranged, a second region in which an electrode that extracts a word line electrically connected to the memory cell transistor is arranged, and a third region in which a peripheral transistor is arranged, the semiconductor substrate including an element isolation layer which separates adjacent active regions;
first active regions provided in the first region and each having a first width;
a first stacked film including a tunnel insulating film and a floating gate electrode stacked on each of the first active regions;
second active regions provided in the second region and each having a second width greater than the first width;
a second stacked film including a gate insulating film and the floating gate electrode stacked on each of the second active regions, the gate insulating film having a thickness greater than a thickness of the tunnel insulation film;
third active regions provided in the third region and each having a third with greater than the first width;
a third stacked film including the gate insulating film and the floating gate electrode stacked on each of the third active regions;
an intergate insulating film provided on the floating gate electrode and the element isolation layer;
a control gate electrode provided on an intergate insulating film in the first and second regions and corresponding to the word line; and
a gate electrode provided on an intergate insulating film in the third region,
wherein an upper surface of an element isolation layer in the second region is higher than an upper surface of an element isolation layer in the first region, and
a curvature radius of a corner of an upper portion of the floating gate electrode of the second stacked film is greater than that of the floating gate electrode of the third stacked film.
7. The device according to claim 6, wherein an upper surface of an element isolation layer in the third region is higher than an upper surface of the element isolation layer in the second region.
8. The device according to claim 6, further comprising:
a selection transistor provided in the first region and configured to select the memory cell,
wherein the second region further includes an electrode that extracts a selection gate line electrically connected to the selection transistor,
the selection transistor includes a fourth stacked film in which a tunnel insulating film, a floating gate electrode, an intergate insulating film, and a gate electrode are stacked,
the intergate insulating film includes a slit that electrically connects the floating gate electrode and the gate electrode, and
an end of the slit is positioned between a boundary between the first region and the second region and a second active region included in the second active regions and closest to the first region.
9. The device according to claim 6, wherein
the upper surface of the element isolation layer in the first region is lower than an upper surface of the floating gate electrode of the first stacked film, and
the upper surface of the element isolation layer in the second region is lower than an upper surface of the floating gate electrode of the second stacked film.
10. The device according to claim 6, wherein an upper surface of an element isolation layer in the third region has a height same as a height of an upper surface of the floating gate electrode of the third stacked film.
11. The device according to claim 6, wherein a position of an upper surfaces of the second and third active regions are less or equal to a position of an upper surfaces of the first active regions.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for determining the location of a device comprising the steps of:
(a) receiving a plurality of signals from a plurality of satellites;
(b) generating estimates of a location of the device using each different combination of the plurality of signals while leaving out N signal from the received signals; and
(c) selecting an estimate as defined by a quality of each of the combinations,
wherein N is a positive integer.
2. The method of claim 1 wherein a cardinality of the plurality of signals is at least four.
3. The method of claim 1 wherein the satellites are part of a Global Navigation Satellite System (\u201cGNSS\u201d).
4. The method of claim 3 wherein the GNSS is selected from the group consisting of: Global Positioning System (\u201cGPS\u201d), Galileo, GLONASS, and Quasi-Zenith Satellite System (\u201cQZSS\u201d).
5. The method of claim 1 wherein the quality is a function of a sum of the squared residuals.
6. The method of claim 1 wherein the device is a mobile unit.
7. The method of claim 6 wherein the mobile unit is selected from the group consisting of: cellular telephone, text messaging device, computer, portable computer, vehicle locating device, vehicle security device, communication device, and wireless transceiver.
8. The method of claim 6 wherein the mobile unit receives signals from a cellular network.
9. The method of claim 8 wherein the estimate of a location of the device is a function of signals provided by the cellular network.

1. A method for predicting simultaneous switching output noise of an integrated circuit device, comprising:
obtaining, by a computer, user input including:
an identification of an inputoutput bank of an integrated circuit die;
an identification of a device package substrate to which the integrated circuit die is to be attached; and
an identification of inputoutput interface to be used by the inputoutput bank;

selecting a noise factor and an impedance responsive to the user input;
multiplying the noise factor with the impedance to provide a result; and
outputting the result as a prediction of the simultaneous switching output noise of the integrated circuit device.
2. The method according to claim 1, wherein the user input further includes a frequency of operation.
3. The method according to claim 2, wherein the inputoutput interface is selected from inputoutput standard interfaces.
4. The method according to claim 3, wherein the user input further includes a number of aggressors.
5. A method for predicting simultaneous switching output noise of an integrated circuit device, comprising:
computing a plurality of impedance profiles as a function of frequency responsive to simulated stimulus provided to a system model,
wherein the plurality impedance profiles are for a plurality of inputoutput banks of a plurality of integrated circuit devices that include the integrated circuit device;
generating through measurement at least one excursion profile for at least one reference inputoutput bank of at least one reference die for at least one device package substrates type;
identifying a resonant frequency from the at least one excursion profile;
generating at least one base noise curve at the resonant frequency for at least one inputoutput interface using multiple quantities of aggressors;
dividing the at least one base noise curve with impedance from an impedance profile of the plurality of impedance profiles for the at least one inputoutput reference bank for the at least one device package substrate type to provide noise factors;
storing the noise factors according to the at least one inputoutput interface and the numbers of aggressors in a database;
storing the plurality of impedance profiles in the database; and
outputting a value for the predicted simultaneous switching output noise of the integrated circuit device by a prediction engine.
6. The method according to claim 5, wherein the prediction engine is configured to:
access the database to obtain a noise factor from the noise factors and an impedance from an impedance profile of the plurality of impedance profiles responsive to user input; and
multiply the noise factor by the impedance using a general-purpose processor to provide the value; and
wherein the computing the plurality of impedance profiles include:
obtaining a structural representation for a device package substrate of the at least one device package substrate type;
determining a substrate model from the structural representation;
integrating the substrate model into the system model in a simulation environment; and
providing as the stimulus a sinusoidal signal to at least one port of the system model to obtain the impedance profile through simulation.
7. The method according to claim 6, further comprising:
obtaining at least one manufacturing database file for the device package substrate; and
determining the structures using manufacturing information in the manufacturing database file,
wherein the manufacturing information includes three-dimensional representations of the structures and materials to be used for the structures.
8. The method according to claim 5, wherein:
the substrate model is a scattering parameter model configured to provide a behavior responsive to frequency of at least one circuitry network associated with the at least one inputoutput reference bank; and
the integrated circuit device includes the device package substrate and an integrated circuit die.
9. The method according to claim 8, wherein the at least one circuitry network includes a power system associated with the at least one inputoutput reference bank.
10. The method according to claim 8, wherein:
the scattering parameter model is a three port scattering parameter model in a format including lists of frequencies, magnitudes, and phases.
11. A non-transitory machine-readable medium having stored thereon information that, when executed by a general-purpose processor, cause performance of a method for predicting simultaneous switching output noise of an integrated circuit device, the method comprising:
obtaining user input including:
an identification of an inputoutput bank of an integrated circuit die;
an identification of a device package substrate to which the integrated circuit die is to be coupled;
an identification of inputoutput interface to be used by a plurality of inputoutput banks; and
a quantity of aggressors;

selecting a noise factor and an impedance responsive to the user input;
multiplying the noise factor with the impedance to provide a result; and
outputting the result as a prediction of the simultaneous switching output noise of the integrated circuit device.
12. The medium according to claim 11, wherein the user input further includes a frequency of operation.
13. The medium according to claim 12, wherein the inputoutput interface is selected from inputoutput standard interfaces.
14. The medium according to claim 13, wherein the user input further includes a number of aggressors.
15. The medium according to claim 14, wherein the method further comprises:
computing a plurality of impedance profiles as a function of frequency responsive to simulated stimulus provided to a system model;
wherein the plurality of impedance profiles are for the plurality of inputoutput banks of a plurality of integrated circuit devices that includes the integrated circuit device;
generating at least one excursion profile for at least one reference bank of at least one reference die for at least one device package substrates type;
identifying a resonant frequency from the at least one excursion profile;
generating at least one base noise curve at the resonant frequency for at least one inputoutput protocol using numbers of aggressors;
dividing the at least one base noise curve using impedance information in the plurality of impedance profiles for the at least one reference bank for the at least one device package substrate type to provide noise factors including the noise factor;
storing the noise factors according to the at least one inputoutput protocol and the numbers of aggressors in a database;
storing the plurality of impedance profiles in the database; and
outputting the result for the predicted simultaneous switching output noise of the integrated circuit device from a prediction engine;
wherein the prediction engine is configured to:
access the database to obtain the noise factor from the noise factors and the impedance from a particular impedance profile of the plurality of impedance profiles responsive to user input; and
multiply the noise factor by the impedance using the general-purpose processor.
16. The medium according to claim 15, wherein the computing the plurality of impedance profiles include:
obtaining a structural representation for a carrier substrate associated with the at least one device package substrate type;
determining a substrate model from the structural representation;
simulating the substrate model in the system model;
integrating the substrate model into the system model in a simulation environment; and
providing as the stimulus a sinusoidal signal to at least one port of the system model to obtain the particular impedance profile through simulation.
17. The medium according to claim 16, wherein the method further comprises:
obtaining at least one manufacturing database file for the carrier substrate;
determining the structures using manufacturing information in the manufacturing database file; and
the manufacturing information including three-dimensional representations of the structures and materials to be used for the structures.
18. The medium according to claim 15, wherein:
the substrate model is a scattering parameter model configured to provide a behavior responsive to frequency of at least one circuitry network associated with the at least one inputoutput reference bank.
19. The medium according to claim 18, wherein the at least one circuitry network includes a power system associated with the at least one reference bank.
20. The medium according to claim 15, wherein:
the database has stored therein the plurality of impedance profiles generated by simulation for all of the plurality of inputoutput banks of all carrier substrates of all die of a family of FPGAs; and
the database further has stored therein noise factors for all inputoutput protocols for multiple quantities of aggressors for all reference banks of all device package substrate types associated with the family of FPGAs.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of controlling a process comprising the steps of:
a) generating a first-principle model corresponding to the process;
b) inputting data describing the current and desired future process conditions;
c) generating a linear approximation to the model which is valid for said current conditions;
d) using said linear approximation to determine an approximate solution to a control problem related to the process; and
e) controlling the process using said approximate solution.
2. A method as claimed in claim 1, wherein the model is non-linear.
3. A method as claimed in claim 1 or 2, wherein the linear approximation is generated by numerical perturbation of the model.
4. A method as claimed in claim 3, wherein the linear approximation provides a quadratic programming problem which is solved to determine the approximate solution to the control problem.
5. A method as claimed in any preceding claim wherein the approximate solution thereby determined is used to determine a more precise solution.
6. A method as claimed in any preceding claim wherein the first-principle model is used to calculate a control response.
7. A method as claimed in any preceding claim wherein the generation of linear approximation to the model is repeated as required using new input data.
8. A method as claimed in any preceding claim wherein the process is a polymerisation process.
9. A method as claimed in claim 8 wherein the process comprises a transition from the production of a first grade of polymer to a second grade of polymer, the transition being controlled automatically.
10. A control apparatus for controlling a process comprising a controller, input and output means and a model, wherein:
a) said model is a fundamental model corresponding to the process;
b) means is provided for inputting data describing the current and desired future process conditions;
c) means is provided for calculating a linear approximation to the model which is valid for said input conditions;
d) means is provided for using said linear approximation to determine an approximate solution to a control problem related to the process;
e) means is provided to generate output signals for controlling the process using the solution of part (d) above.