Author: claimsbot

What is claimed is:

1. An integrated circuit, comprising:
a programmable logic device (PLD), comprising:
an array of PLD cells, each of a plurality of PLD cells comprising a nonvolatile transistor and a select transistor connected in series between a bit line and a source line, a control terminal of the nonvolatile transistor being connected to a predetermined voltage level and a control terminal of the select transistor being coupled to an input of the PLD, the nonvolatile transistors being disposed in at least one first area within the array and the select transistors being disposed in at least one second area within the array, the at least one second area being disposed adjacent the at least one first area;
a plurality of sense amplifiers, each sense amplifier being coupled to a distinct source line; and
an array of combinational logic having inputs coupled to the sense amplifiers and at least one output coupled to an output of the PLD.
2. The integrated circuit of claim 1, further comprising a nonvolatile memory device having a layout conforming to a set of design rules for nonvolatile memory devices, the layout of the array of PLD cells conforming to the set of design rules for nonvolatile memory devices.
3. The integrated circuit of claim 2, wherein the nonvolatile memory device comprises a flash memory device and the nonvolatile transistors of the PLD cell array comprises flash memory transistors.
4. The integrated circuit of claim 2, wherein the nonvolatile memory device comprises a plurality of floating-gate transistors, the nonvolatile transistors of the PLD cell array comprises floating-gate transistors, and the floating-gate transistors of the nonvolatile memory device and the floating-gate transistors of the PLD cell array having substantially the same transistor architecture.
5. The integrated circuit of claim 1, wherein the nonvolatile transistors are disposed in a plurality of first areas and the select transistors are disposed within a plurality of second areas separate from the first areas.
6. The integrated circuit of claim 5, wherein nonvolatile transistors in each first area forms PLD cells with select transistors in a distinct second area adjacent the first area.
7. The integrated circuit of claim 1, wherein electrical connections forming the PLD cells comprise segments from three layers of electrically-conductive material.
8. The integrated circuit of claim 1, wherein segments of electrically-conductive material within the at least one first area and segments of electrically-conductive material within the at least one second area comprise segments from two layers of electrically-conductive material.
9. The integrated circuit of claim 1, wherein each of a plurality of the nonvolatile transistors comprises a plurality of first nonvolatile transistors, the first nonvolatile transistors of a single nonvolatile transistor being disposed in at least two rows of transistors within the at least one first area.
10. The integrated circuit of claim 1, further comprising a plurality of isolation transistors disposed between adjacent nonvolatile transistors in the first area.
11. The integrated circuit of claim 9, wherein contacts to the nonvolatile transistors that allow electrical connections to corresponding select transistors are staggered.
12. A method of fabricating an integrated circuit, comprising:
forming a plurality of nonvolatile transistors in a first area of the integrated circuit;
forming a plurality of select transistors in a second area of the integrated circuit and a plurality of transistors in a third area; and
forming electrical interconnections between nonvolatile transistors in the first area and select transistors in the second area so as to form a plurality of programmable logic device (PLD) cells, each of a plurality of PLD cells comprising a nonvolatile transistor connected in series with a distinct select transistor, to electrically connect transistors in the third area with each other to form combinatorial logic circuitry; and to electrically connect the PLD cells to transistors in the third area.
13. The method of claim 12, further comprising:
forming an array of nonvolatile transistors in a fourth area of the integrated circuit, the nonvolatile transistors in the first area and the nonvolatile transistors in the fourth area following the same set of layout design rules.
14. The method of claim 12, further comprising:
forming an array of nonvolatile transistors in a fourth area of the integrated circuit, the nonvolatile transistors in the first area and the nonvolatile transistors in the fourth area having substantially the same transistor architecture.
15. The method of claim 12, wherein the nonvolatile transistors are floating gate transistors.
16. The method of claim 12, wherein the nonvolatile transistors are flash memory transistors.
17. The method of claim 12, wherein the step of forming electrical interconnections comprises connecting a plurality of PLD cells in parallel between at least one bit line and at least one source line.
18. The method of claim 12, wherein the step of forming the nonvolatile transistors forms the nonvolatile transistors in a plurality of first areas, the step of forming the select transistors forms the select transistors in a plurality of second areas, each second area being adjacent a first area.
19. The method of claim 18, wherein the step of forming electrical interconnections connects nonvolatile transistors in each first area with select transistors in the second area adjacent thereto to form the PLD cells.
20. The method of claim 19, wherein the PLD cells from a first area and the select transistors in the second area adjacent thereto form a PLD block, the integrated circuit having an array of PLD blocks.
21. An integrated circuit, comprising:
programmable logic device (PLD), comprising:
a plurality of floating gate transistors disposed in at least one first area of a semiconductor substrate;
a plurality of field effect transistors disposed in at least one second area of the semiconductor substrate; and
a plurality of layers of electrically conductive material disposed over the semiconductor substrate and electrically connecting the floating gate transistors and the field effect transistors so as to form a plurality of PLD cells, each of the plurality of PLD cells comprising a floating gate transistor connected in series with at least one distinct field effect transistor, the plurality of PLD cells being connected between at least one source line and at least one bit line.
22. The integrated circuit of claim 21, wherein the PLD device further comprises a plurality of transistors in a third area of the semiconductor substrate, the layers of electrically conductive material connecting the transistors in the third area together so as to form combinatorial logic circuitry and connecting the at least one bit line to the combinatorial logic circuitry, the combinatorial logic circuitry generating at least one output signal of the PLD device.
23. The integrated circuit of claim 21, wherein the layers of electrically conductive material couple gate terminals of the field effect transistors to inputs of the PLD device.
24. The integrated circuit of claim 21, wherein the floating gate transistors are disposed in a plurality of first areas and the plurality of field effect transistors are disposed in a plurality of second areas, the layers of electrically conductive material forming PLD cells with the floating gate transistors in a first area with the field effect transistors in a second area adjacent the first area.
25. The integrated circuit of claim 24, wherein each pair of a first area and a corresponding second area adjacent thereto is replicated a plurality of times.
26. The integrated circuit of claim 21, further comprising a nonvolatile memory device having a plurality of nonvolatile memory cells, each of a plurality of nonvolatile memory cells including a floating gate transistor having substantially the same architecture as the floating gate transistors of the PLD device.
27. The integrated circuit of claim 21, further comprising a nonvolatile memory device having a plurality of nonvolatile memory cells, each of a plurality of nonvolatile memory cells including a floating gate transistor having a layout that conforms to the same set of design rules as the layout of the floating gate transistors of the PLD device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An educational tool for teaching students, comprising:
a tarp portion;
an inflatable portion being positioned on the tarp portion;
the inflatable portion including a first end section positioned on a first end of the inflatable portion;
a river section connected to the first end section;
a middle section connected to the river section;
a second end section connected to the middle section; and
wherein the river section is decorated as a river cascading down and includes a top river section and a bottom river section, and wherein the top river section is independently inflatable and deflatable with respect to the bottom river section to indicate a river eroding a riverbed.
2. An educational tool for teaching students as in claim 1, wherein the first end section includes a first contour portion.
3. An educational tool for teaching students as in claim 1, wherein the middle section includes a second contour portion.
4. An educational tool for teaching students as in claim 3, wherein the second end section includes a third contour portion to cooperate with the second contour portion.
5. An educational tool for teaching students as in claim 1, wherein the second end section includes a fourth contour portion.
6. An educational tool for teaching students as in claim 1, wherein the river section includes a pullout portion showing sediment examples, the pullout portion slideably extending from the bottom of the bottom river section atop the tarp portion.
7. An educational tool for teaching students as in claim 1, wherein the educational tool includes a tunnel baffle adapted to allow users to walk in a passageway of the tunnel baffle.
8. An educational tool for teaching students as in claim 7, wherein the tunnel baffle cooperates with the middle and second end section in order to form a classroom.
9. An educational tool for teaching students comprising:
an inflatable first end section; and
an inflatable river section decorated as a river cascading down adjacent the inflatable first end section, the river section having an inflatable top river section and an inflatable bottom river section, the top river section deflatable independent of the inflatable bottom river section to indicate a river eroding a riverbed.
10. The educational tool of claim 9, wherein the top river section further comprises a deflation valve.
11. The educational tool of claim 9, further comprising an inflatable second end section.
12. The educational tool of claim 11, wherein the first end section includes a first contour portion.
13. An educational tool for teaching students as in claim 12, further comprising wherein a middle section, the middle section includes a second contour portion.
14. An educational tool for teaching students as in claim 13, wherein the second end section includes a third contour portion to cooperate with the second contour portion.
15. An educational tool for teaching students as in claim 14, wherein the second end section includes a fourth contour portion.
16. An educational tool for teaching students as in claim 15, wherein the river section includes a pullout portion showing sediment examples, the pullout portion slideably extending from the bottom of the bottom river section atop a tarp portion.
17. An educational tool for teaching students as in claim 16, wherein the educational tool includes a tunnel baffle adapted to allow users to walk in a passageway of the tunnel baffle.
18. An educational tool for teaching students as in claim 17, wherein the tunnel baffle cooperates with the middle and second end section in order to form a classroom.

1. A device, comprising:
a transmitter configured to generate an excitation signal for a first node of a transducer during a transmitting phase, a second node of said transducer being coupled to a biasing voltage terminal;
a receiver including a charge amplifier having an input terminal and biased as a function of an amplifier biasing voltage; and
switching circuitry coupled to the amplifier biasing voltage and configured to:
generate a pre-charge biasing voltage based on the amplifier biasing voltage during a pre-charge phase;
couple the receiver to said first node during a receiving phase; and
decouple the receiver from said first node during the transmitting phase.
2. The device of claim 1, comprising:
decoupling circuitry coupled between an output terminal of said transmitter and said first node and configured to decouple the transmitter from said first node during the receiving phase; and
transmitter biasing circuitry coupled to said output terminal and configured to set a voltage of said output terminal to a reference voltage value during said receiving phase.
3. The device of claim 2 wherein said decoupling circuitry comprises a pair of diodes in antiparallel configuration, connected between said output terminal and said first node and biased during said receiving phase.
4. The device of claim 2 wherein said transmitter biasing circuitry comprises a switch and a high-impedance element, connected in series between said output terminal and a line set at said reference voltage, said switch being configured to open during said transmitting phase and to close during said receiving phase.
5. The device of claim 1 wherein said switching circuitry comprises an intermediate node and is configured to charge the intermediate node to the pre-charge biasing voltage during the pre-charge phase and to couple the amplifier input terminal to the intermediate node during the receiving phase.
6. The device of claim 5 wherein said switching circuitry comprises:
a first switch configured to selectively coupled the first node to the intermediate node;
a second switch configured to selectively couple the intermediate node to the input terminal of the charge amplifier;
a biasing-voltage generator coupled to the intermediate node and configured to generate the pre-charge biasing voltage based on said amplifier biasing voltage; and
a third switch coupled between a reference voltage terminal and the biasing-voltage generator and configured to selectively activate the biasing-voltage generator during the pre-charge phase.
7. The device of claim 6 wherein,
the receiver comprises a biasing-current generator coupled to the biasing voltage and configured to supply a biasing current, wherein the charge amplifier is configured to generate an operating voltage on the input terminal based on the biasing current; and
the biasing-voltage generator comprises: a pre-charge-current generator, which is coupled to the biasing generator and configured to supply a pre-charge current, wherein the biasing-voltage generator is configured to provide the pre-charge biasing voltage on the intermediate node based on the pre-charge current, said pre-charge biasing voltage having a pre-set relation with said operating voltage.
8. The device of claim 7 wherein,
said charge amplifier includes a first transistor coupled to the biasing-current generator to receive the biasing current and having a control terminal coupled to the input terminal, and a first aspect ratio; and
said biasing-voltage generator comprises a fourth switch coupled between the intermediate node and the pre-charge-current generator, and a second transistor, coupled to the pre-charge-current generator to receive the pre-charge current, which is mirrored with respect to the biasing current via a mirror ratio, the second transistor having a control terminal coupled to the intermediate node and a second aspect ratio, wherein the second aspect ratio is a multiple of the first aspect ratio, the multiple being a function of the mirror ratio.
9. The device of claim 1 wherein the charge amplifier includes a feedback capacitor coupled between an output terminal of the charge amplifier and the input terminal of the charge amplifier.
10. The device of claim 1 wherein the transmitter operates at a first voltage and the receiver operates at a second voltage, lower than the first voltage, and the switching circuitry is configured to protect the receiver stage from the first voltage in the transmitter stage.
11. The device of claim 1 wherein the biasing voltage terminal is configured to receive a voltage from an external source.
12. The device of claim 2 wherein said switching circuitry comprises an intermediate node and is configured to charge the intermediate node to the pre-charge biasing voltage during the pre-charge phase and to couple the amplifier input terminal to the intermediate node during the receiving phase.
13. A system, comprising:
an ultrasonic probe including a plurality of transducers arranged in an array and a corresponding plurality of transceiver circuits, each transceiver circuit having:
a transmitter configured to generate an excitation signal for a first node of a transducer during a transmitting phase, a second node of said transducer being coupled to a biasing voltage terminal;
a receiver including a charge amplifier having an input terminal and biased as a function of an amplifier biasing voltage; and
switching circuitry coupled to the amplifier biasing voltage and configured to:
generate a pre-charge biasing voltage based on the amplifier biasing voltage during a pre-charge phase;
couple the receiver to said first node during a receiving phase; and
decouple the receiver from said first node during the transmitting phase; and
a controller configured to the timing of the receiving and transmitting phases of each of said transceiver circuits.
14. The system of claim 13 wherein each transceiver circuit comprises:
decoupling circuitry coupled between an output terminal of the transmitter and the first node and configured to decouple the transmitter from the first node during the receiving phase of the respective transceiver; and
transmitter biasing circuitry coupled to the output terminal and configured to set a voltage of the output terminal to a reference voltage value during the receiving phase of the respective transceiver.
15. The system of claim 13 configured to perform at least one of ultrasonography and ultrasonic tomography.
16. A method, comprising:
transmitting an excitation signal of a transmitter to a first node of a transducer during a transmitting phase, a second node of said transducer being coupled to a biasing voltage terminal;
biasing a charge amplifier of a receiver as a function of an amplifier biasing voltage, the charge amplifier having an input terminal;
generating a pre-charge biasing voltage based on the amplifier biasing voltage during a pre-charge phase;
coupling the receiver to said first node during a receiving phase; and
decoupling the receiver from said first node during the transmitting phase.
17. The method of claim 16, comprising:
decoupling an output of the transmitter from said first node during the receiving phase; and
clamping a voltage of said output terminal to a reference voltage value during said receiving phase.
18. The method of claim 17 wherein said clamping comprises controlling a switch coupling said output terminal to a reference voltage line through a high-impedance element.
19. The method of claim 16, comprising charging an intermediate node to the pre-charge biasing voltage during the pre-charge phase and coupling the amplifier input terminal to the intermediate node during the receiving phase.
20. The method of claim 18, comprising charging an intermediate node to the pre-charge biasing voltage during the pre-charge phase and coupling the amplifier input terminal to the intermediate node during the receiving phase.
21. A non-transitory computer-readable medium having contents which configured a transducer system to perform a method, the method comprising:
transmitting an excitation signal of a transmitter to a first node of a transducer of the transducer system during a transmitting phase, a second node of said transducer being coupled to a biasing voltage terminal;
biasing a charge amplifier of a receiver as a function of an amplifier biasing voltage;
generating a pre-charge biasing voltage based on the amplifier biasing voltage during a pre-charge phase;
coupling the receiver to said first node during a receiving phase; and
decoupling the receiver from said first node during the transmitting phase.
22. The medium of claim 21 wherein the method comprises:
decoupling an output of the transmitter from said first node during the receiving phase; and
clamping a voltage of said output terminal to a reference voltage value during said receiving phase.
23. The medium of claim 21 wherein the method comprises charging an intermediate node to the pre-charge biasing voltage during the pre-charge phase and coupling an input terminal of the amplifier to the intermediate node during the receiving phase.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A battery cell interconnect and voltage sensing assembly, comprising:
a frame member having a first side and a second side, the frame member further having a generally rectangular ring-shaped peripheral wall having first, second, third and fourth wall portions, the first and second wall portions being substantially parallel to one another and being spaced apart from one another, the third and fourth wall portions being substantially parallel to one another and being spaced apart from one another;
the frame member further having a central plate portion coupled between the first and second wall portions, the central plate portion defining a first space between the central plate portion and the third wall portion, the central plate portion further defining a second space between the central plate portion and the fourth wall portion;
the frame member further having a first support member disposed between the third wall portion and the central plate portion such that first and second gaps are formed adjacent to opposite edges of the first support member;
a first electrical interconnect member coupled to the first support member on the first side of the frame member, the first electrical interconnect member being configured to be electrically coupled to a first electrical terminal of a first battery cell extending through the first gap, the first electrical interconnect member having a first voltage sensing tab that extends through a first aperture in the central plate portion; a circuit board disposed proximate to the second side of the frame member on at least one coupling tab extending from the central plate portion, the circuit board having first and second sides, the first side of the circuit board being disposed proximate to the central plate portion and the second side of the circuit board being disposed opposite to the first side of the circuit board; and
an electrical connector disposed on the circuit board and extending through a second aperture of the central plate portion, the circuit board having a first electrical trace coupled between the first voltage sensing tab and the electrical connector; and
an encapsulation portion that is bonded to and covers the second side of the circuit board.
2. The battery cell interconnect and voltage sensing assembly of claim 1, wherein the encapsulation portion further bonds to and covers the first side of the circuit board disposed proximate to the central plate portion.
3. The battery cell interconnect and voltage sensing assembly of claim 1, wherein the frame member further includes a second support member disposed between the fourth wall portion and the central plate portion such that third and fourth gaps are formed adjacent to opposite edges of the second support member.
4. The battery cell interconnect and voltage sensing assembly of claim 3, further comprising a second electrical interconnect member coupled to the second support member on the first side of the frame member, the second electrical interconnect member being configured to be electrically coupled to a second electrical terminal of the first battery cell extending through the third gap, the second electrical interconnect member being further configured to be electrically coupled to a third electrical terminal of a second battery cell extending through the fourth gap, such that the first and second electrical interconnect members electrically couple the first battery cell to the second battery cell, the second electrical interconnect member having a second voltage sensing tab that extends through a third aperture in the central plate portion.
5. The battery cell interconnect and voltage sensing assembly of claim 4, wherein the circuit board includes a second electrical trace coupled between the second voltage sensing tab and the electrical connector.
6. The battery cell interconnect and voltage sensing assembly of claim 3, wherein the first support member includes at least one attachment tab that extends through an aperture in the first electrical interconnect member.
7. The battery cell interconnect and voltage sensing assembly of claim 6, wherein the second support member includes at least one attachment tab that extends through an aperture in the second electrical interconnect member.
8. The battery cell interconnect and voltage sensing assembly of claim 1, wherein the encapsulation portion is constructed of thermoplastic polyamide.
9. A method for manufacturing a battery cell interconnect and voltage sensing assembly, comprising:
providing a frame member having a first side and a second side, the frame member further having a generally rectangular ring-shaped peripheral wall having first, second, third and fourth wall portions, the first and second wall portions being substantially parallel to one another and being spaced apart from one another, the third and fourth wall portions being substantially parallel to one another and being spaced apart from one another; the frame member further having a central plate portion coupled between the first and second wall portions, the central plate portion defining a first space between the central plate portion and the third wall portion, the central plate portion further defining a second space between the central plate portion and the fourth wall portion; the frame member further having a first support member disposed between the third wall portion and the central plate portion such that first and second gaps are formed adjacent to opposite edges of the first support member;
disposing a circuit board proximate to the second side of the frame member on at least one coupling tab extending from the central plate portion, the circuit board having first and second sides, the first side of the circuit board being disposed proximate to the central plate portion and the second side of the circuit board being disposed opposite to the first side of the circuit board, an electrical connector being disposed on the circuit board that extends through a second aperture of the central plate portion, the circuit board having a first electrical trace;
coupling a first electrical interconnect member to the first support member on the first side of the frame member, the first electrical interconnect member having a first voltage sensing tab that extends through a first aperture in the central plate portion;
soldering the first voltage sensing tab to the first electrical trace on the circuit board, the first electrical trace extending between the first voltage sensing tab and the electrical connector; and
applying an encapsulation portion to the second side of the circuit board that bonds to and covers the second side of the circuit board.
10. The method of claim 9, wherein the encapsulation portion further covers the first side of the circuit board proximate to the central plate portion.
11. The method of claim 9, wherein the frame member further includes a second support member disposed between the fourth wall portion and the central plate portion such that third and fourth gaps are formed adjacent to opposite edges of the second support member.
12. The method of claim 11, further comprising coupling a second electrical interconnect member to the second support member on the first side of the frame member, the second electrical interconnect member having a second voltage sensing tab that extends through a third aperture in the central plate portion.
13. The method of claim 12, further comprising soldering the second voltage sensing tab to a second electrical trace on the circuit board, the second electrical trace extending between the second voltage sensing tab and the electrical connector.
14. The method of claim 9, wherein the encapsulation portion is constructed of thermoplastic polyamide.