Author: claimsbot

1. A voltage converter comprising
a switching device in series with an input terminal for controlling an output voltage of said voltage converter,
means for developing a voltage due to input current from said input terminal to said voltage converter, and
means for controlling said switching device to provide a desired voltage droop in said output voltage of said voltage converter such that said output voltage of said voltage converter is adaptively positioned above a minimum allowed voltage by an amount sufficient to accommodate transients, overshoot and ringing at maximum load and below a maximum allowed voltage by an amount sufficient to accommodate transients, overshoot and ringing at low load, said means for controlling said switching device being responsive to both said output voltage of said voltage converter and said voltage developed due to said input current.
2. The voltage converter as recited in claim 1, wherein said means for developing a voltage due to input current to said voltage converter comprises
a resistor in series with said switching device and an output current path, said resistor being conductive when said switching device is conductive,
a filter for smoothing a voltage developed across said resistor when said switching device is conductive, and
wherein said means for controlling said switching device is responsive to said output voltage of said voltage converter and a voltage developed across said resistor.
3. The voltage converter as recited in claim 2, wherein said resistor is connected in a current input path to said voltage converter from a voltage source.
4. The voltage converter as recited in claim 2, wherein said resistor is connected in a current return path from said voltage converter to a voltage source.
5. The voltage converter as recited in claim 2, wherein said desired voltage droop corresponds to a resistance, R0, and a resistance value of said resistor, Rs, is approximately (\u03b7VinV0)*R0 where Vin and V0 are the input and output voltages of said voltage converter and \u03b7 is the approximate full load efficiency of said voltage converter.
6. The voltage converter as recited in claim 1, wherein said means for controlling said switching device includes a pulse width modulator.
7. The voltage converter as recited in claim 2, wherein said filter includes a capacitor.
8. The voltage converter as recited in claim 7, wherein said capacitor is connected in parallel with said resistor.
9. The voltage converter as recited in claim 2, wherein said filter comprises a capacitor connected as an input capacitor for said voltage converter.
10. The voltage converter as recited in claim 2, wherein a time constant of said filter in combination with said resistor is four to ten times the switching cycle period of said switching device.
11. The voltage converter as recited in claim 1, further including a feed-forward circuit for compensating for variation in input voltage to said voltage converter.
12. The voltage converter as recited in claim 1, further including a remote voltage sensing and correction arrangement.
13. The voltage converter as recited in claim 12, further including a remote ground sensing and correction arrangement.
14. The voltage converter as recited in claim 1, further including a remote ground sensing and correction arrangement.
15. The voltage converter as recited in claim 1, further including a voltage filter or regulator or further voltage converter stage.
16. A method for passively producing voltage droop with increasing load in a voltage converter, said method comprising steps of
interrupting input current from a voltage source to control an output voltage of said voltage converter,
controlling a switch to supply current in said voltage converter when said input current is interrupted,
developing a voltage due to input current to said voltage converter from an input terminal of said voltage converter, and
controlling said interruption step to provide a desired voltage droop in said output voltage of said voltage converter such that said output voltage of said voltage converter is adaptively positioned above a minimum allowed voltage by an amount sufficient to accommodate transients, overshoot and ringing at maximum load and below a maximum allowed voltage by an amount sufficient to accommodate transients, overshoot and ringing at low load, said controlling step being responsive to both said output voltage of said voltage converter and said voltage developed due to said input current.
17. The method as recited in claim 16, including the further step of
compensating for variation in voltage of said voltage source.
18. The method as recited in claim 16, further comprising the step of
remotely sensing voltage or ground at a remote connection of an output of said voltage converter.
19. The method as recited on claim 16, including the further step of
filtering, regulating or voltage converting said output voltage of said voltage converter.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A process for separating a product from at least one multicomponent feed by simulated countercurrent adsorptive separation in a simulated moving-bed adsorption apparatus comprising at least one rotary valve and plural sieve chambers, characterized by the steps of: (a) introducing a first multicomponent feed, comprising at least one desired product, through at least one fluid communication conduit into said apparatus; (b) withdrawing a first multicomponent extract, comprising at least one desired product, through at least one fluid communication conduit out of said apparatus; (c) flushing said at least one conduit in step (a) with at least one initial flushing medium, whereby residue of said first multicomponent feed is flushed from the at least one conduit in step (a) into said apparatus by the at least one initial flushing medium, so as to produce a first flush output comprising said at least one initial flushing medium and said residue of said first multicomponent feed; (d) flushing at least one conduit in step (b) with at least one initial flushing medium, whereby residue of said first multicomponent extract is flushed form the at least one conduit in step (b) out of said apparatus by the at least one initial flushing medium, so as to produce a first flush output comprising said at least one initial flush medium and said residue of said first multicomponent extract; (e) after step (c) flushing said at least one fluid communication conduit with a second flushing medium, with the proviso that said second flushing medium comprises said first flush output from step (d).
2. The process of claim 1, further characterized by not having a step of distillation of said flush output before it is used as said second flushing medium.
3. The process of claim 1, wherein said final extract comprises at least 99.7 wt % paraxylene, based on the total amount of C8 aromatic hydrocarbons in said final extract.
4. The process of claim 1, wherein said first multicomponent feed has a concentration of paraxylene of greater than or equal to the thermodynamic equilibrium concentration of paraxylene in a mixture of C8 aromatic hydrocarbons.
5. The process of claim 1, wherein the initial flushing medium has a concentration of paraxylene greater than the concentration of xylene in said first multicomponent feed.
6. The process of claim 1, wherein the volume of the second flushing medium is from 110 to 150 vol % of the volume of the bedline flushed.

1. An image processing apparatus for receiving a plurality of images, saving the plurality of images, and executing image processing, said image forming apparatus, comprising:
an identifying unit for identifying a first image and a second image from the plurality of the images;
an image recognizing unit for recognizing information on the second image from the first image; and
a processing setting unit for setting processing for the second image based on recognition at the image recognition unit,
wherein the images are processed based on the setting set at the processing setting unit.
2. The image processing apparatus according to claim 1, wherein the processing executed at the image recognizing unit includes a letter recognition processing.
3. The image processing apparatus according to claim 1, wherein the processing executed at the image recognizing unit includes a mark recognition processing.
4. The image processing apparatus according to claim 1, wherein the processing executed at the image recognizing unit includes a bar code recognition processing.
5. The image processing apparatus according to claim 1, wherein the processing set at the processing setting unit is a program selecting a plurality of processes.
6. The image processing apparatus according to claim 1, wherein the processing set at the processing setting unit is an approving processing.
7. The image processing apparatus according to claim 1, wherein the identifying unit reads the setting information according to a feature of an arraignment of a line or lines in a page.
8. The image processing apparatus according to claim 1, wherein the identifying unit reads the setting information by recognizing a combination of dots forming a line or lines in a page as a code.
9. The image processing apparatus according to claim 1, wherein the identifying unit reads the setting information by recognizing a letter formed at a prescribed position in a page.
10. The image processing apparatus according to claim 1, wherein the identifying unit reads the setting information by recognizing a bar code formed at a prescribed position in a page.
11. The image processing apparatus according to claim 1, wherein the identifying unit reads the setting information by recognizing a background pattern formed in a page.
12. The image processing apparatus according to claim 1, further comprising an image reading unit for reading plural images from an original document, wherein the plural images are received through the image reading unit.
13. The image processing apparatus according to claim 1, further comprising an inputting unit for inputting image data produced at an external apparatus, wherein the plural images are received through the image reading unit.
14. An image processing method for receiving, saving, and processing plural images, said image processing method comprising the steps of:
identifying a first image and a second image among the plural images;
recognizing information regarding the second image from the first image;
setting a processing for the second image based on recognition made at the recognizing step; and
processing the images based on the setting set at the setting step.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A static random access memory (\u201cSRAM\u201d), comprising:
a plurality of cells arranged in an SRAM having a plurality of columns; and a voltage control circuit operable to temporarily reduce a voltage at which power is supplied to cells belonging to a selected column of said SRAM, said selected column being selected during a write operation in which a bit is written to one of said cells belonging to said selected column, wherein said voltage control circuit includes a first p-type field effect transistor (\u201cPFET\u201d) and a second PFET, said first PFET having a conduction path connected between a power supply and said cells belonging to said selected column, said second PFET having a conduction path connected between said cells belonging to said selected column and ground, wherein said first PFET has a gate terminal directly connected to ground.
2. The SRAM as claimed in claim 1, wherein said second PFET is operable in response to selection input applied to a gate terminal of said second PFET when said column is selected.
3. An SRAM as claimed in claim 2, further comprising a third PFET having a conduction path connected in parallel with said first PFET.
4. An SRAM as claimed in claimed in claim 3, wherein said third PFET is operable to conduct substantially greater current than said first PFET.
5. An SRAM as claimed in claim 4, wherein said selection input is a first selection input, said third PFET being operable to present greater resistance in response to a second selection input applied to a gate terminal of said third PFET.
6. An SRAM as claimed in claim 5, wherein said second PFET is operable in response to said first selection input transitioning towards a low voltage level.
7. A static random access memory (\u201cSRAM\u201d), comprising:
a plurality of SRAM cells arranged in an array including a plurality of columns; and a plurality of voltage control circuits corresponding to respective ones of said columns, each of said plurality of voltage control circuits coupled to a power supply and being operable to temporarily reduce a voltage at which power is supplied to cells belonging to a column selected to be written from said columns, wherein each said voltage control circuit includes a first p-type field effect transistor (\u201cPFET\u201d) and a second PFET, said first PFET having a conduction path connected between the power supply and said cells belonging to said selected column, said second PFET having a conduction path connected between said cells belonging to said selected column and ground, wherein said first PFET has a gate terminal directly connected to ground.
8. An SRAM as claimed in claim 7, wherein said second PFET is operated by a selection input applied to a gate terminal of said second PFET when said column is selected.
9. An SRAM as claimed in claim 8, further comprising a third PFET having a conduction path connected in parallel with said first PFET.
10. An SRAM as claimed in claimed in claim 9, wherein said third PFET is operable to conduct substantially greater current than said first PFET.
11. An SRAM as claimed in claim 10, wherein said selection input is a first selection input, said third PFET being operable to present greater resistance in response to a second selection input applied to a gate terminal of said third PFET.
12. An SRAM as claimed in claim 11, wherein said second PFET is operable in response to the first selection input transitioning towards a low voltage level.
13. A static random access memory (\u201cSRAM\u201d), comprising:
a plurality of cells arranged in an SRAM having a plurality of columns; and
a voltage control circuit operable to temporarily raise a voltage level of a low voltage reference to cells belonging to a column selected for writing from said plurality of columns, wherein said voltage control circuit includes a first n-type field effect transistor (\u201cNFET\u201d) and a second NFET, said first NFET having a conduction path connected between ground and the low voltage reference, said second NFET having a conduction path connected between a power supply and the low voltage reference.
14. The SRAM as claimed in claim 13, wherein said first NFET has a gate terminal connected to said power supply.
15. The SRAM as claimed in claim 13, wherein said second NFET is operable in response to selection input applied to a gate terminal of said second NFET when said column is selected.
16. An SRAM as claimed in claim 15, further comprising a third NFET having a conduction path connected in parallel with said first NFET.
17. An SRAM as claimed in claimed in claim 16, wherein said third NFET is operable to conduct substantially greater current than said first NFET.
18. An SRAM as claimed in claim 17, wherein said selection input is a first selection input, said third NFET being operable to present greater resistance in response to a second selection input applied to a gate terminal of said third NFET.
19. An SRAM as claimed in claim 18, wherein said second NFET is operable to raise the voltage in response to said first selection input transitioning towards a high voltage level.