Author: claimsbot

1. An eyeglass device, comprising:
a lens unit; and
a pair of temple pieces connected to said lens unit, each of said temple pieces including a rigid upper portion and a soft lower portion, said rigid upper portion having a rigid front end connected to said lens unit, and a rigid rear end, said soft lower portion having a front soft section disposed below and connected to said rigid front end, a rear soft section connected to said rigid rear end, and an intermediate soft section disposed between said front and rear soft sections and below said rigid upper portion, said intermediate soft section and said rigid upper portion cooperatively defining an elongate gap therebetween, said soft lower portion having a bottom abutment face extending from said front soft section to said rear soft section for contacting an ear of a user.
2. The eyeglass device of claim 1, wherein said rigid upper portion has a rigid main segment having said rigid front end, and a rigid tail segment having said rigid rear end and including a projection, said rear soft section enclosing said rigid tail segment, said projection extending outwardly of said rear soft section.
3. The eyeglass device of claim 2, wherein said rigid main segment of said rigid upper portion of each of said temple pieces further has a bottom surface, an inner surface facing the other one of said temple pieces, an indented part formed in said inner surface adjacent to said bottom surface, a non-indented part that is formed in said inner surface and that has front, lateral and rear edges bounding said indented part, and a tongue protruding frontwardly into said indented part from said rear edge of said non-indented part, and a groove formed between said tongue and said lateral edge of said non-intended part and defined by a substantially V-shaped wall, said front soft section enclosing said bottom surface and said indented part and having a finger portion engaging said groove.
4. The eyeglass device of claim 2, wherein said rigid main segment of said rigid upper portion of each of said temple pieces further has a bottom surface, an inner surface facing the other one of said temple pieces, an indented part formed in said inner surface adjacent to said bottom surface, a non-indented part that is formed in said inner surface and that has front, lateral and rear edges bounding said indented part, and a protrusion formed in and protruding from said indented part, said front soft section enclosing said bottom surface, said indented part and said protrusion.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A process compensation circuit for an inverting element of a CMOS device, comprising:
a duplicate inverting element connected in parallel with the inverting element of the CMOS device; and
an upside-down inverter stage having an input thereto connected to the output of said duplicate inverting element, and an output thereof connected to the output of said inverting element of the CMOS device;
wherein said upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.
2. The process compensation circuit of claim 1, wherein said upside-down inverter stage further comprises:
an NFET having a gate coupled to the output of said duplicate inverting element, said NFET having a source coupled to a logic high voltage supply terminal of the CMOS device;
a PFET having a gate coupled to the output of said duplicate inverting element, said PFET having a source coupled to a logic low voltage supply terminal of the CMOS device; and
a drain of said NFET coupled to a drain of said PFET, which defines said output of said upside-down inverter stage.
3. The process compensation circuit of claim 2, wherein said NFET and said PFET of said upside-down inverter stage are formed at a size about 10 times smaller with respect to NFET and PFET devices of the inverting element of the CMOS device.
4. A process compensation device for a CMOS receiver having a NAND stage and an inverter stage; comprising:
a duplicate NAND gate stage connected in parallel with the NAND gate stage of the CMOS receiver; and
an upside-down inverter stage having an input connected to the output of said duplicate NAND gate stage, and an output connected to the output of said NAND stage of the CMOS receiver;
wherein said upside-down inverter stage is configured to counteract a delayed logic transition of the output of the NAND gate stage of the CMOS device receiver in the event of a process skew between NFET and PFET devices.
5. The process compensation device of claim 4, wherein said upside-down inverter stage further comprises:
an NFET having a gate coupled to the output of said duplicate NAND stage, said NFET having a source coupled to a first logic high voltage supply terminal of the CMOS receiver;
a PFET having a gate coupled to the output of said duplicate NAND stage, said PFET having a source coupled to a logic low voltage supply terminal of the CMOS receiver; and
a drain of said NFET coupled to a drain of said PFET, which defines said output of said upside-down inverter stage.
6. The compensation circuit of claim 5, wherein said NFET and said PFET of said upside-down inverter stage are formed at a size about 10 times smaller with respect to NFET and PFET devices of the NAND stage of the CMOS receiver.
7. A CMOS receiver device, comprising:
an input NAND stage operating at a first voltage level, said input NAND stage having a data input and an enable input connected thereto;
an output inverter stage operating at a second voltage level, said output inverter stage having an input connected to an output of said input NAND stage, which defines an intermediate node;
a hysteresis latch coupled to said intermediate node, said hysteresis latch comprising a pair of inverter stages; and
a process compensation circuit coupled in parallel with said input NAND stage, said process compensation circuit further comprising a duplicate NAND stage receiving said data input and said enable input, and an upside-down inverter stage having an input coupled to an output of said duplicate NAND stage and an output connected to said intermediate node;
wherein said upside-down inverter stage is configured to counteract a delayed logic transition of said output of said input NAND stage in the event of a process skew between NFET and PFET devices.
8. The CMOS receiver device of claim 7, wherein said upside-down inverter stage further comprises:
an NFET having a gate coupled to the output of said duplicate NAND stage, said NFET having a source coupled to a logic high voltage supply terminal of the CMOS receiver corresponding to said first voltage level;
a PFET having a gate coupled to the output of said duplicate NAND stage, said PFET having a source coupled to a logic low voltage supply terminal of the CMOS receiver; and
a drain of said NFET coupled to a drain of said PFET, which defines said output of said upside-down inverter stage.
9. The CMOS receiver device of claim 8, wherein said NFET and said PFET of said upside-down inverter stage are formed at a size about 10 times smaller with respect to NFET and PFET devices of said input NAND stage.

1. A device for feeding printed products to a subsequent processing machine having a working cycle and a cyclic infeed system, comprising:
a continuous-drive accumulating conveyor for the products, having upstream and downstream ends;
a product arrestor arranged at the downstream end of the accumulating conveyor;
a timed trigger for the arrestor to release individual ones of the arrested products;
a continuous-drive onward conveyor which receives and transports each individual product by friction through a conveyance region to a defined transfer position from which further transport of the product is taken over by the cyclic infeed system of the subsequent processing machine;
a control sensor, arranged at a control position in the conveyance region of the onward conveyor, for generating a signal upon detecting the leading edge of each product at said control position along the conveying region; and
an infeed control device responsive to the sensor signal for triggering the arrestor to release individual product, according to a control logic wherein,
a first transport time interval is the measured time interval from the moment the detected product produces the sensor signal at said control position to the moment the printed product is taken over by the infeed system at the transfer position,
a second transport time interval is a known time interval for the onward conveyor to translate from the control position of the sensor to the transfer position where the printed product is taken over by the infeed system, and
the timing for triggering of the arrestor to release individual products subsequent to a leading product is adjusted by the time difference between said first and second time intervals associated with said leading product.
2. The device according to claim 1, wherein the sensor is arranged in the downstream end of the conveyance region of the onward conveyor.
3. The device according to claim 1, wherein the control position of the sensor is adjustable along the direction of conveyance of the products.
4. The device according to claim 1, wherein
the onward conveyor delivers the products to the transfer position in a flat orientation, with a spine or fore edge cut of the product defining said leading edge, and
the infeed system of the subsequent processing machine is a star feeder which rotates intermittently and cyclically, and has lift surfaces that lift the products from the onward conveyor at the transfer position, reorient the products, and place the products onto the spine or fore edge cut, for onward transfer to a transport system of the subsequent processing machine.
5. The device according to claim 1, wherein the onward conveyor comprises a plurality of conveyor belts, arranged parallel in relation to each other.
6. The device according claim 1, wherein a retaining device is arranged at the downstream end of the accumulating conveyor for temporarily preventing a second product in a queue of products from being conveyed thereon and thereby generating a conveyance gap during onward conveying of said leading product.
7. The device according to claim 1, wherein the control logic includes a triggering reset upon restart of the machine following a machine stop, whereby the time of triggering of the arrestor is reset based on the time difference between said first and second time intervals of the leading product fed in upon restart of the machine.
8. The device according to claim 2, wherein the position of the sensor is adjustable along the direction of conveyance of the products.
9. The device according to claim 2, wherein
the onward conveyor delivers the products to the transfer position in a flat orientation, with a spine or fore edge cut of the product defining said leading edge, and
the infeed system of the subsequent processing machine is a star feeder which rotates intermittently and cyclically, and has lift surfaces that lift the printed products from the onward conveyor at the transfer position, reorient the products, and place the products onto the spine or fore edge cut, for onward transfer to a transport system of the subsequent processing machine.
10. The device according to claim 3, wherein
the onward conveyor delivers the products to the transfer position in a flat orientation, with a spine or fore edge cut of the product defining said leading edge, and
the infeed system of the subsequent processing machine is a star feeder which rotates intermittently and cyclically, and has lift surfaces that lift the printed products from the onward conveyor at the transfer position, reorient the products, and place the products onto the spine or fore edge cut, for onward transfer to a transport system of the subsequent processing machine.
11. The device according to claim 4, wherein the onward conveyor comprises a plurality of conveyor belts, arranged parallel in relation to each other.
12. The device of claim 4, wherein a retaining device is arranged at the downstream end of the accumulating conveyor for temporarily preventing a second product in a queue of products from being conveyed thereon and thereby generating a conveyance gap during onward conveying of said leading product.
13. The device of claim 4, wherein the control logic includes a triggering reset upon restart of the machine following a machine stop, whereby the time of triggering of the arrestor is reset based on the time difference between said first and second time intervals of the leading product fed in upon restart of the machine.
14. The device of claim 10, wherein the onward conveyor comprises a plurality of conveyor belts, arranged parallel in relation to each other.
15. The device of claim 10, wherein a retaining device is arranged at the downstream end of the accumulating conveyor for temporarily preventing a second product in a queue of products from being conveyed thereon and thereby generating a conveyance gap during onward conveying of said leading printed product.
16. The device of claim 10, wherein the control logic includes a triggering reset upon restart of the machine following a machine stop, whereby the time of triggering of the arrestor is reset based on the time difference between said first and second time intervals of the leading product fed in upon restart of the machine.
17. The device of claim 15, wherein the control logic includes a triggering reset upon restart of the machine following a machine stop, whereby the time of triggering of the arrestor is reset based on the time difference between said first and second time intervals of the leading product fed in upon restart of the machine.
18. The device of claim 1, wherein the control logic controls the timing for the triggering of the arrestor acting on the arrested products on the accumulating conveyor based on a determination of minimizing the time difference between said first and second time intervals associated with said leading product.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for compensating a frequency offset in processing a received radio signal, wherein the receiving and the processing comprises the steps of
receiving a radio signal having a carrier frequency from a radio channel,
producing a local oscillator signal, wherein there is a frequency offset between the carrier frequency of the received radio signal and the frequency of the local oscillator signal,
mixing the received radio signal with the local oscillator signal for producing a baseband signal,
converting the baseband signal into digital samples
producing a radio channel estimation data,
correcting the phase of the baseband signal on the basis of the channel estimation data,
characterized in that the method further comprises the steps of:
detecting phases from successive channel estimation data,
generating a complex phasor on the basis of said detected phases, and
multiplying the baseband signal with said complex phasor for reducing the frequency offset of the baseband signal.
2. A method according to claim 1, characterized in that the received signal is a spread spectrum signal and the method further comprises the step of despreading the received wideband signal to form a narrowband signal.
3. A method according to claim 2, characterized in that the step of multiplying the baseband signal with said complex phasor is performed to the wideband signal prior to despreading.
4. A method according to claim 2, characterized in that the received signal is a spread spectrum signal and the step of multiplying the baseband signal with said complex phasor is performed to the narrowband signal after despreading.
5. A method according to claim 1, characterized in that the radio channel estimate data is made on the basis of the baseband signal that has been multiplied with a complex phasor for frequency offset correction.
6. A method according to claim 5, characterized in that before the step of detecting phases the method comprises a step of forming a derivative signal on the basis of successive channel estimate data, and a step of low pass filtering the derivated data.
7. A method according to claim 5, characterized in that the after the step of detecting phases the method comprises a step of forming a phase derivative signal on the basis of successive detected phase values, and a step of low pass filtering the derivated data.
8. A method according to claim 5, characterized in that before the step of generating a complex phasor on the basis of said detected phases the method further comprises a step of integrating.
9. A method according to claim 1, characterized in that the method further comprises the steps of
producing a first channel estimation data,
detecting phases from successive first channel estimation data,
generating a complex phasor on the basis of said detected phases from successive first channel estimation data,
multiplying the baseband signal with the complex phasor for correcting the frequency offset,
producing a second channel estimation data on the basis of the frequency corrected signal, and
multiplying an uncorrected baseband signal with the second channel estimate data for forming a corrected output signal.
10. A method according to claim 9, characterized in that the after the step of detecting phases the method comprises a step of forming a phase derivative signal on the basis of successive detected phase values.
11. A method according to claim 9, characterized in that the before the step of detecting phases the method comprises a step of forming a phase derivative signal on the basis of successive channel estimate data.
12. A method according to claim 9, characterized in that the processing the baseband signal is made for at least two multipath components of the received signal, and the process of reducing the frequency offset is based on averaging at least one signal from the processing of the different multipath components.
13. A method according to claim 12, characterized in that the complex phasor is generated on the basis of frequency offset estimate values from at least two multipath components.
14. An arrangement for receiving a radio signal and compensating a frequency offset in processing the received radio signal, wherein the arrangement comprises
means for receiving a radio signal having a carrier frequency from a radio channel,
means for producing a local oscillator signal, wherein there is a frequency offset between the carrier frequency of the received radio signal and the frequency of the local oscillator signal,
means for mixing the received radio signal with the local oscillator signal for producing a baseband signal,
means for converting the baseband signal into digital samples,
means for producing a radio channel estimation data,
means for correcting the phase of the baseband signal on the basis of the channel estimation data,
characterized in that the arrangement further comprises:
means for detecting phases from successive channel estimation data,
means for generating a complex phasor on the basis of said detected phases, and
means for multiplying the baseband signal with said complex phasor for reducing the frequency offset of the baseband signal.
15. An arrangement according to claim 14, characterized in that the received signal is a spread spectrum signal and the arrangement further comprises means for despreading the received wideband signal to form a narrowband signal.
16. An arrangement according to claim 15, characterized in that the arrangement comprises means for multiplying a wideband baseband signal with said complex phasor with the output coupled to the input of said despreading means.
17. An arrangement according to claim 15, characterized in that the arrangement comprises means for multiplying a narrowband baseband signal with said complex phasor with the input coupled to the output of the despreading means.
18. An arrangement according to claim 14, characterized in that input of the means for forming the radio channel estimate data is coupled to the output of said means for multiplying the baseband signal with said complex phasor for reducing the frequency offset of the baseband signal.
19. An arrangement according to claim 14, characterized in that it comprises a derivator that is coupled to the output of said channel estimator and a low pass filter which has an input coupled to the output of said derivator and an output coupled to the input of said means for detecting phases.
20. An arrangement according to claim 14, characterized in that it comprises a derivator that is coupled to the output of said means for detecting phases, and a low pass filter which has an input coupled to the output of said derivator and an output coupled to the input of said means for forming a complex phasor.
21. An arrangement according to claim 14, characterized in comprises an integrator for integrating the phase detected data, to form an error frequency value for the input of the means for forming a complex phasor.
22. An arrangement according to claim 14, characterized in that the arrangement further comprises
means for producing a first channel estimation data,
means for detecting phases from successive first channel estimation data,
means for generating a complex phasor on the basis of said detected phases from successive first channel estimation data,
means for multiplying the baseband signal with the complex phasor for correcting the frequency offset,
means for producing a second channel estimation data on the basis of the frequency corrected signal, and
means for multiplying an uncorrected baseband signal with the second channel estimate data for forming a corrected output signal.
23. An arrangement according to claim 14, characterized in that it comprises a derivator for forming a phase derivative signal on the basis of successive detected phase values.
24. An arrangement according to claim 14, characterized in that it comprises a derivator with its input coupled to the output of said channel estimation means and for forming a derivative signal on the channel estimation data prior to detecting phases.
25. An arrangement according to claim 15, characterized in that it comprises at least two rake fingers, and means for averaging at least one corresponding signal from the at least two rake fingers for the process of reducing the frequency offset.
26. A method according to claim 15, characterized in that it comprises means for generating the complex phasor on the basis of frequency offset estimate values ({circumflex over (f)}e) from the at least two rake fingers.
27. A mobile station including an arrangement for receiving a radio signal and compensating a frequency offset in processing the received radio signal, wherein the arrangement comprises
means for receiving a radio signal having a carrier frequency from a radio channel,
means for producing a local oscillator signal, wherein there is a frequency offset between the carrier frequency of the received radio signal and the frequency of the local oscillator signal,
means for mixing the received radio signal with the local oscillator signal for producing a baseband signal,
means for converting the baseband signal into digital samples,
means for producing a radio channel estimation data,
means for correcting the phase of the baseband signal on the basis of the channel estimation data,
characterized in that the arrangement further comprises:
means for detecting phases from successive channel estimation data,
means for generating a complex phasor on the basis of said detected phases, and
means for multiplying the baseband signal with said complex phasor for reducing the frequency offset of the baseband signal.
28. A base station including an arrangement for receiving a radio signal and compensating a frequency offset in processing the received radio signal, wherein the arrangement comprises
means for receiving a radio signal having a carrier frequency from a radio channel,
means for producing a local oscillator signal, wherein there is a frequency offset between the carrier frequency of the received radio signal and the frequency of the local oscillator signal,
means for mixing the received radio signal with the local oscillator signal for producing a baseband signal,
means for converting the baseband signal into digital samples,
means for producing a radio channel estimation data,
means for correcting the phase of the baseband signal on the basis of the channel estimation data,
characterized in that the arrangement further comprises:
means for detecting phases from successive channel estimation data,
means for generating a complex phasor on the basis of said detected phases, and
means for multiplying the baseband signal with said complex phasor for reducing the frequency offset of the baseband signal.