Author: claimsbot

1. A split gate field effect transistor device, comprising:
a split gate structure having a trench, a gate electrode and a source electrode;
first poly layer a disposed within the trench connected to the source electrode;
a second poly layer connected to the gate electrode, wherein the first poly layer and the second poly layer are independent.
2. The device of claim 1, further comprising:
a gate contact connecting the second poly layer; and
a source contact connecting the first poly layer.
3. The device of claim 2, further comprising:
an active region body; and
a source contact, wherein the active region body and the source contact are disposed outside of said trench.
4. The device of claim 3, wherein the same surface plane is established via a CMP compatible process.
5. The device of claim 3, wherein layout method is used to enable a CMP compatible process to connect the first poly layer to the source electrode and the second poly layer to the gate electrode within said trench.
6. A CMP compatible split gate field effect transistor device, comprising:
a split gate structure having a trench, a gate electrode and a source electrode;
first poly layer a disposed within the trench connected to the source electrode;
a second poly layer disposed within the trench connected to the gate electrode, wherein the first poly layer and the second poly layer are independent; and
a metal layer disposed over the split gate structure.
7. The device of claim 6, further comprising:
a gate contact connecting the second poly layer to the gate electrode; and
a source contact connecting the first poly layer to the source electrode.
8. The device of claim 7, further comprising:
an active region body; and
a source contact, wherein the active region body and the source contact are disposed outside of said trench.
9. The device of claim 8, wherein the same surface plane is established via a CMP compatible process.
10. The device of claim 9, wherein layout method is used to enable a CMP compatible process to connect the first poly layer to the source electrode and the second poly layer to the gate electrode within said trench.
11. A planar split gate field effect transistor device, comprising:
a split gate structure having a trench, a gate electrode and a source electrode;
a first poly layer a disposed within the trench and connected to the source electrode;
a second poly layer is disposed within the trench and connected to the gate electrode, wherein the first poly layer and the second poly layer are independent, and wherein the first poly layer and the second poly layer are both disposed within the trench substantially in their entirety.
12. The device of claim 11, further comprising:
a gate contact connecting the second poly layer to the gate electrode; and
a source contact connecting the first poly layer to the source electrode.
13. The device of claim 12, further comprising:
an active region body; and
a source contact, wherein the active region body and the source contact are disposed at a same surface plane.
14. The device of claim 13, wherein the same surface plane is established via a CMP compatible process.
15. The device of claim 14, wherein layout method is used to enable a CMP compatible process to connect the first poly layer to the source electrode and the second poly layer to the gate electrode within said trench.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for fabricating a pixel structure, comprising:
providing a substrate;
forming a first conductive layer over the substrate;
providing a first shadow mask over the first conductive layer, wherein the first shadow mask exposes a portion of the first conductive layer;
applying a laser ablation process through the first shadow mask to irradiate the first conductive layer to remove the exposed portion of the first conductive layer and form a gate;
forming a gate dielectric layer over the substrate to cover the gate;
forming a channel layer on the gate dielectric layer above the gate;
forming a source and a drain on the channel layer above both sides of the gate, wherein the gate, the channel layer, the source and the drain together constitute a thin film transistor;
forming a patterned passivation layer over the thin film transistor to cover the channel layer and expose the drain; and
forming an electrode material layer to cover the patterned passivation layer and the exposed drain, wherein the patterned passivation layer is used to pattern the electrode material layer to form a pixel electrode.
2. The method for fabricating a pixel structure according to claim 1, further comprising baking the patterned passivation layer after forming the patterned passivation layer so as to make the top-surface of the patterned passivation layer is protruded out of the sidewall of the patterned passivation layer.
3. The method for fabricating a pixel structure according to claim 2, wherein a shape of top-surface of the patterned passivation layer comprises a mushroom-like shape.
4. The method for fabricating a pixel structure according to claim 1, further comprising removing the patterned passivation layer after forming the pixel electrode.
5. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the channel layer comprises:
forming a semiconductor layer over the substrate; and
patterning the semiconductor layer to form the channel layer.
6. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the channel layer comprises:
forming a semiconductor layer on the substrate;
providing a shadow mask over the semiconductor layer, wherein the shadow mask exposes a portion of the semiconductor layer; and
applying a laser through the second shadow mask to irradiate the semiconductor layer for removing the exposed portion of the semiconductor layer.
7. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the source and the drain comprises:
forming a second conductive layer over the channel layer and the gate dielectric layer; and
patterning the second conductive layer to form the source and the drain.
8. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the patterned passivation layer comprises:
forming a passivation layer on the thin film transistor; and
patterning the passivation layer.
9. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the patterned passivation layer comprises:
forming a passivation layer on the thin film transistor;
providing a third shadow mask over the passivation layer, wherein the third shadow mask exposes a portion of the passivation layer; and
applying a laser through the third shadow mask to irradiate the passivation layer for removing the exposed portion of the passivation layer.
10. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the first conductive layer comprises a sputtering process or evaporation process.
11. The method for fabricating a pixel structure according to claim 1, wherein dose of the laser is in a range of 10-500 mJcm2.
12. The method for fabricating a pixel structure according to claim 1, wherein a wavelength of the laser is in a range between 100 nm and 400 nm.
13. The method for fabricating a pixel structure according to claim 1, wherein the patterned passivation layer comprises is formed on a portion of the gate dielectric layer.
14. The method for fabricating a pixel structure according to claim 1, wherein the material of the patterned passivation layer comprises organic photoresist material.
15. The method for fabricating a pixel structure according to claim 1, further comprising simultaneously forming the gate and a lower-layer capacitor electrode, and simultaneously forming the source, the drain and an upper-layer capacitor electrode, wherein the lower-layer capacitor electrode and the upper-layer capacitor electrode together constitute a storage capacitor.
16. The method for fabricating a pixel structure according to claim 1, wherein the substrate comprises glass or plastic.
17. The method for fabricating a pixel structure according to claim 1, wherein the channel layer comprises amorphous silicon (a-Si) or N-type doped amorphous silicon (a-Si).
18. The method for fabricating a pixel structure according to claim 1, wherein the first conductive layer comprises Cu, Al, Mo, Ti, Nd, MoN, TiN or a combination thereof.
19. The method for fabricating a pixel structure according to claim 1, wherein the source and the drain comprise Cu, Al, Mo, Ti, Nd, MoN, TiN or a combination thereof.
20. The method for fabricating a pixel structure according to claim 1, wherein the electrode material layer comprises indium tin oxide (ITO), indium zinc oxide (IZO) or high transparent material.
21. The method for fabricating a pixel structure according to claim 1, wherein a method of laser process further comprises using digital exposing mode to automatically position the laser beam and adjust the energy of the laser beam.

1. A light emitting diode package, comprising:
a metallic frame including
a first metal plate having a first top surface and a first bottom surface,
a second metal plate having a second top surface coplanar with said first top surface, and a second bottom surface coplanar with said first bottom surface, said first and second metal plates being arranged side by side with a space therebetween, and
two support arms that extend integrally and respectively from two opposite ends of said second metal plate to a level higher than said second top surface and that further extend toward said first metal plate at a level higher than said first top surface crossing said space, said support arms being not in contact with said first metal plate;

at least one LED chip disposed on said metallic frame; and
an encapsulant encapsulating said metallic frame and said LED chip and exposing said first and second bottom surfaces, wherein at least a region of said encapsulant that covers said LED chip is transparent.
2. The light emitting diode package of claim 1, wherein said first top surface of said first metal plate has an area larger than that of said second top surface of said second metal plate.
3. The light emitting diode package of claim 1, wherein said first top surface of said first metal plate has an area equal to that of said second top surface of said second metal plate, and said LED chip is flipped over said first top surface and said second top surface.
4. The light emitting diode package of claim 2, wherein (A)>(L)>(A3), where (A) is total length of said first metal plate, said second metal plate and said space along a length direction of said support arms, and (L) is length of each of said support arms.
5. The light emitting diode package of claim 2, wherein each of said support arms includes an extension section extending straightly toward said first metal plate, and a curved section extending curvedly from said extension section toward a curved section of the other one of said support arms, said curved sections of said support arms being located above said first metal plate.
6. The light emitting diode package of claim 5, wherein each of said two support arms includes a connecting section extending curvedly and upwardly from said second metal plate.
7. The light emitting diode package of claim 5, wherein said extension sections of said support arms of said second metal plate extend along a length direction in a parallel and symmetric manner.
8. The light emitting diode package of claim 5, wherein said curved sections are radially disposed above said first metal plate and surround a chip-mounting area that said LED chip is mounted thereon.
9. The light emitting diode package of claim 5, wherein curvatures of said curved sections of said support arms have a common center point on a line that connects a junction of said extension section and said curved section of one of said support arms to a junction of said extension section and said curved section of the other one of said support arms.
10. The light emitting diode package of claim 9, wherein ends of said curved sections of said support arms are spaced apart from each other and subtend an included angle at said common center point, said included angle ranging from 30 to 120 degrees.
11. The light emitting diode package of claim 1, wherein an indented portion is formed in said first bottom surface, and said first bottom surface is divided into two parts by said indented portion.
12. The light emitting diode package of claim 1, wherein said encapsulant includes a non-transparent frame portion and a transparent light exit portion, said frame portion defining a cavity that surrounds said LED chip, a material of said light exit portion filling said cavity and covering said LED chip.
13. The light emitting diode package of claim 12, wherein a fluorescent material is coated on a surface of said LED chip, or said fluorescent material is disposed oninto said light exit portion.
14. The light emitting diode package of claim 1, wherein said encapsulant is made in one piece from a transparent material, and includes abase portion and a lens body projecting from said base portion.
15. The light emitting diode package of claim 14, wherein a fluorescent material is coated on a surface of said LED chip, or said fluorescent material is disposed oninto said lens body.
16. The light emitting diode package of claim 1, wherein said first top surface of said first metal plate has an area smaller than that of said second top surface of said second metal plate.
17. A metallic frame of a light emitting diode package, comprising:
a first metal plate having a first top surface and a first bottom surface;
a second metal plate having a second top surface coplanar with said first top surface, and a second bottom surface coplanar with said first bottom surface, said first and second metal plates being arranged side by side with a first space therebetween; and
two first support arms that extend integrally and respectively from two opposite ends of said second metal plate to a level higher than said second top surface and that further extend toward said first metal plate at a level higher than said first top surface crossing said first space, said first support arms being not in contact with said first metal plate.
18. The metallic frame of claim 17, further comprising a third metal plate and two second support arms, said third metal plate and said first metal plate being arranged side by side with a second space therebetween, said third metal plate having a third top surface coplanar with said first top surface, and a third bottom surface coplanar with said first bottom surface, said second support arms extending integrally and respectively from two opposite ends of said third metal plate to a level higher than said third top surface and further extending toward said first metal plate at a level higher than said first top surface crossing said second space, said second support arms being not in contact with said first metal plate.
19. The metallic frame of claim 18, wherein said first top surface of said first metal plate has an area larger than that of said second top surface of said second metal plate, and larger than that of said third top surface of said third metal plate.
20. The metallic frame of claim 19, wherein said first top surface of said first metal plate, said second top surface of said second metal plate and said third top surface of said third metal plate provided for chip-mounting or wire-bonding have a rectangular shape.
21. The metallic frame of claim 20, wherein (A)>(L)>(A3), where (A) is total length of said first metal plate, said second metal plate, said third metal plate, said first space and said second space along a length direction of said first and second support arms, and (L) is length of each of said first and second support arms.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus comprising:
a device operable to emit a projection;
a surface to reflect said projection to produce a floating image, wherein said surface is substantially flat along a first direction and curved along a second direction that is orthogonal to said first direction; and
at least one reference cue disposed adjacent to said surface.
2. The apparatus of claim 1, wherein said surface comprises a cylindrical mirror.
3. The apparatus of claim 1, wherein said curve along said second direction comprises a substantially parabolic curve.
4. The apparatus of claim 1, wherein said curve along said second direction comprises a substantially circular curve.
5. The apparatus of claim 1, further comprising a light source to form a shadow of said reference cue onto said surface.
6. The apparatus of claim 1, wherein said device is a monitor.
7. The apparatus of claim 6, wherein a color of said monitor is substantially dark in an outer portion of said monitor compared to a substantially light central portion of said monitor.
8. An apparatus comprising:
a device operable to emit a projection;
a surface to reflect said projection to produce a floating image, wherein said surface is substantially flat along a first direction and curved along a second direction that is orthogonal to said first direction;
a panel reflector to reflect said projection onto said surface;
an opening formed by said panel reflector and said surface to accept said projection; and
a viewing aperture formed by said panel reflector and said surface so that said floating image is projected through said viewing aperture.
9. The apparatus of claim 8, wherein a reflectance of said panel reflector comprises a variable reflectance.
10. The apparatus of claim 8, wherein a color across a portion of said panel reflector comprises substantially white blending to gray blending to substantially black, said substantially white portion to receive said projection.
11. The apparatus of claim 8, further comprising at least one reference cue disposed in said viewing aperture.
12. An apparatus comprising:
a device operable to emit a projection;
a surface to reflect said projection to produce a floating image, wherein said surface is substantially flat along a first direction and curved along a second direction that is orthogonal to said first direction; and
a viewing aperture formed by said device and said surface so that said floating image is projected through said viewing aperture.