1. A split gate field effect transistor device, comprising:
a split gate structure having a trench, a gate electrode and a source electrode;
first poly layer a disposed within the trench connected to the source electrode;
a second poly layer connected to the gate electrode, wherein the first poly layer and the second poly layer are independent.
2. The device of claim 1, further comprising:
a gate contact connecting the second poly layer; and
a source contact connecting the first poly layer.
3. The device of claim 2, further comprising:
an active region body; and
a source contact, wherein the active region body and the source contact are disposed outside of said trench.
4. The device of claim 3, wherein the same surface plane is established via a CMP compatible process.
5. The device of claim 3, wherein layout method is used to enable a CMP compatible process to connect the first poly layer to the source electrode and the second poly layer to the gate electrode within said trench.
6. A CMP compatible split gate field effect transistor device, comprising:
a split gate structure having a trench, a gate electrode and a source electrode;
first poly layer a disposed within the trench connected to the source electrode;
a second poly layer disposed within the trench connected to the gate electrode, wherein the first poly layer and the second poly layer are independent; and
a metal layer disposed over the split gate structure.
7. The device of claim 6, further comprising:
a gate contact connecting the second poly layer to the gate electrode; and
a source contact connecting the first poly layer to the source electrode.
8. The device of claim 7, further comprising:
an active region body; and
a source contact, wherein the active region body and the source contact are disposed outside of said trench.
9. The device of claim 8, wherein the same surface plane is established via a CMP compatible process.
10. The device of claim 9, wherein layout method is used to enable a CMP compatible process to connect the first poly layer to the source electrode and the second poly layer to the gate electrode within said trench.
11. A planar split gate field effect transistor device, comprising:
a split gate structure having a trench, a gate electrode and a source electrode;
a first poly layer a disposed within the trench and connected to the source electrode;
a second poly layer is disposed within the trench and connected to the gate electrode, wherein the first poly layer and the second poly layer are independent, and wherein the first poly layer and the second poly layer are both disposed within the trench substantially in their entirety.
12. The device of claim 11, further comprising:
a gate contact connecting the second poly layer to the gate electrode; and
a source contact connecting the first poly layer to the source electrode.
13. The device of claim 12, further comprising:
an active region body; and
a source contact, wherein the active region body and the source contact are disposed at a same surface plane.
14. The device of claim 13, wherein the same surface plane is established via a CMP compatible process.
15. The device of claim 14, wherein layout method is used to enable a CMP compatible process to connect the first poly layer to the source electrode and the second poly layer to the gate electrode within said trench.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for fabricating a pixel structure, comprising:
providing a substrate;
forming a first conductive layer over the substrate;
providing a first shadow mask over the first conductive layer, wherein the first shadow mask exposes a portion of the first conductive layer;
applying a laser ablation process through the first shadow mask to irradiate the first conductive layer to remove the exposed portion of the first conductive layer and form a gate;
forming a gate dielectric layer over the substrate to cover the gate;
forming a channel layer on the gate dielectric layer above the gate;
forming a source and a drain on the channel layer above both sides of the gate, wherein the gate, the channel layer, the source and the drain together constitute a thin film transistor;
forming a patterned passivation layer over the thin film transistor to cover the channel layer and expose the drain; and
forming an electrode material layer to cover the patterned passivation layer and the exposed drain, wherein the patterned passivation layer is used to pattern the electrode material layer to form a pixel electrode.
2. The method for fabricating a pixel structure according to claim 1, further comprising baking the patterned passivation layer after forming the patterned passivation layer so as to make the top-surface of the patterned passivation layer is protruded out of the sidewall of the patterned passivation layer.
3. The method for fabricating a pixel structure according to claim 2, wherein a shape of top-surface of the patterned passivation layer comprises a mushroom-like shape.
4. The method for fabricating a pixel structure according to claim 1, further comprising removing the patterned passivation layer after forming the pixel electrode.
5. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the channel layer comprises:
forming a semiconductor layer over the substrate; and
patterning the semiconductor layer to form the channel layer.
6. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the channel layer comprises:
forming a semiconductor layer on the substrate;
providing a shadow mask over the semiconductor layer, wherein the shadow mask exposes a portion of the semiconductor layer; and
applying a laser through the second shadow mask to irradiate the semiconductor layer for removing the exposed portion of the semiconductor layer.
7. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the source and the drain comprises:
forming a second conductive layer over the channel layer and the gate dielectric layer; and
patterning the second conductive layer to form the source and the drain.
8. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the patterned passivation layer comprises:
forming a passivation layer on the thin film transistor; and
patterning the passivation layer.
9. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the patterned passivation layer comprises:
forming a passivation layer on the thin film transistor;
providing a third shadow mask over the passivation layer, wherein the third shadow mask exposes a portion of the passivation layer; and
applying a laser through the third shadow mask to irradiate the passivation layer for removing the exposed portion of the passivation layer.
10. The method for fabricating a pixel structure according to claim 1, wherein a method of forming the first conductive layer comprises a sputtering process or evaporation process.
11. The method for fabricating a pixel structure according to claim 1, wherein dose of the laser is in a range of 10-500 mJcm2.
12. The method for fabricating a pixel structure according to claim 1, wherein a wavelength of the laser is in a range between 100 nm and 400 nm.
13. The method for fabricating a pixel structure according to claim 1, wherein the patterned passivation layer comprises is formed on a portion of the gate dielectric layer.
14. The method for fabricating a pixel structure according to claim 1, wherein the material of the patterned passivation layer comprises organic photoresist material.
15. The method for fabricating a pixel structure according to claim 1, further comprising simultaneously forming the gate and a lower-layer capacitor electrode, and simultaneously forming the source, the drain and an upper-layer capacitor electrode, wherein the lower-layer capacitor electrode and the upper-layer capacitor electrode together constitute a storage capacitor.
16. The method for fabricating a pixel structure according to claim 1, wherein the substrate comprises glass or plastic.
17. The method for fabricating a pixel structure according to claim 1, wherein the channel layer comprises amorphous silicon (a-Si) or N-type doped amorphous silicon (a-Si).
18. The method for fabricating a pixel structure according to claim 1, wherein the first conductive layer comprises Cu, Al, Mo, Ti, Nd, MoN, TiN or a combination thereof.
19. The method for fabricating a pixel structure according to claim 1, wherein the source and the drain comprise Cu, Al, Mo, Ti, Nd, MoN, TiN or a combination thereof.
20. The method for fabricating a pixel structure according to claim 1, wherein the electrode material layer comprises indium tin oxide (ITO), indium zinc oxide (IZO) or high transparent material.
21. The method for fabricating a pixel structure according to claim 1, wherein a method of laser process further comprises using digital exposing mode to automatically position the laser beam and adjust the energy of the laser beam.