Author: claimsbot

1. A method of disassociating tissue using a dual-compartment bioreactor, which comprises a flexible pouch (1) having two compartments (2, 3) separated by a screen (4), and also at least one inlet opening (5) in communication with one of the compartments (2) and at least one outlet opening (6) in communication with the other compartment (3), comprising the insertion thereof in biological processing equipment, in particular for washing or converting a tissue or cell product, characterized in that it implements, for a tissue dissociation, the use of said bioreactor as a digestion chamber and manual kneading of the flexible pouch for dissociating the tissues during a digestion step in which a digestion solution containing collagenase flows between the inlet (5) and outlet (6) openings of the pouch.
2. The method as claimed in claim 1, characterized in that the tissue dissociation is the sorting of islets of Langerhans and in that the kneading separates the islets of Langerhans.
3. The method as claimed in claim 1, characterized in that the screen (4) has a mesh of between 50 \u03bcm and 600 \u03bcm suitable for the sorting of islets of Langerhans.
4. The method as claimed in claim 1, characterized in that the screen has a pore size that allows only a cell-free liquid to pass through, said liquid being suitable in particular for cell culture or for a method for washing cell suspensions.
5. The method as claimed in claim 1, characterized in that the pouch is used for biological reactions such as cell culture, coculture, or else cell engineering.
6. The method as claimed in claim 1, characterized in that the pouch is used as a washing device in biology, without the need to centrifuge the cell suspension.
7. The method as claimed in claim 1, characterized in that at least one of the compartments has both an inlet opening and an outlet opening.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A semiconductor memory device comprising:
a semiconductor substrate;
a tunnel insulating film formed on said semiconductor substrate;
an Al2O3 film formed on said tunnel insulating film;
a pair of charge storage layers sandwiching said Al2O3 film therebetween in plain view formed on said tunnel insulating film;
an insulating film formed on said Al2O3 film and said pair of charge storage layers;
a gate electrode formed on said insulating film; and
a source region and a drain region formed as a pair sandwiching said gate electrode in plain view formed on a surface of said semiconductor substrate.
2. The semiconductor memory device according to claim 1, further comprising a sidewall insulating film formed over a side surface of said gate electrode, said insulating film, and said pair of charge storage layers.
3. A semiconductor memory device having a pair of charge storage layers in each memory cell thereof and being capable of storing four values, comprising an Al2O3 film insulating said pair of charge storage layers with each other.
4. The semiconductor memory device according to claim 1, wherein
said charge storage layers are composed of a polycrystalline silicon.
5. The semiconductor memory device according to claim 3, wherein
said charge storage layers are composed of a polycrystalline silicon.
6. The semiconductor memory device according to claim 1, wherein
said tunnel insulating film has a thickness of 3 nm to 9 nm.
7. The semiconductor memory device according to claim 3, wherein
a tunnel insulating film has a thickness of 3 nm to 9 nm.
8. The semiconductor memory device according to claim 1, wherein
said Al2O3 film and said pair of charge storage layers have a thickness of 5 nm to 15 nm.
9. The semiconductor memory device according to claim 3, wherein
said Al2O3 film and said pair of charge storage layers have a thickness of 5 nm to 15 nm.
10. A manufacturing method of a semiconductor memory device comprising the steps of:
forming a tunnel insulating film on a semiconductor substrate;
forming sequentially an Al2O3 film, an insulating film, and a material film of a gate electrode on the tunnel insulating film;
forming a gate electrode by processing the material film of the gate electrode, the insulating film, and the Al2O3 film into a planar shape of the gate electrode;
making a retreat of an outer edge of the Al2O3 film to be smaller than an outer edge of the gate electrode by performing isotropic etching to the Al2O3 film so as to form a pair of spaces under the insulating film;
forming charge storage layers respectively in the pair of spaces; and
forming a source region and a drain region sandwiching the gate electrode in plain view, as a pair, on a surface of the semiconductor substrate.
11. The manufacturing method of the semiconductor memory device according to claim 10, wherein
isotropic etching of the Al2O3 film is performed using a solution of sulfuric acid with hydrogen peroxide during the step of performing isotropic etching to the Al2O3 film.
12. The manufacturing method of the semiconductor memory device according to claim 10, wherein
a polycrystalline silicon film is formed as the charge storage layers.
13. The manufacturing method of the semiconductor memory device according to claim 10, wherein
said step of forming the charge storage layers comprises the steps of:
forming a polycrystalline silicon film all over surface; and
making the polycrystalline silicon film remain in the spaces and forming a sidewall composed of the polycrystalline silicon film over side surfaces of the gate electrode and the insulating film by performing anisotropic etching to the polycrystalline silicon film.
14. The manufacturing method of the semiconductor memory device according to claim 13, wherein
said step of forming the charge storage layers comprises a step of oxidizing the sidewall after the step of performing anisotropic etching to the polycrystalline silicon film.
15. The manufacturing method of the semiconductor memory device according to claim 10, wherein
said step of forming the charge storage layers comprises the steps of:
forming a polycrystalline silicon film all over surface; and
making the polycrystalline silicon film remain only in the spaces by performing anisotropic etching to the polycrystalline silicon film.
16. The manufacturing method of the semiconductor memory device according to claim 15, wherein
said step of forming the charge storage layers comprises the steps of:
forming an insulating film for a sidewall all over surface; and
forming a sidewall insulating film over side surfaces of the gate electrode and the insulating film by etching back the insulating film for the sidewall, after the step of performing anisotropic etching to the polycrystalline silicon film.
17. The manufacturing method of the semiconductor memory device according to claim 10, wherein
the tunnel insulating film has a thickness of 3 nm to 9 nm.
18. The manufacturing method of the semiconductor memory device according to claim 10, wherein
the Al2O3 film and the pair of charge storage layers have a thickness of 5 nm to 15 nm.
19. The manufacturing method of the semiconductor memory device according to claim 11, wherein
the tunnel insulating film has a thickness of 3 nm to 9 nm.
20. The manufacturing method of the semiconductor memory device according to claim 11, wherein
the Al2O3 film and a pair of charge storage layers have a thickness of 5 nm to 15 nm.

1. An integrated circuit, comprising:
a substrate, a surface region of the substrate comprising a contact pad region; and
a passivation layer stack comprising at least one passivation layer, the passivation layer stack formed over the surface region and adjacent to the contact pad region,
wherein, in a portion of the passivation layer stack proximate the contact pad region, an upper portion of the passivation layer stack is removed.
2. The integrated circuit of claim 1, wherein the passivation layer stack comprises:
a first passivation layer formed on the surface region;
a second passivation layer formed on the first passivation layer; and
a third passivation layer formed on the second passivation layer.
3. The integrated circuit of claim 2, wherein the first passivation layer comprises a first nitride layer, wherein the second passivation layer comprises an oxide layer, and wherein the third passivation layer comprises a second nitride layer.
4. The integrated circuit of claim 1, further comprising an adhesion layer disposed on the passivation layer stack.
5. The integrated circuit of claim 4, wherein, in the portion of the passivation layer stack proximate the contact pad region, the passivation layer stack is free from the adhesion layer.
6. The integrated circuit of claim 1, further comprising a reinforcement layer stack formed on an upper surface of the contact pad region, the reinforcement layer stack comprising at least one reinforcement layer.
7. The integrated circuit of claim 6, wherein an upper surface of the reinforcement layer stack is flush with an upper surface of the passivation layer stack.
8. An integrated circuit comprising:
a metallization layer overlying a semiconductor workpiece;
a via surrounded by an electrically insulating region, the via overlying the metallization layer;
a contact pad region overlying the via such that the via electrically couples the metallization layer and the contact pad region;
an electrically insulating layer overlying the electrically insulating region, wherein the contact pad region is embedded in the electrically insulating layer;
a passivation layer overlying the electrically insulating layer but not overlying the contact pad region; and
an adhesion layer overlying portions of the passivation layer that are not proximate the contact pad region, wherein the passivation layer has a first thickness in the portions that underlie the adhesion layer and a second thickness in remaining portions that are proximate the contact pad region, the first thickness being greater than the second thickness.
9. The integrated circuit of claim 8, wherein a top surface of the contact pad region is substantially co-planar with a top surface of the electrically insulating layer.
10. The integrated circuit of claim 9, further comprising a reinforcement layer stack overlying the contact pad region.
11. The integrated circuit of claim 10, wherein the reinforcement layer stack has substantially the second thickness so that a top surface of the reinforcement layer stack is substantially co-planar with the portions of the passivation layer that are adjacent the contact pad region.
12. The integrated circuit of claim 8, wherein the portions of the passivation layer proximate the contact pad region surround the contact pad region by a lateral length of between about 3 \u03bcm to about 8 \u03bcm.
13. The integrated circuit of claim 8, further comprising a reinforcement layer stack overlying the contact pad region.
14. The integrated circuit of claim 13, wherein the contact pad region comprises copper and the reinforcement layer stack comprises a first layer comprising nickel, a second layer comprising palladium and a third layer comprising gold.
15. The integrated circuit of claim 8, wherein the passivation layer comprises a passivation layer stack.
16. The integrated circuit of claim 15, wherein the passivation layer stack comprises a first nitride layer, an oxide layer overlying the first nitride layer, and a second nitride layer overlying the oxide layer.
17. The integrated circuit of claim 16, wherein the first nitride layer and the oxide layer both have a substantially uniform thickness throughout the portions that underlie the adhesion layer and the portions that are proximate the contact pad region.
18. The integrated circuit of claim 8, wherein the adhesion layer comprises an imide layer.
19. The integrated circuit of claim 18, wherein the contact pad region comprises copper and the adhesion layer comprises a photoimide.
20. An integrated circuit comprising:
an electrically insulating layer;
a contact pad region that is embedded in the electrically insulating layer such that a top surface of the contact pad region is substantially co-planar with a top surface of the electrically insulating layer;
a passivation layer stack overlying the electrically insulating layer but not overlying the contact pad region such that edges of the passivation layer stack are adjacent the contact pad region, the passivation layer stack including a first passivation layer and a second passivation layer that overlies the first passivation layer;
an adhesion layer overlying the passivation layer stack but spaced from the contact pad region by a lateral distance of at least one micron; and
a reinforcement layer stack overlying the contact pad region, a top surface of the reinforcement layer stack is substantially co-planar with a top surface of the passivation layer stack.
21. The integrated circuit of claim 20, wherein the adhesion layer is spaced from the contact pad region by a lateral distance of between about 3 \u03bcm to about 8 \u03bcm.
22. The integrated circuit of claim 20, wherein the contact pad region comprises copper and the reinforcement layer stack comprises a first layer comprising nickel, a second layer comprising palladium and a third layer comprising gold.
23. The integrated circuit of claim 20, wherein the passivation layer stack comprises a first nitride layer, an oxide layer overlying the first nitride layer, and a second nitride layer overlying the oxide layer.
24. The integrated circuit of claim 20, wherein the passivation layer stack has a first thickness in portions underlying the adhesion layer and a second thickness in remaining portions, the first thickness being greater than the second thickness.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system for the circulatory conveyance of media, with two conveying chambers and with a common drive (1), wherein the first conveying chamber constitutes a feed chamber (4) and the second conveying chamber a return chamber (3).
2. The system as claimed in claim 1, defined by a double-diaphragm pump.
3. The system as claimed in claim 1 or 2, defined by a pulsation damper
4. The system as claimed in claim 3, wherein the pulsation damper (5) is integrated into the feed chamber (4).
5. The system as claimed in one of claims 1 to 4, defined by a needle valve (10).
6. The system as claimed in one of claims 1 to 5, wherein at least one line connection is arranged perpendicularly to the feed chamber (4) andor return chamber (3).
7. The system as claimed in one of claims 1 to 6, defined by polyethylene housing parts of the drive (1) andor of the conveying chambers (3,4).
8. The system as claimed in one of claims 1 to 7, defined by a reservoir (13).
9. The system as claimed in one of claims 1 to 8, defined by a four-way valve (12).
10. The system as claimed in claim 9, wherein the four-way valve (12) is designed as a disk valve.
11. A use of a system as claimed in one of claims 1 to 10 for the conveyance of media along a circulatory path between a first and a second container.
12. A use of a system as claimed in one of claims 1 to 10 for regulating the filling-level height in a doctor blade chamber.
13. A use of a system as claimed in claim 9 or 10 for emptying a first and a second container.
14. A method for conveying a medium from a first container into a second container, with the following steps:
operating a pump assembly with a feed chamber and with a discharge chamber by means of a common drive;
sucking the medium out of the first container into a feed chamber;
discharging the medium from the feed chamber into the second container;
sucking the medium out of the second container into a return chamber, and
discharging the medium from the return chamber into the first container.
15. The method as claimed in claim 14, defined by a pulsation damping of the medium.