Author: claimsbot

1. A composite porous material comprising:
a substrate comprising a sintered porous first polymeric material having a first average pore size;
a membrane comprising a precipitated porous second polymeric material having a second average pore size smaller than the first average pore size;

wherein at least a portion of the membrane is fused to the substrate by at least one direct physical bond, the second polymeric material is in at least some of the pores of the first polymeric material, and the first polymeric material and the second polymeric material are soluble in a common solvent.
2. The composite porous material of claim 1, wherein
the first polymeric material comprises polyvinylidene fluoride, polysulfone, polyethersulfone, polyamide, polyether imide, polyacrylonitrile, polyester, polyvinyl chloride, or polyetheretherketone, and the second polymeric material comprises polyvinylidene fluoride, polysulfone, polyethersulfone, polyamide, polyether imide, polyacrylonitrile, polyester, polyvinyl chloride, or polyetheretherketone.
3. The composite material of claim 2, wherein the first polymeric material comprises polysulfone and the second polymeric material comprises polyethersulfone.
4. The composite material of claim 2, wherein the first polymeric material comprises polyethersulfone and the second polymeric material comprises polyethersulfone.
5. The composite material of claim 2, wherein the first polymeric material comprises polyethersulfone and the second polymeric material comprises polysulfone.
6. The composite material of claim 2, wherein the first polymeric material comprises polyvinylidene fluoride and the second polymeric material comprises polyethersulfone.
7. The composite material of claim 2, wherein the first polymeric material comprises polyamide and the second polymeric material comprises polyamide.
8. The composite material of claim 2, wherein the first polymeric material comprises polyamide and the second polymeric material comprises polyvinylidene fluoride.
9. The composite material of claim 2, wherein the first polymeric material comprises polyvinylidene fluoride and the second polymeric material comprises polyamide.
10. The composite material of claim 2, wherein the first polymeric material comprises polyvinylidene fluoride and the second polymeric material comprises polysulfone.
11. The composite material of claim 2, wherein the first polymeric material comprises polysulfone and the second polymeric material comprises polyvinylidene fluoride.
12. The composite material of claim 2, wherein the first polymeric material comprises polysulfone and the second polymeric material comprises polyamide.
13. The composite material of claim 2, wherein the first polymeric material comprises polyether imide and the second polymeric material comprises polyether imide.
14. The composite material of claim 2, wherein the first polymeric material comprises polyether imide and the second polymeric material comprises polyvinylidene fluoride.
15. The composite material of claim 2, wherein the first polymeric material comprises polyether imide and the second polymeric material comprises polyethersulfone.
16. The composite material of claim 2, wherein the first polymeric material comprises polyether imide and the second polymeric material comprises polysulfone.
17. The composite material of claim 2, wherein the first polymeric material comprises polyether imide and the second polymeric material comprises polyamide.
18. The composite material of claim 2, wherein the first polymeric material comprises polyvinylidene fluoride and the second polymeric material comprises polyether imide.
19. The composite material of claim 2, wherein the first polymeric material comprises polysulfone and the second polymeric material comprises polyether imide.
20. The composite material of claim 2, wherein the first polymeric material comprises polyethersulfone and the second polymeric material comprises polyether imide.
21. The composite material of claim 2, wherein the first polymeric material comprises polyamide and the second polymeric material comprises polyether imide.
22. The composite material of claim 2, wherein the first polymeric material comprises polyvinylidene fluoride and the second polymeric material comprises polyvinylidene fluoride.
23. The composite porous material of claim 1, wherein the first polymeric material is a sheet, tube, or other molded shape.
24. The composite porous material of claim 1, wherein the first polymeric material has a thickness greater than about 250 \u03bcm.
25. The composite porous material of claim 1, wherein the second polymeric material has a thickness less than about 125 \u03bcm.
26. The composite porous material of claim 1, wherein the first polymeric material comprises sintered underwater pelletized particles.
27. The composite porous material of claim 1, wherein the first polymeric material comprises sintered cryogenically ground particles.
28. The composite material of claim 1, wherein the second polymeric material is in greater than about 1% of the pores of the first polymeric material.
29. The composite porous material of claim 1, wherein the first average pore size ranges from about 1 \u03bcm to about 200 \u03bcm.
30. The composite porous material of claim 1, wherein the second average pore size ranges from about 0.2 nm to about 10 \u03bcm.
31. The composite material of claim 1, wherein the second polymeric material has a thickness less than or equal to the first polymeric material.
32. The composite material of claim 1, wherein at least a portion of the membrane is fused to the first polymeric material by a plurality of direct physical bonds.
33. A composite porous material comprising:
a substrate comprising a sintered porous first polymeric material having a first average pore size;
a membrane comprising a precipitated porous second polymeric material having a second average pore size smaller than the first average pore size;
wherein at least a portion of the membrane is fused to the substrate by at least one direct physical bond, the second polymeric material is in at least some of the pores of the first polymeric material, and the first polymeric material comprises polyvinylidene fluoride, polysulfone, polyethersulfone, polyamide, polyether imide, polyacrylonitrile, polyester, polyvinyl chloride, or polyetheretherketone, and the second polymeric material comprises polyvinylidene fluoride, polysulfone, polyethersulfone, polyamide, polyether imide, polyacrylonitrile, polyester, polyvinyl chloride, or polyetheretherketone.
34. A composite porous material comprising:
a substrate comprising a sintered porous first polymeric material having a first average pore size;
a membrane comprising a precipitated porous second polymeric material having a second average pore size smaller than the first average pore size;
wherein at least a portion of the membrane is fused to the substrate by at least one direct physical bond, the second polymeric material is in at least some of the pores of the first polymeric material, and the first polymeric material comprises polyvinylidene fluoride, polysulfone, polyethersulfone, polyamide, polyether imide, polyacrylonitrile, polyester, polyvinyl chloride, or polyetheretherketone, the second polymeric material comprises polyvinylidene fluoride, polysulfone, polyethersulfone, polyamide, polyether imide, polyacrylonitrile, polyester, polyvinyl chloride, or polyetheretherketone, and the first polymeric material and the second polymeric material are soluble in a common solvent.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for allocating core processor bandwidth, comprising:
detecting an interrupt service request;
storing into an instruction cache interrupt service instructions in response to detecting the interrupt service request;
fetching instructions from the instruction cache into an instruction stream sequence, the instruction stream sequence including mainline program instructions and the interrupt service instructions resulting in allocating core processor bandwidth between the interrupt servicing and mainline program instructions while executing the instruction stream sequence based on an interrupt priority;
decoding instructions from the instruction stream sequence into micro-ops;
executing the micro-ops in one or more out-of-order execution units;
recycling the executed micro-ops for optional re-execution in the one or more out-of-order execution units by retiring the executed micro-ops including those micro-ops representing the interrupt servicing instructions to the instruction cache.
2. The method of claim 1 where the processor bandwidth is allocated to interrupt servicing without flushing the instruction cache.
3. The method of claim 1 where the detecting is performed by an interrupt processor, which after the detecting, the method comprising:
at the interrupt processor, determining whether the detected interrupt service request is of a priority meeting one or more defined high-priority criteria and if so then signaling the core processor to perform the storing; and
at the core processor, responding to said signaling by performing said storing and processing.
4. The method of claim 1 comprising retiring the executed micro-ops to the instruction cache in order.
5. The method of claim 1 where detecting comprises detecting plural interrupts by prioritizing the plural interrupts and storing one or more instances of the interrupt servicing instructions into the instruction stream sequence within the instruction cache in accordance with one or more predefined interrupt servicing allocation criteria.
6. The method of claim 5 where the one or more allocation criteria include the priority of the interrupts and the capacity of the processor to allocate bandwidth to interrupt servicing.
7. The method of claim 6 where the prioritizing is dynamically responsive to changing allocation criteria.
8. A machine-readable medium comprising a computer-readable medium containing instructions, that, when executed by a machine cause the machine to perform a method comprising:
detecting an interrupt service request;
storing into an instruction cache interrupt service instructions in response to detecting the interrupt service request;
fetching instructions from the instruction cache into an instruction stream sequence, the instruction stream sequence including mainline program instructions and the interrupt service instructions resulting in allocating core processor bandwidth between the interrupt servicing and mainline program instructions while executing the instruction stream sequence based on an interrupt priority;
processing instructions from the instruction stream sequence including the interrupt servicing instructions; and
signaling after detecting an impending natural context switch represented by a recognized instruction sequence within the instruction cache;
where detecting an impending natural context switch is predicated on the instruction stream sequence.
9. The article of claim 8 comprising:
signaling with a vector representing an interrupt service request upon determining that an interrupt service request of a priority that exceeds a given threshold has occurred; and
fetching interrupt service instructions from memory in accordance with the vector representing the determined priority interrupt service request.
10. A method comprising:
detecting an interrupt service request;
storing into an instruction cache interrupt service instructions in response to detecting the interrupt service request;
fetching instructions from the instruction cache into an instruction stream sequence, the instruction stream sequence including mainline program instructions and the interrupt service instructions resulting in allocating core processor bandwidth between the interrupt servicing and mainline program instructions while executing the instruction stream sequence based on an interrupt priority;
executing the interrupt servicing instructions and the other program instructions from the instruction stream sequence;
determining that a natural processor context switch is imminent, said determining including analyzing one or more instructions within the instruction cache for context switch-inducing instructions;
signaling an interrupt processor to make ready the highest priority interrupt service request; and
signaling an instruction fetch unit to fetch the readied interrupt service request in advance of a context switch responsive to the determining;
where the detecting is performed by the interrupt processor.
11. A processor, comprising:
a fetch unit to fetch instructions from an instruction cache into an instruction stream sequence, the instruction stream sequence including mainline program instructions and interrupt service instructions resulting in allocating processor bandwidth between the interrupt servicing and mainline program instructions while executing the instruction stream sequence based on an interrupt priority;
an interrupt handler to detect an interrupt service request;
a decode unit to decode the instruction stream sequence including mainline program and interrupt servicing instructions into micro-ops;
a dispatch unit to schedule the micro-ops for execution;
an execute unit to execute the micro-ops;
a retirement unit to retire executed micro-ops including the micro-ops corresponding to the interrupt instructions back to the instruction cache; and
where the interrupt handler signals the fetch and decode units to insert micro-ops corresponding to the interrupt servicing instructions into the instruction stream sequence without flushing the instruction cache.
12. The processor of claim 11
where the processor supports plural hardware interrupt inputs;
where the interrupt-handler includes an interrupt concentrator to determine priority among the plural hardware interrupt inputs and to schedule the plural hardware interrupt inputs; and
where the interrupt-handler is adapted to instruct the fetch and decode units such that plural instances of such decoded micro-ops are inserted, each instance representing one or more corresponding sets of the interrupt servicing instructions, into the instruction stream sequence for serial scheduling and execution of the plural instances of such decoded micro-ops by the dispatch and execute units in accordance with a determined priority of the plural hardware interrupt inputs.
13. A processor comprising:
a fetch unit to fetch instructions from an instruction cache into an instruction stream sequence, the instruction stream sequence including mainline program instructions and interrupt service instructions resulting in allocating processor bandwidth between the interrupt servicing and mainline program instructions while executing the instruction stream sequence based on an interrupt priority;
an interrupt handler to detect an interrupt service request;
a decode unit to decode instructions from the instruction stream sequence including mainline program and interrupt servicing instructions into micro-ops;
a dispatch unit to schedule the micro-ops for execution;
an execute unit to execute the micro-ops;
a context switch prediction unit coupled with the fetch and decode units to predict a naturally occurring context switch and to signal the interrupt handler upon such prediction, the context switch prediction unit being adapted to analyze one or more instructions within a context switch inducing instruction cache;
where the interrupt handler signals the fetch and decode units to insert micro-ops corresponding to the interrupt servicing instructions into the instruction stream sequence without flushing the instruction cache; and
where the interrupt handler is coupled to the prediction unit instructing the fetch and decode units.
14. An apparatus, comprising:
an instruction queue mechanism to stage an instruction stream sequence including mainline and interrupt instructions for execution;
a plurality of interrupt inputs corresponding to a plurality of hardware inputoutput devices;
interrupt priority logic to prioritize the plurality of interrupt inputs;
bandwidth allocation logic to allocate processing resources to service the plurality of interrupts according to their relative priority;
a decoder to generate p-code representative of the instruction stream sequence including mainline and interrupt instructions responsive to the plurality of interrupts and the bandwidth allocation logic;
a p-code insertion mechanism to insert the p-code representative of the interrupt instructions into an instruction stream containing the p-code representative of the mainline instructions according to the processing resources allocated to the plurality of interrupt inputs;
a p-code processor coupled to the instruction queue mechanism and to the insertion mechanism to execute the p-code representative of the mainline and interrupt instructions in the instruction stream;
a retirement unit to retire executed p-code representative of the mainline and interrupt instructions back to an instruction cache.
15. The apparatus of claim 14,
where the instruction queue mechanism includes an instruction cache and an in-order instruction unit to perform branch predictions; and
where the p-code processor includes a dispatch and our-of-order execution units to schedule and execute the p-code representative of the mainline and interrupt instructions in parallel among one or more execution ports.
16. The apparatus of claim 14 where the priority logic is coupled to a current-usage model.
17. The apparatus of claim 15 where the in-order instruction unit includes said allocation logic.
18. The apparatus of claim 17 where the allocation logic is coupled to a computer operating system.
19. The apparatus of claim 14 where the priority logic is coupled to a computer operating system.
20. The apparatus of claim 14 where the allocation logic is coupled to a current-usage model.
21. A computer system, comprising:
one or more inputoutput (IO) devices to generate one or more hardware interrupts; an interrupt concentrator to rank and queue the interrupts into an ordered interrupt array;
a core processor coupled to the interrupt concentrator, the core processor including an instruction cache, fetch unit, and a decode unit,
the fetch unit to fetch instructions from the instruction cache into an instruction stream sequence, the instruction stream sequence including mainline program instructions and interrupt service instructions resulting in allocating processor bandwidth between the interrupt servicing and mainline program instructions while executing the instruction stream sequence based on an interrupt priority; and
the decode unit to decode the instruction stream sequence including interrupt service instructions and other program instructions into micro-ops,
the core processor including a dispatch unit to schedule the micro-ops, and an execute unit having one or more execution ports to execute the micro-ops in the one or more execution ports; and
an interrupt-handler responsive to the one or more hardware interrupts, the interrupt-handler instructing the fetch and decode units to insert into an instruction sequence decoded micro-ops representing interrupt servicing instructions for scheduling and execution by the dispatch and execute units, wherein the instruction sequence also comprises decoded micro-ops representing other program instructions.
22. The computer system of claim 21 which supports plural hardware interrupt inputs, where the interrupt-handler includes the interrupt concentrator to determine priority among and to schedule the plural hardware interrupts, the interrupt-handler instructing the fetch and decode units to insert plural instances of such decoded micro-ops, each instance representing one or more corresponding sets of the interrupt servicing instructions, into the instruction sequence for serial scheduling and execution of the plural instances of such decoded micro-ops by the dispatch and execute units in accordance with the determined priority of said plural hardware interrupts.
23. The computer system of claim 21 comprising:
a context switch prediction unit coupled with the fetch and decode units to predict a naturally occurring context switch represented by a recognized instruction sequence within the instruction cache and to signal the interrupt-handler upon such prediction;
where the interrupt-handler is coupled to such signaling from the prediction unit instructing the fetch and decode units.
24. A method, comprising:
detecting an interrupt service request;
fetching instructions from the instruction cache into an instruction stream sequence, the instruction stream sequence including micro-ops representative of interrupt servicing instructions responsive to the interrupt service request and micro-ops representative of mainline program instructions;
allocating core processor bandwidth between the inserted micro-ops representative of the interrupt servicing instructions and the micro-ops representative of the mainline program instructions while executing the instruction stream sequence based on an interrupt priority;
processing the instruction stream sequence without first flushing the instruction cache; and
re-processing the instruction stream sequence including micro-ops representative of the interrupt servicing instructions and the micro-ops representative of the mainline program instructions in the one or more out-of-order execution units by reordering and retiring the executed micro-ops including those micro-ops representing the inserted interrupt servicing instructions to the instruction cache.

1-31. (canceled).
32. The offset printing method as set forth in claim 59, wherein the material on the printing plate has photocatalyst function, and
wherein the whole of the surface of the printing plate is made hydrophilic first by irradiating light having a wavelength activating the photocatalyst function, and then a part of the surface of the printing plate is heated at the second temperature to form a hydrophobic region.
33. The offset printing method as set forth in claim 32, wherein the second temperature is 50 to 250\xb0 C.
34. The offset printing method as set forth in claim 32, wherein the claimed steps are repeated to reuse the printing plate after cleaning the surface thereof to remove ink left after the printing.
35. The offset printing method as set forth in claim 32, wherein the hydrophobic region forming step is performed by one recording means selected from a thermal transfer recording head and a photothermal converting type radiant rays.
36. The offset printing method as set forth in claim 32, wherein the hydrophobic region forming step is performed in an atmosphere in which an organic compound exists.
37. The offset printing method as set forth in claim 36, wherein the organic compound has a vapor pressure of at least 1 mmHg or higher at 400\xb0 C., and is stable at the first temperature.
38. The offset printing method as set forth in claim 36, wherein the organic compound has a boiling point of 30 to 400\xb0 C., and is stable at the first temperature.
39. The offset printing method as set forth in claim 32, wherein the material on the printing plate is constituted by at least one of metal selected from a group consisting of elements belonging to third to sixth period of the periodic table and elements not belonging to group 0 and group VIIA (halogen elements) and a group of oxides of the metal.
40. The offset printing method as set forth in claim 32, wherein the material on the printing plate is constituted by at least one type of metal oxide selected from a group consisting of Ti02, RTi03 (where R is an alkaline earth metal atom), AB2-xCxD3-xExO10 (x is an arbitrary value from 0 to 2), and Sn02, Bi203, Si02, Ge02, Al203, ZnO and FeOx, (x is an arbitrary value from 1 to 1.5), and
wherein A is a hydrogen atom or an alkaline metal atom, B is an alkaline earth metal atom or a lead atom, C is a rare earth atom, D is a metal atom belonging to elements in group 5A of the periodic table, and E is a metal atom belonging to elements in group 4A.
41-45. (canceled).
46. The offset printing method as set forth in claim 59, wherein the material on the printing plate has photocatalyst function, and
wherein the whole of the surface of the printing plate is made hydrophobic first by heating at the second temperature, and then a part of the surface of the printing plate of the printing plate is irradiated by light having a wavelength activating the photocatalyst function to form a hydrophilic region.
47. The offset printing method as set forth in claim 46, wherein the second temperature is 50 to 250\xb0 C.
48. The offset printing method as set forth in claim 46, wherein the claimed steps are repeated to reuse the printing plate after cleaning the surface thereof to remove ink left after the printing.
49. The offset printing method as set forth in claim 46, wherein the hydrophobication step is performed in an atmosphere in which an organic compound exists.
50. The offset printing method as set forth in claim 49, wherein the organic compound has a vapor pressure of at least 1 mmHg or higher at 400\xb0 C., and is stable at the second temperature.
51. The offset printing method as set forth in claim 49, wherein the organic compound has a boiling point of 30 to 400\xb0 C., and is stable at the second temperature.
52. The offset printing method as set forth in claim 46, wherein the material on the printing plate is constituted by at least one of metal selected from a group consisting of elements belonging to third to sixth period of the periodic table and except for elements not belonging to group 0 and group VIIA (halogen elements) and a group of oxides of the metal.
53. The offset printing method as set forth in claim 46, wherein the material on the printing plate is constituted by at least one type of metal oxide selected from a group consisting of Ti02, RTiO3 (where R is an alkaline earth metal atom), AB2-xCxD3-xExO10 (x is an arbitrary value from 0 to 2), and Sn02, Bi203, Si02, Ge02, Al203, ZnO and FeOx (x is an arbitrary value from 1 to 1.5), and
wherein A is a hydrogen atom or an alkaline metal atom, B is an alkaline earth metal atom or a lead atom, C is a rare earth atom, D is a metal atom belonging to elements in group 5A of the periodic table, and E is a metal atom belonging to elements in group 4A.
54-58. (canceled).
59. An offset printing method, comprising the steps of:
preparing a printing plate having a surface converted to hydrophilic due to light energy generated at a first temperature, the surface being converted to hydrophobic due to the heat energy generated at a second temperature;
making forcibly the whole surface of the printing plate either one of hydrophobic or hydrophilic in nature;
forming a region having the other one nature of hydrophobic and hydrophilic on a part of the surface of the printing plate so as to correspond to an image to be printed;
supplying ink onto the region having the hydrophobic nature; and
transferring the ink onto a printing medium to print the image.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A mediator for optimizing the transmission of media contents between a multimedia resource function and a plurality of terminals
when these terminals are conferees in a same video call conference created by a telephony server; comprising\u2014:
means for receiving video content requests from said terminals when they request to take part in said video call conference,

and then forwarding the received video streams to the terminals that have requested them, when a same video stream has been requested by several terminals,
and means for commanding the telephony server to accept conferees in the video call conference, as a function of the video content requests from said terminals, for receiving the video streams that have been requested, from the multimedia resource function;
means for optimizing these requests, in order to avoid requesting any redundant video stream from the multimedia resource function. and then forwarding the optimized requests to the multimedia resource function; and

means for implementing virtual conferees as a function of the video content requests from said terminals, for receiving the video streams that have been requested by the optimized requests, from the multimedia resource function.
2. A gateway for optimizing the transmission of media contents between a multimedia resource function and a plurality of terminals via this gateway, when these terminals are conferees in a same video call conference created by a telephony server; comprising
means for implementing conferees when a same video stream has been requested by several terminals;
wherein said means for implementing conferees implement virtual conferees in the video call conference, these virtual conferees forwarding the received video streams to the terminals that have requested them, in a broadcast way, when a same video stream has been requested by several terminals.
3. A multimedia resource for optimizing the transmission of media contents between this multimedia resource function and a plurality of terminals when these terminals are conferees in a same video call conference created by a telephony server;
comprising:
means for receiving video content requests from said terminals when they request to take part in said video call conference,
and means for commanding the telephony server to accept virtual conferees in the video call conference;

wherein for optimizing these requests, in order to avoid requesting any redundant video stream from the multimedia resource function, said means for commanding the telephony server to accept conferees, comprise
means for commanding the telephony server to accept virtual conferees in the video call conference, these virtual conferees forwarding the received video streams to the terminals that have requested them, in a broadcast way, when a same video stream has been requested by several terminals.