Author: claimsbot

1-25. (canceled)
26. A system for controlling condensation associated with a vehicle engine air supply, comprising:
a shutter assembly configured to selectively allow airflow therethrough;
an air supply cooler configured to provide intake air to an engine, the air supply cooler being situated relative to the shutter assembly such that air flowing through the shutter assembly is incident on an exterior of the air supply cooler; and
a controller that is configured to:
determine when at least one condition exists that is conducive to condensation within the air supply cooler by
determining a condensation temperature range based on at least an ambient air temperature and an ambient air pressure, and
determining whether an intake air temperature is within the condensation temperature range; and

control the shutter assembly to alter an amount of air incident on the exterior of the air supply cooler for controlling condensation in the air supply cooler.
27. The system of claim 26, wherein the controller is configured to control the shutter assembly to raise the intake air temperature to a temperature above an upper limit of the condensation range by reducing an amount of air incident on the exterior of the air supply cooler when the condition exists.
28. The system of claim 26, wherein the controller controls the shutter assembly to reduce an amount of cooling of the intake air within the air supply cooler when the at least one condition exists.
29. The system of claim 28, wherein the controller is configured to at least temporarily close the shutter assembly when the at least one condition exists.
30. The system of claim 26, wherein the controller is configured to determine whether the at least one condition exists by determining whether moisture is present in ambient air based on at least one indicator.
31. The system of claim 30, wherein the at least one indicator comprises an indication that vehicle windscreen wipers are on.
32. The system of claim 26, wherein the controller is configured to:
determine whether a vehicle speed is within a speed range conducive to condensation;
determine whether an ambient pressure is within a pressure range conducive to condensation;
determine whether there is moisture in ambient air;
determine whether an engine operating condition requires a setting of the shutter assembly;
determine whether the at least one condition exists when the vehicle speed is within the speed range, the ambient pressure is within the pressure range, and there is moisture in the ambient air; and
control the shutter assembly for controlling condensation in the air supply cooler when the at least one condition exists and the engine operating condition does not require a setting of the shutter assembly.
33. A method of controlling condensation associated with a vehicle engine air supply, comprising the steps of:
determining whether at least one condition exists that is conducive to condensation within an air supply cooler that is configured to provide intake air to an engine; and
controlling a shutter assembly to alter an amount of air incident on an exterior of the air supply cooler for controlling condensation in the air supply cooler when the at least one condition exists,
wherein determining whether the at least one condition exists comprises:
determining a condensation temperature range based on at least an ambient air temperature and an ambient air pressure; and
determining whether an intake air temperature is within the condensation temperature range.
34. The method of claim 33, comprising controlling the shutter assembly to raise the intake air temperature to a temperature above an upper limit of the condensation range by reducing an amount of air incident on the exterior of the air supply cooler when the condition exists.
35. The method of claim 33, comprising controlling the shutter assembly to reduce an amount of cooling of the intake air within the air supply cooler when the at least one condition exists.
36. The method of claim 33, comprising at least temporarily closing the shutter assembly when the at least one condition exists.
37. The method of claim 33 wherein determining whether the at least one condition exists comprises determining whether moisture is present in ambient air based on at least one indicator.
38. The method of claim 37, wherein the at least one indicator comprises an indication that vehicle windscreen wipers are on.
39. The method of claim 33, comprising:
determining whether a vehicle speed is within a speed range conducive to condensation;
determining whether an ambient pressure is within a pressure range conducive to condensation;
determining whether there is moisture in ambient air;
determining whether an engine operating condition requires a setting of the shutter assembly;
determining whether the at least one condition exists when the vehicle speed is within the speed range, the ambient pressure is within the pressure range, and there is moisture in the ambient air; and
controlling the shutter assembly for controlling condensation in the air supply cooler when the at least one condition exists and the engine operating condition does not require a setting of the shutter assembly.
40. A vehicle, comprising:
an engine;
an intake air supply cooler situated to provide cooled intake air to the engine.
a shutter assembly configured to selectively allow airflow through the shutter assembly, the shutter assembly being situated relative to the air supply cooler such that at least some of the airflow through the shutter assembly is incident on an exterior of the air supply cooler; and
a controller configured to:
determine when at least one condition exists that is conducive to condensation within the air supply cooler by
determining a condensation temperature range based on at least an ambient air temperature and an ambient air pressure, and
determining whether an intake air temperature is within the condensation temperature range; and

control the shutter assembly to alter an amount of air incident on the exterior of the air supply cooler for controlling condensation in the air supply cooler.
41. The vehicle of claim 40, wherein the controller is configured to control the shutter assembly to raise the intake air temperature to a temperature above an upper limit of the condensation range by reducing an amount of air incident on the exterior of the air supply cooler when the condition exists.
42. The vehicle of claim 40, wherein:
the shutter assembly comprises a plurality of shutter members that are selectively moveable between an open and a closed position.
43. The vehicle of claim 42, wherein the controller controls a position of the shutter members to at least temporarily reduce an amount of air incident on the air supply cooler for reducing cooling of the intake air within the air supply cooler when the at least one condition exists.
44. The vehicle of claim 40, comprising windscreen wipers and wherein the controller is configured to determine whether the at least one condition based on an operating condition of the windscreen wipers as an indication of whether moisture is present in ambient air.
45. The vehicle of claim 40, wherein the controller is configured to:
determine whether a vehicle speed is within a speed range conducive to condensation;
determine whether an ambient pressure is within a pressure range conducive to condensation;
determine whether there is moisture in ambient air;
determine whether an engine operating condition requires a setting of the shutter assembly;
determine whether the at least one condition exists when the vehicle speed is within the speed range, the ambient pressure is within the pressure range, and there is moisture in the ambient air; and
control the shutter assembly for controlling condensation in the air supply cooler when the at least one condition exists and the engine operating condition does not require a setting of the shutter assembly.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-13. (canceled)
14. A system of accelerating transmission of a packet sequence over a network, the system comprising:
a host software stack comprising a module implementing a partial offload of one or more functionalities defined by a network communication protocol comprising Remote Direct Memory Access (RDMA); and
a device coupled to the host software stack and comprising hardware configured to support the partial offload, the device comprising a transmit interface configured to receive a request for transmitting a packet sequence from the host software stack and generate a transmit descriptor based on the request, the transmit descriptor including information for creating individual packets from the packet sequence, each packet having a format defined by the network communication protocol.
15. The system of claim 14, wherein the transmit descriptor comprises header information, a total transmit size of the packet sequence, a frame size for each packet to be created, a start point of packet sequence number (PSN) and a list of host buffers for obtaining payload data.
16. The system of claim 15, wherein the device further comprises a transmit offload processor coupled to the transmit interface and configured for receiving the transmit descriptor from the transmit interface and creating the individual packets from the packet sequence based on the information in the transmit descriptor.
17. The system of claim 16, wherein the transmit offload processor, in creating individual packets from the packet sequence, creates an Ethernet header, a Global Routing Header (GRH) and one or more transport layer headers for each packet frame based on the header information in the transmit descriptor.
18. The system of claim 16, wherein the transmit offload processor, in creating individual packets from the packet sequence, acquires payload data from the list of host buffers in the transmit descriptor.
19. The system of claim 16, wherein the transmit offload processor, in creating individual packets from the packet sequence, performs an Invariant CRC calculation and insertion in each packet frame.
20. (canceled)
21. (canceled)
22. The system of claim 14, wherein the device is further configured for receiving a packet over the network and parsing the packet in accordance with the network communication protocol.
23. (canceled)
24. The system of claim 14, wherein the network communication protocol is a RDMA (remote direct memory access) over the Converged Ethernet (RoCE) protocol.
25. (canceled)
26. The system of claim 24, wherein the host software stack further comprises a RoCE software stack coupled to and in communication with the software module implementing the partial offload, the RoCE software stack configured for handling details of the RoCE protocol.
27. The system of claim 14, further comprising an Ethernet driver or a NIC (network interface controller) coupled to and in communication with the software module implementing the partial offload, the Ethernet driver or NIC further coupled to the device and configured to send the request for transmitting the packet sequence to the device.
28. A network device comprising:
a transmit interface operable to read, from a host memory, a transmit request and associated header information, the associated header information comprising a packet sequence number (PSN) and a list of host buffers for obtaining payload data; and
an offload processor operable to generate, in response to the transmit request, a data packet, the offload processor being operable to transmit the data packet over a data network to at least one data network address,
wherein the data packet comprises the associated header information and is generated according to a direct memory access protocol.
29. The network device in claim 28, wherein the transmit descriptor comprises the associated header information, a total transmit size of the packet sequence, a frame size for each packet to be created, the packet sequence number (PSN) and the list of host buffers for obtaining payload data.
30. The network device in claim 29, wherein the offload processor is coupled to the network interface and configured for receiving the transmit descriptor from the network interface and creating the data packet based on the information in the transmit descriptor.
31. The network device in claim 30, wherein the offload processor, in creating the data packet, creates an Ethernet header, a Global Routing Header (GRH) and one or more transport layer headers based on the header information in the transmit descriptor.
32. The network device in claim 30, wherein the offload processor, in creating the data packet, acquires payload data from the list of host buffers in the transmit descriptor.
33. The network device in claim 30, wherein the offload processor, in creating the data packet, performs an Invariant CRC calculation and insertion in the data packet.
34. (canceled)
35. The network device in claim 28, the network device comprising a receive interface configured for receiving a packet sent from the network to a host.
36. The network device in claim 35, wherein the offload processor is coupled to the receive interface and configured for receiving the packet from the receive interface and parsing the packet in accordance with a network communication protocol, the offload processor further configured for performing an Invariant CRC validation and inserting a validation result in a receive descriptor, the receive descriptor transmitted to the host to avoid additional Invariant CRC validation in the host.
37. The network device in claim 28, wherein the direct memory access protocol is a RDMA (remote direct memory access) over the Converged Ethernet (RoCE) protocol, and the network is the converged Ethernet.
38-49. (canceled)
50. A network device comprising:
an interface operably coupled to a host, the host implementing one or more elements of a Remote Direct Memory Access (RDMA) protocol; and
an offload processor operably coupled to the interface, the offload processor being a hardware device configured to receive a request for transmitting a packet sequence from the host and configured generate a transmit descriptor based on the request, the transmit descriptor including information for creating individual packets from the packet sequence, each individual packet having a format defined by the RDMA protocol.

1. A method for encoding a bit stream to meet a minimum bit transition requirement, comprising the steps of:
providing uncoded bits;
determining whether the uncoded bits meet the minimum bit transition requirement; and
replacing selected bits in the uncoded bits with replacement bits that meet the minimum bit transition requirement if the uncoded bits do not meet the minimum bit transition requirement, thereby encoding the uncoded bits into encoded bits that meet the minimum bit transition requirement, wherein the replacement bits invert at least two of the selected bits, and the selected bits and the replacement bits have the same bit length which is less than the bit length of the uncoded bits.
2. The method of claim 1, wherein the selected bits are consecutive bits.
3. The method of claim 2, wherein the uncoded bits exceed a maximum run length limitation.
4. The method of claim 2, including maintaining the uncoded bits that meet the minimum bit transition requirement even though the uncoded bits exceed a maximum run length limitation.
5. The method of claim 1, including storing the encoded bits as magnetic-polarity transitions on a disk.
6. The method of claim 5, including reading the magnetic-polarity transitions from the disk to retrieve the encoded bits.
7. The method of claim 6, including replacing the replacement bits in the encoded bits read from the disk with the selected bits based on an ECC computation performed on the encoded bits read from the disk, thereby decoding the encoded bits into the uncoded bits.
8. The method of claim 7, including sending data bits in the uncoded bits decoded from the encoded bits to a host computer.
9. The method of claim 8, wherein the replacement bits inject errors into the uncoded bits that increase timing information in the uncoded bits such that the encoded bits have sufficient timing information for phase locking on the encoded bits as the encoded bits are read from the disk regardless of whether the encoded bits exceed a maximum run length limitation.
10. A method for encoding a bit stream to meet a minimum bit transition requirement, comprising the steps of:
providing uncoded bits;
analyzing the uncoded bits by:
determining a first value based on first bit transitions in the uncoded bits;
determining a second value based on second bit transitions in the uncoded bits;
generating a combination value as a function of the first and second values; and
determining whether the combination value meets the minimum bit transition requirement; and

replacing selected bits in the uncoded bits with replacement bits that meet the minimum bit transition requirement if the combination value fails to meet the minimum bit transition requirement, thereby encoding the uncoded bits into encoded bits that meet the minimum bit transition requirement, wherein the replacement bits invert at least two of the selected bits, and the selected bits and the replacement bits have the same bit length which is less than the bit length of the uncoded bits.
11. The method of claim 10, including generating the combination value by averaging values that include the first and second values.
12. The method of claim 10, wherein the first value is based on a first set of m uncoded bits that includes the first bit transitions and is designated by a sliding window of m bits, and the second value is based on a second set of m uncoded bits that includes the second bit transitions and is designated by the sliding window.
13. The method of claim 10, wherein the first value is based on the number of the first bit transitions, and the second value is based on the number of the second bit transitions.
14. The method of claim 10, wherein step the first value is a function of the slope of a waveform based on the first bit transitions, and the second value is a function of the slope of a waveform based on the second bit transitions.
15. The method of claim 10, wherein the first value is a function of the slope squared of a waveform based on the first bit transitions, and the second value is a function of the slope squared of a waveform based on the second bit transitions.
16. The method of claim 15, wherein the slope squared of each waveform corresponds to the amount of timing information in the waveform.
17. The method of claim 10, including storing the encoded bits magnetic-polarity transitions on a disk.
18. The method of claim 17, including reading the magnetic-polarity transitions from the disk to retrieve the encoded bits.
19. The method of claim 18, including replacing the replacement bits in the encoded bits read from the disk with the selected bits based on an ECC computation performed on the encoded bits read from the disk, thereby decoding the encoded bits into the uncoded bits.
20. The method of claim 19, including sending data bits in the uncoded bits decoded from the encoded bits to a host computer.
21. The method of claim 20, wherein the replacement bits inject errors into the uncoded bits that increase timing information in the uncoded bits such that the encoded bits have sufficient timing information for phase locking on the encoded bits as the encoded bits are read from the disk regardless of whether the encoded bits exceed a maximum run length limitation.
22. A method for encoding a bit stream to meet a minimum bit transition requirement, comprising the steps of:
providing uncoded bits;
analyzing the uncoded bits by:
establishing a sliding window for m uncoded bits;
accumulating a moving sum based on the bit transitions in each set of m uncoded bits designated by the sliding window; and
comparing the moving sum to a threshold based on the minimum bit transition requirement; and

replacing selected bits in the uncoded bits with replacement bits that meet the minimum bit transition requirement if the moving sum fails to meet the threshold, thereby encoding the uncoded bits into encoded bits that meet the minimum bit transition requirement, wherein the replacement bits invert at least two of the selected bits, and the selected bits and the replacement bits have the same bit length which is less than the bit length of the uncoded bits.
23. The method of claim 22, including replacing more than m uncoded bits with the replacement bits.
24. The method of claim 22, including accumulating the moving sum of the slope squared of a waveform based on each set of m uncoded bits, wherein the slope squared is a function of the bit transitions in the waveform.
25. The method of claim 24, including determining the slope squared for a set of m consecutive bits includes the steps of determining the slope of the waveform and generating the square of the slope.
26. The method of claim 24, wherein determining the slope includes differentiating the waveform.
27. The method of claim 24, wherein determining the slope squared includes accessing a look-up table that includes a corresponding slope squared for each m uncoded bit sequence.
28. The method of claim 24, wherein the slope squared is quantized to two levels.
29. The method of claim 22, including storing the encoded bits, as magnetic-polarity transitions on a disk.
30. The method of claim 29, including reading the magnetic-polarity transitions from the disk to retrieve the encoded bits.
31. The method of claim 30, including replacing the replacement bits in the encoded bits read from the disk with the selected bits based on an ECC computation performed on the encoded bits read from the disk, thereby decoding the encoded bits into the uncoded bits.
32. The method of claim 31, including sending data bits in the uncoded bits decoded from the encoded bits to a host computer.
33. The method of claim 32, wherein the replacement bits inject errors into the uncoded bits that increase timing information in the uncoded bits such that the encoded bits have sufficient timing information for phase locking on the encoded bits as the encoded bits are read from the disk regardless of whether the encoded bits exceed a maximum run length limitation.
34. The method of claim 22, including accumulating the moving sum of the number of bit transitions in each set of m uncoded bits.
35. The method of claim 34, including replacing more than m uncoded bits with the replacement bits.
36. A method for encoding a bit stream to meet a minimum bit transition requirement, comprising the steps of:
providing data bits;
performing an ECC computation on the data bits to generate ECC bits;
forming uncoded bits that include the data bits and the ECC bits;
randomizing the uncoded bits;
determining whether the randomized uncoded bits meet the minimum bit transition requirement; and
replacing selected bits in the randomized uncoded bits with replacement bits that meet the minimum bit transition requirement if the randomized uncoded bits do not meet the minimum bit transition requirement, thereby encoding the randomized uncoded bits into randomized encoded bits that meet the minimum bit transition requirement, wherein the replacement bits invert at least two of the selected bits, and the selected bits and the replacement bits have the same bit length which is less than the bit length of the uncoded bits.
37. The method of claim 36, including the repeating the method and storing a number of replacements by counting the number of times that the replacements bits replace the selected bits.
38. The method of claim 37, including performing the randomizing using a seed.
39. The method of claim 38 wherein the seed is a default seed.
40. The method of claim 39, including performing the randomizing using another seed instead of the default seed if the number of replacements exceeds a predetermined value.
41. The method of claim 37, including counting the number of replacements per data sector on a disk.
42. The method of claim 36, wherein the randomizing is Galois field randomizing.
43. The method of claim 36, including storing the randomized encoded bits as magnetic-polarity transitions on a disk.
44. The method of claim 43, including reading the magnetic-polarity transitions from the disk to retrieve the randomized encoded bits.
45. The method of claim 44, including derandomizing the randomized encoded bits read from the disk.
46. The method of claim 45, including replacing the replacement bits in the derandomized encoded bits with the selected bits based on an ECC computation performed on the derandomized encoded bits, thereby decoding the encoded bits into the uncoded bits.
47. The method of claim 46, including sending the data bits in the uncoded bits decoded from the encoded bits to a host computer.
48. The method of claim 44, including derandomizing the randomized encoded bits read from the disk using a default seed.
49. The method of claim 48, including derandomizing the randomized encoded bits read from the disk using a different seed than the default seed.
50. A data storage device for storing data on storage media and retrieving data from the storage media, comprising:
a buffer for storing uncoded bits that include data bits and ECC bits; and
a controller that encodes the uncoded bits to meet a minimum bit transition requirement, wherein the controller determines whether the uncoded bits meet the minimum bit transition requirement, and the controller replaces selected bits in the uncoded bits with replacement bits that meet the minimum bit transition requirement if the uncoded bits do not meet the minimum bit transition requirement, thereby encoding the uncoded bits into encoded bits that meet the minimum bit transition requirement, wherein the replacement bits invert at least two of the selected bits, and the selected bits and the replacement bits have the same bit length which is less than the bit length of the uncoded bits.
51. The data storage device of claim 50, wherein the selected bits are consecutive bits.
52. The data storage device of claim 51, wherein the controller determines whether the uncoded bits meet the minimum bit transition requirement even though the uncoded bits exceed a maximum run length limitation.
53. The data storage device of claim 51, wherein the controller maintains the uncoded bits if the uncoded bits meet the minimum bit transition requirement even though the uncoded bits exceed a maximum run length limitation.
54. The data storage device of claim 50, wherein the controller stores the encoded bits as magnetic-polarity transitions on the storage media.
55. The data storage device of claim 54, wherein upon read back of the magnetic-polarity transitions from the storage media the controller retrieves the encoded bits.
56. The data storage device of claim 55, wherein the controller replaces the replacement bits in the encoded bits read from the storage media with the selected bits based on an ECC computation performed on the encoded bits read from the storage media, thereby decoding the encoded bits into the uncoded bits.
57. The data storage device of claim 56, wherein the controller sends the data bits in the uncoded bits decoded from the encoded bits to a host computer.
58. The data storage device of claim 57, wherein the replacement bits inject errors into the uncoded bits that increase timing information in the uncoded bits such that the encoded bits have sufficient timing information for phase locking on the encoded bits as the encoded bits are read from the storage media regardless of whether the encoded bits exceed a maximum run length limitation.
59. The data storage device of claim 50, wherein the controller (i) determines a first value based on first bit transitions in the uncoded bits, (ii) determines a second value based on second bit transitions in the uncoded bits, (iii) generates a combination value as a function the first and second values, (iv) determines whether the combination value meets the minimum bit transition requirement, and (v) replaces the selected said first andor second number of bits with the replacement bits if the combination value fails to meet the minimum bit transition requirement.
60. The data storage device of claim 59, wherein the controller generates the combination value by averaging values that include the first and second values.
61. The data storage device of claim 59, wherein the controller determines the first value based on a first set of m uncoded bits that includes the first bit transitions and is designated by a sliding window of m bits, and determines the second value based on a second set of m uncoded bits that includes the second bit transitions and is designated by the sliding window.
62. The data storage device of claim 59, wherein the controller determines the first value based on the number of the first bit transitions, and determines the second value based on the number of the second bit transitions.
63. The data storage device of claim 59, wherein the controller determines the first value as function of the slope of a waveform based on the first bit transitions, and determines the second value as a function of the slope of a waveform based on the second bit transitions.
64. The data storage device of claim 59, wherein the controller determines the first value as a function of the slope squared of a waveform based on the first bit transitions, and determines the second value as a function of the slope squared of a waveform based on the second bit transitions.
65. The data storage device of claim 50, wherein the controller (i) obtains the uncoded bits, (ii) establishes a sliding window for m uncoded bits, (iii) accumulates a moving sum of values based on the bit transitions in each set of m uncoded bits, (iv) compares the moving sum to a threshold based on the minimum bit transition requirement, and (v) replaces the selected bits with the replacement bits if the moving sum fails to meet the threshold.
66. The data storage device of claim 65, wherein the replacement bits are more than m bits.
67. The data storage device of claim 65, wherein the moving sum is the slope squared of a waveform based on each set of m bits.
68. The data storage device of claim 67, wherein the controller determines the slope squared by determining the slope of the waveform and generating the square of the slope.
69. The data storage device of claim 67, wherein the controller determines the slope by differentiating the waveform.
70. The data storage device of claim 67, wherein the controller determines the slope squared by accessing a look-up table that includes a corresponding sloped squared for each m bit sequence.
71. A method for encoding and decoding a bit stream in a disk drive that includes a disk, the method comprising the following steps in the sequence set forth:
providing uncoded bits that include data bits and ECC bits;
determining whether the uncoded bits meet a minimum bit transition requirement;
replacing selected bits in the uncoded bits with replacement bits that meet the minimum bit transition requirement if the uncoded bits do not meet the minimum bit transition requirement, thereby encoding the uncoded bits into encoded bits that meet the minimum bit transition requirement, wherein the replacement bits invert at least two of the selected bits, and the selected bits and the replacement bits have the same bit length which is less than the bit length of the uncoded bits;
storing the encoded bits on the disk;
reading the encoded bits from the disk;
generating the selected bits using an ECC computation performed on the encoded bits read from the disk; and
replacing the replacement bits in the encoded bits read from the disk with the generated selected bits, thereby decoding the encoded bits into the uncoded bits.
72. The method of claim 71, wherein the data bits are arranged as data symbols, the ECC bits are arranged as ECC symbols, and the uncoded bits include the data symbols and the ECC symbols.
73. The method of claim 72, wherein the selected bits are a selected symbol from the data symbols and the ECC symbols, and the replacement bits replace the selected symbol.
74. The method of claim 73, wherein the selected symbol is a data symbol.
75. The method of claim 73, wherein the selected symbol is an ECC symbol.
76. The method of claim 71, wherein the selected bits are consecutive bits.
77. The method of claim 71, wherein the replacement bits are predetermined.
78. The method of claim 71, wherein the replacement bits are not based on the uncoded bits.
79. The method of claim 71, wherein the replacement bits inject errors into the uncoded bits.
80. The method of claim 71, wherein the replacement bits increase timing information in the uncoded bits.
81. The method of claim 71, wherein the replacement bits inject errors into the uncoded bits that increase timing information in the uncoded bits.
82. The method of claim 71, wherein the replacement bits inject errors into the uncoded bits that increase timing information in the uncoded bits such that the encoded bits have sufficient timing information regardless of whether the encoded bits exceed a maximum run length limitation.
83. The method of claim 71, wherein the replacement bits inject errors into the uncoded bits that increase timing information in the uncoded bits such that the encoded bits have sufficient timing information for phase locking on the encoded bits as the encoded bits are read from the disk regardless of whether the encoded bits exceed a maximum run length limitation.
84. The method of claim 71, wherein the replacement bits improve phase locking on the encoded bits as the encoded bits are read from the disk.
85. The method of claim 71, wherein the replacement bits are alternating pairs of 1’s and 0’s.
86. The method of claim 85, wherein the replacement bits are 0011001100.
87. The method of claim 85, wherein the replacement bits are 1100110011.
88. The method of claim 71, wherein the minimum bit transition requirement is a function of the location of the uncoded bits in a data block.
89. The method of claim 88, wherein the minimum bit transition requirement is more difficult at the beginning of the data block that at the end of the data block.
90. The method of claim 89, wherein the minimum bit transition requirement is more difficult at about the first 1000 to 2000 uncoded bits in the data block than at the remaining uncoded bits in the data block.
91. The method of claim 88, wherein the minimum bit transition requirement is adaptive and selected as the data block is written to the disk.
92. The method of claim 71, wherein the minimum bit transition requirement is a function of the disk and a transducer that reads from and writes to the disk.
93. The method of claim 71, wherein the minimum bit transition requirement is a function of recording zones on the disk.
94. The method of claim 71, wherein determining whether the uncoded bits meet the minimum bit transition requirement includes:
sampling m uncoded bits using an m bit sliding window to obtain sets of m uncoded bits;
obtaining values from the sets of m uncoded bits, wherein each obtained value is obtained from a corresponding set of m uncoded bits;
determining a combination value based on the obtained values; and
comparing the combination value with a threshold.
95. The method of claim 94, wherein the combination value is a moving average of the obtained values.
96. The method of claim 95, wherein each obtained value is based on the number of bit transitions in the corresponding set of m uncoded bits.
97. The method of claim 95, wherein each obtained value is based on the slope of a waveform derived from the corresponding set of m uncoded bits.
98. The method of claim 95, wherein each obtained value is based on the slope squared of a waveform derived from the corresponding set of m uncoded bits.
99. The method of claim 71, including:
randomizing the uncoded bits;
encoding the randomized uncoded bits;
storing the randomized encoded bits on the disk;
reading the randomized encoded bits from the disk; and
derandomizing the randomized encoded bits read from the disk to provide the encoded bits.
100. The method of claim 71, including:
receiving the data bits from a host computer; then
providing the uncoded bits; and then
sending the data bits in the uncoded bits decoded from the encoded bits to the host computer.
101. A method for encoding and decoding a bit stream in a disk drive that includes a disk, the method comprising the following steps in the sequence set forth:
providing uncoded bits that include data bits and ECC bits;
determining whether the uncoded bits meet a minimum bit transition requirement;
replacing selected bits in the uncoded bits with replacement bits that meet the minimum bit transition requirement if the uncoded bits do not meet the minimum bit transition requirement, thereby encoding the uncoded bits into encoded bits that meet the minimum bit transition requirement, wherein the replacement bits invert at least two of the selected bits to inject errors into the uncoded bits that increase timing information in the uncoded bits, and the selected bits and the replacement bits have the same bit length which is less than the bit length of the uncoded bits;
storing the encoded bits on the disk;
reading the encoded bits from the disk, wherein the replacement bits improve phase locking on the encoded bits as the encoded bits are read from the disk due to the increased timing information in the encoded bits;
generating the selected bits using an ECC computation performed on the encoded bits read from the disk; and
replacing the replacement bits in the encoded bits read from the disk with the generated selected bits, thereby decoding the encoded bits into the uncoded bits.
102. The method of claim 101, wherein the replacement bits are predetermined.
103. The method of claim 101, wherein the minimum bit transition requirement is a function of the location of the uncoded bits in a data block.
104. The method of claim 103, wherein the minimum bit transition requirement is more difficult at the beginning of the data block than at the end of the data block.
105. The method of claim 101, wherein determining whether the uncoded bits meet the minimum bit transition requirement includes:
sampling m uncoded bits using an m bit sliding window to obtain sets of m uncoded bits;
obtaining values from the sets of m uncoded bits, wherein each obtained value is obtained from a corresponding set of m uncoded bits;
determining a combination value based on the obtained values; and
comparing the combination value with a threshold.
106. The method of claim 105, wherein the combination value is a moving average of the obtained values.
107. The method of claim 106, wherein each obtained value is based on the slope of a waveform derived from the corresponding set of m uncoded bits.
108. The method of claim 106, wherein each obtained value is based on the slope squared of a waveform derived from the corresponding set of m uncoded bits.
109. The method of claim 101, including:
randomizing the uncoded bits;
encoding the randomized uncoded bits;
storing the randomized encoded bits on the disk;
reading the randomized encoded bits from the disk; and
derandomizing the randomized encoded bits read from the disk to provide the encoded bits.
110. The method of claim 101, including:
receiving the data bits from a host computer; then
providing the uncoded bits; and then
sending the data bits in the uncoded bits decoded from the encoded bits to the host computer.
111. A method for encoding and decoding a bit stream in a disk drive that includes a disk, the method comprising the following steps in the sequence set forth:
providing uncoded bits that include data bits and ECC bits, wherein the data bits are arranged as data symbols, the ECC bits are arranged as ECC symbols, and the uncoded bits include the data symbols and the ECC symbols;
determining whether the uncoded bits meet a minimum bit transition requirement;
replacing selected bits in the uncoded bits with replacement bits that meet the minimum bit transition requirement if the uncoded bits do not meet the minimum bit transition requirement, thereby encoding the uncoded bits into encoded bits that meet the minimum bit transition requirement, wherein the selected bits are a selected symbol from the data symbols and the ECC symbols, the replacement bits invert at least two of the selected bits to inject errors into the uncoded bits that increase timing information in the uncoded bits, and the selected bits and the replacement bits have the same bit length which is less than the bit length of the uncoded bits;
storing the encoded bits on the disk;
reading the encoded bits from the disk, wherein the replacement bits improve phase locking on the encoded bits as the encoded bits are read from the disk due to the increased timing information in the encoded bits;
generating the selected bits using an ECC computation on the encoded bits read from the disk; and
replacing the replacement bits in the encoded bits read from the disk with the generated selected bits, thereby decoding the encoded bits into the uncoded bits.
112. The method of claim 111, wherein the replacement bits are predetermined.
113. The method of claim 111, wherein the minimum bit transition requirement is a function of the location of the uncoded bits in a data block.
114. The method of claim 113, wherein the minimum bit transition requirement is more difficult at the beginning of the data block than at the end of the data block.
115. The method of claim 111, wherein determining whether the uncoded bits meet the minimum bit transition requirement includes:
sampling m uncoded bits using an m bit sliding window to obtain sets of m uncoded bits;
obtaining values from the sets of m uncoded bits, wherein each obtained value is obtained from a corresponding set of m uncoded bits;
determining a combination value based on the obtained values; and
comparing the combination value with a threshold.
116. The method of claim 115, wherein the combination value is a moving average of the obtained values.
117. The method of claim 116, wherein each obtained value is based on the slope of a waveform derived from the corresponding set of m uncoded bits.
118. The method of claim 116, wherein each obtained value is based on the slope squared of a waveform derived from the corresponding set of m uncoded bits.
119. The method of claim 111, including:
randomizing the uncoded bits;
encoding the randomized uncoded bits;
storing the randomized encoded bits on the disk;
reading the randomized encoded bits from the disk; and
derandomizing the randomized encoded bits read from the disk to provide the encoded bits.
120. The method of claim 111, including:
receiving the data bits from a host computer; then
providing the uncoded bits; and then
sending the data bits in the uncoded bits decoded from the encoded bits to the host computer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A service provider system, comprising:
a non-transitory memory storing a user credential for a user, a first key, a second key, and an authorization; and
one or more hardware processors coupled to the non-transitory memory and configured to read instructions from the non-transitory memory to cause the system to perform the steps of:
receiving the user credential from a merchant device corresponding to a merchant, wherein the user credential is transmitted using the first key previously provided to the merchant device;
verifying that the first key used to transmit the user credential is associated with the merchant;
providing the authorization to the merchant device based on the user credential and the first key;
receiving the authorization from the merchant device, wherein the authorization is transmitted using the second key previously provided to the merchant device; and
processing a transaction between the user and the merchant based on the first key and the second key both corresponding to the merchant.
2. The system of claim 1, wherein the second key is protected from access on the merchant device.
3. The system of claim 1, wherein the first key is used in at least one of a merchant application for the merchant and a merchant website for the merchant.
4. The system of claim 1, wherein the transaction is processed using a payment account for the user with the service provider, and wherein the user credential identifies the payment account.
5. The system of claim 4, wherein the user credential comprises a PIN issued to the user by the service provider that is distinct from at least one of a username for the payment account and a password for the payment account.
6. The system of claim 5, wherein the user establishes the PIN with the payment account for use in identifying the payment account during merchant transactions including the transaction with the merchant.
7. The system of claim 6, wherein the authorization is provided in response to the PIN being matched to the user and the first key being matched to the merchant.
8. The system of claim 1, wherein the one or more hardware processors are further configured to cause the system to further perform the steps of:
providing payment to the merchant in response to the merchant being identified by the first key matching the second key.
9. The system of claim 1, wherein the processing comprises:
determining that the second key was previously issued to the merchant; and
in response, processing the transaction using a payment account of the user with the service provider.
10. The system of claim 1, wherein the processing comprises:
receiving the authorization from the merchant device;
determining that the authorization is not transmitted using the second key previously issued to the merchant; and
in response, marking at least one of the transaction, the merchant device, and the merchant as fraudulent.
11. A method comprising:
receiving a user credential for a user from a merchant device corresponding to a merchant, wherein the user credential is transmitted using a first key previously provided to the merchant device;
verifying that the first key used to transmit the user credential is associated with the merchant;
providing an authorization to the merchant device based on the user credential and the first key;
receiving the authorization from the merchant device, wherein the authorization is transmitted using a second key previously provided to the merchant device; and
processing a transaction between the user and the merchant when the first key and the second key correspond to the merchant.
12. The method of claim 11, wherein the second key is protected from access on the merchant device, and wherein the first key is used in at least one of a merchant application for the merchant and a merchant website for the merchant.
13. The method of claim 11, wherein the transaction is processed using a payment account for the user with the service provider, and wherein the user credential identifies the payment account.
14. The method of claim 13, wherein the user credential comprises a PIN issued to the user by the service provider that is distinct from at least one of a username for the payment account and a password for the payment account.
15. The method of claim 14, wherein the user establishes the PIN with the payment account for use in identifying the payment account during merchant transactions including the transaction with the merchant.
16. The method of claim 15, wherein the authorization is provided in response to the PIN being matched to the user and the first key being matched to the merchant.
17. The method of claim 11, further comprising:
providing payment to the merchant in response to the merchant being identified by the first key matching the second key.
18. The method of claim 11, wherein the processing comprises:
determining that the second key was previously issued to the merchant; and
in response, processing the transaction using a payment account of the user with the service provider.
19. The method of claim 11, wherein the processing comprises:
receiving the authorization from the merchant device;
determining that the authorization is not transmitted using the second key previously issued to the merchant; and
in response, marking at least one of the transaction, the merchant device, and the merchant as fraudulent.
20. A non-transitory machine-readable medium having stored thereon machine-readable instructions executable to cause a machine to perform operations comprising:
receiving a user credential for a user from a merchant device corresponding to a merchant, wherein the user credential is transmitted using a first key previously provided to the merchant device;
verifying that the first key used to transmit the user credential is associated with the merchant;
providing an authorization to the merchant device based on the user credential and the first key;
receiving the authorization from the merchant device, wherein the authorization is transmitted using a second key previously provided to the merchant device; and
processing a transaction between the user and the merchant when the first key and the second key correspond to the merchant.