Author: claimsbot

1. An apparatus for storing data of Radio Frequency Identification (RFID) tags having sensors, comprising:
a controlling means for controlling the data from the sensors to be stored; and
a storing means for storing the data from the sensors,
wherein the storing means includes:
a first storing unit which includes a kill password storage storing a kill password that an RFID reader transmits to an RFID tag in order to halt operation of the RFID tag, and an access password storage storing an access password of the tag;
a second storing unit which includes an Electronic Product Code (EPC) storage storing a code for identifying an object having the tag, a protocol control storage having physical-layer information of the code storage, and an error check storage storing a Cyclic Redundancy Checking (CRC) code for detecting a transmission error;
a third storing unit which includes a tag identifier storage storing a tag identifier including a manufacture model and a serial number of the tag; and
a fourth storing unit which includes an initial sensor data storage storing initial information of the sensor, a real-time information storage storing information of year, month, day, time, minute and second, a maximumminimum data storage storing maximumminimum values compared to set up an excessvalidity region of the sensing data, and a sensor data storage storing sensing data actually measured through the sensor embedded in the RFID tag.
2. The apparatus as recited in claim 1, wherein initial information of the sensor includes type information of the sensor embedded in the tag, type information of the tag including the sensor, and sensing time interval information of the tag including the sensor.
3. The apparatus as recited in claim 1, wherein in a process for storing data acquired from the sensor embedded in the tag in data storing apparatus for the RFID tags with sensors, sensing data inputted in real-time are comparedcalculated with the maximumminimum values of the maximumminimum data storage, and the sensing values of the maximumminimum excess regions are stored in the RFID tag data storing apparatus.
4. The apparatus as recited in claim 3, wherein when the sensing value of the maximumminimum excess regions are stored, and only the corresponding value is stored by a command of a reader or a value pre-designated when the tag is manufactured.
5. The apparatus as recited in claim 1, wherein in a process for storing data acquired from the sensor embedded in the tag in the data storing apparatus for RFID tags with sensors, sensing data inputted in real-time are comparedcalculated with the maximumminimum values of the maximumminimum data storage, and the sensing value of only a validity region is stored.
6. The apparatus as recited in claim 1, wherein in a process for storing data acquired from the sensor embedded in the tag in the data storing apparatus for RFID tags with sensors, only a difference between neighboring two data inputted in real-time is stored.
7. A method for storing data of Radio Frequency Identification (RFID) tags having sensors, comprising the steps of:
a) controlling the data from the sensors to be stored on a storing means,
wherein the storing means includes:
a kill password storage storing a kill password that an RFID reader transmits to an RFID tag in order to halt operation of the RFID tag, and an access password storage storing an access password of the tag;
an Electronic Product Code (EPC) storage storing a code for identifying an object having the tag, a protocol control storage having physical-layer information of the code storage, and storing a Cyclic Redundancy Checking (CRC) code for detecting a transmission error;
a tag identifier storage storing a tag identifier having a manufacture model and a serial number of the tag; and
an initial sensor data storage storing initial information of the sensor, storing information of year, month, day, time, minute and second, storing maximumminimum values compared to set up an excessvalidity region of the sensing data, and storing sensing data actually measured through the sensor embedded in the RFID tag.
8. The method as recited in claim 7, wherein initial information of the sensor includes type information of the sensor embedded in the tag, type information of the tag including the sensor, and sensing time interval information of the tag including the sensor.
9. The method as recited in claim 7, wherein in a process for storing data acquired from the sensor embedded in the tag in data storing apparatus for the RFID tags with sensors, sensing data inputted in real-time are comparedcalculated with the maximumminimum values of the maximumminimum data storage, and the sensing values of the maximumminimum excess regions are stored in the RFID tag data storing apparatus.
10. The method as recited in claim 9, wherein when the sensing value of the maximumminimum excess regions are stored, and only the corresponding value is stored by a command of a reader or a value pre-designated when the tag is manufactured.
11. The method as recited in claim 7, wherein in a process for storing data acquired from the sensor embedded in the tag in the data storing apparatus for RFID tags with sensors, sensing data inputted in real-time are comparedcalculated with the maximumminimum values of the maximumminimum data storage, and the sensing value of only a validity region is stored.
12. The method as recited in claim 7, wherein in a process for storing data acquired from the sensor embedded in the tag in the data storing apparatus for RFID tags with sensors, only a difference between neighboring two data inputted in real-time is stored.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A method of operating a processor comprising:
running one or more program applications concurrently;
executing a plurality of execution threads in a multiple-thread pipeline including a plurality of multiple-bit flip-flops that hold the plurality of execution threads, the execution threads for executing issued instructions for the program applications;
switching the execution threads in the multiple-thread pipeline including:
freezing an active state in the pipeline;
activating a previously idle thread in the pipeline while holding the state of the newly frozen thread in the pipeline; and
subsequently resuming execution of the frozen thread at the precise state of the frozen thread immediately prior to the thread switch.
2. A method according to claim 1 wherein:
the multiple-thread pipeline includes a plurality of pulse-based high-speed flip-flops, the pulse-based high-speed flip-flops having a latch structure coupled to a plurality of select-bus lines, the select-bus lines selecting an active thread from among the plurality of execution threads.
3. A method according to claim 1 wherein executing a plurality of execution threads in a multiple-thread pipeline includes:
latching data in pulse-based high-speed flip-flops; and
selecting an active thread from among the plurality of execution threads using select-bus lines.
4. A method according to claim 1 further comprising:
detecting a cache miss;
generating a cache miss stall signal in response to the cache miss stall; and
freezing an active state in the pipeline in response to the cache miss stall signal.
5. A method according to claim 1 further comprising:
issuing instructions for the program applications in-order.
6. A method according to claim 1 further comprising:
issuing instructions for the program applications in-order; and
managing a machine state of the individual execution threads separately and independently.
7. A method according to claim 1 further comprising:
loading data from a storage and storing data to a storage via a plurality of loadstore units that are individually allocated to individual threads in the multiple-thread pipeline.
8. A method according to claim 1 further comprising:
concurrently executing a plurality of execution threads in a plurality of multiple-thread pipelines so that the processor executes the one or more program applications with vertical threading and horizontal threading.
9. A method of operating a processor comprising:
running one or more program applications concurrently;
executing a plurality of execution threads in a multiple-thread pipeline including a plurality of multiple-bit flip-flops that hold the plurality of execution threads, the execution threads for executing issued instructions for the program applications, the executing operation including:
holding a plurality of threads in the multiple-thread pipeline simultaneously including an active thread and one or more inactive threads; receiving notification of a stall condition;
in response to receipt of the stall condition, stalling the active thread immediately including immediately deactivating a currently active thread and activating a currently inactive thread while the state of the threads in the multiple-thread pipeline remains the same.
10. A method according to claim 9 wherein:
the multiple-thread pipeline includes a plurality of pulse-based high-speed flip-flops, the pulse-based high-speed flip-flops having a latch structure coupled to a plurality of select-bus lines, the select-bus lines selecting an active thread from among the plurality of execution threads.
11. A method according to claim 9 wherein executing a plurality of execution threads in a multiple-thread pipeline includes:
latching data in pulse-based high-speed flip-flops; and
selecting an active thread from among the plurality of execution threads using select-bus lines.
12. A method according to claim 9 further comprising:
detecting a cache miss;
generating a cache miss stall signal in response to the cache miss stall; and
freezing an active state in the pipeline in response to the cache miss stall signal.
13. A method according to claim 9 further comprising:
issuing instructions for the program applications in-order.
14. A method according to claim 9 further comprising:
issuing instructions for the program applications in-order; and
managing a machine state of the individual execution threads separately and independently.
15. A method according to claim 9 further comprising:
loading data from a storage and storing data to a storage via a plurality of loadstore units that are individually allocated to individual threads in the multiple-thread pipeline.
16. A method according to claim 9 further comprising:
concurrently executing a plurality of execution threads in a plurality of multiple-thread pipelines so that the processor executes the one or more program applications with vertical threading and horizontal threading.
17. A method of operating a processor comprising:
running a non-threaded program application;
executing the non-threaded program in a multiple-thread pipeline including a plurality of multiple-bit flip-flops that are capable of holding a plurality of execution threads;
switching context in a fast context switching operation including:
executing a first context in a first thread pathway in the multiple-thread pipeline;
receiving an exception condition signal;
in response to receipt of the exception condition signal, stalling the first context immediately including immediately deactivating the first context and activating an exception handler context while the state of the contexts in the multiple-thread pipeline remains the same.
18. A method according to claim 17 wherein:
the exception handler context is activated without operating system penalty.
19. A method according to claim 17 wherein:
the exception handler context is activated in hardware without incurring operating system speed penalty of software saverestore operations.
20. A method according to claim 17 wherein:
the multiple-thread pipeline includes a plurality of pulse-based high-speed flip-flops, the pulse-based high-speed flip-flops having a latch structure coupled to a plurality of select-bus lines, the select-bus lines selecting an active thread from among the plurality of execution threads.
21. A method according to claim 17 wherein executing a context in a multiple-thread pipeline includes:
latching data in pulse-based high-speed flip-flops; and
selecting an active thread from among the plurality of execution threads using select-bus lines.
22. A method according to claim 17 further comprising:
detecting a cache miss;
generating a cache miss stall signal in response to the cache miss stall; and
freezing an active state in the pipeline in response to the cache miss stall signal.
23. A method according to claim 17 further comprising:
issuing instructions for the program application in-order.
24. A method according to claim 17 further comprising:
issuing instructions for the program application in-order; and
managing a machine state of the individual contexts separately and independently.
25. A method according to claim 17 further comprising:
loading data from a storage and storing data to a storage via a plurality of loadstore units that are individually allocated to individual threads in the multiple-thread pipeline.
26. A method according to claim 17 further comprising:
concurrently executing a plurality of execution threads in a plurality of multiple-thread pipelines so that the processor executes the one or more program applications with vertical threading and horizontal threading.
27. A processor comprising:
means for running a non-threaded program application;
means for executing the non-threaded program in a multiple-thread pipeline including a plurality of multiple-bit flip-flops that are capable of holding a plurality of execution threads;
means for switching context in a fast context switching operation including:
means for executing a first context in a first thread pathway in the multiple-thread pipeline;
means for receiving an exception condition signal;
means response to receipt of the exception condition signal for stalling the first context immediately including:
immediately deactivating the first context and activating an exception handler context while the state of the contexts in the multiple-thread pipeline remains the same.
28. A processor comprising:
means for running one or more program applications concurrently;
means for executing a plurality of execution threads in a multiple-thread pipeline including a plurality of multiple-bit flip-flops that hold the plurality of execution threads, the execution threads for executing issued instructions for the program applications, the executing operation including:
means for holding a plurality of threads in the multiple-thread pipeline simultaneously including an active thread and one or more inactive threads;
means for receiving notification of a stall condition;
means responsive to receipt of the stall condition for stalling the active thread immediately including:
immediately deactivating a currently active thread and activating a currently inactive thread while the state of the threads in the multiple-thread pipeline remains the same.
29. A processor comprising:
means for running one or more program applications concurrently;
means for executing a plurality of execution threads in a multiple-thread pipeline including a plurality of multiple-bit flip-flops that hold the plurality of execution threads, the execution threads for executing issued instructions for the program applications;
means for switching the execution threads in the multiple-thread pipeline including:
means for freezing an active state in the pipeline;
means for activating a previously idle thread in the pipeline while holding the state of the newly frozen thread in the pipeline; and
means for subsequently resuming execution of the frozen thread at the precise state of the frozen thread immediately prior to the thread switch.
30. A method of operating a processor comprising:
selecting a thread from among a plurality of execution threads, other threads being nonselected threads;
activating a machine state for the selected execution thread;
executing the selected execution thread in a shared pipeline; and freezing nonselected threads in the shared pipeline without executing.
31. A method according to claim 30 further comprising:
allocating a loadstore unit to individual threads of the plurality of execution threads; and
accessing the allocated loadstore units according to the executing thread.
32. A method according to claim 30 further comprising:
sharing a data storage unit among the plurality of execution threads.
33. A method according to claim 30 further comprising:
sharing an instruction control logic among the plurality of execution threads.
34. A method according to claim 30 further comprising:
sharing an external cache control unit among the plurality of execution threads.

1. A phototransistor having a substrate and a layer formed on the substrate containing laterally spaced emitter and collector regions of a first conductivity type and a base region of a second opposite conductivity type located between the emitter and collector regions, a depletion region being formed between the base region and the emitter region and including the whole of the base region.
2. A phototransistor according to claim 1 in which said depletion region includes the whole of the base region only upon a bias voltage being applied between the base and emitter regions.
3. A phototransistor having a substrate and a layer formed on the substrate containing laterally spaced emitter and collector regions of a first conductivity type and a base region of a second opposite conductivity type located between the emitter and collector regions, the base region having a width no more than about 4 m and having a charge carrier concentration of no more than about 1016 cm3.
4. A phototransistor according to claim 1, claim 2 or claim 3 in which the emitter, collector and base regions are doped regions of an element semiconductor.
5. A phototransistor according to claim 3 in which the element semiconductor is silicon.
6. A phototransistor according to any preceding claim having an insulating layer between the substrate and the emitter, collector and base regions.
7. A phototransistor according to any preceding claim in which an oxide layer is formed covering at least part of the base region.
8. A phototransistor according to any preceding claim in which the first conductivity type is n-type and the second conductivity type is p-type.
9. A phototransistor according to any preceding claim in combination with circuitry arranged to generate a bias voltage between the base and emitter regions adequate to generate a depletion region which includes the whole of the base region.
10. A method of operating a phototransistor according to any preceding claim, the method comprising using applying a bias voltage between the emitter and collector regions to generate the depletion region including the whole of the base region, exposing the phototransistor to illumination, and measuring the current conducted from the emitter region to the collector region.
11. A method according to claim 10 in which the bias voltage is in the range 2 to 6 volts.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A three-dimensional microstructure formed by a sequential build process, comprising:
a first microstructural element formed of a first material;
a second microstructural element formed of a second material;
a substrate over which the first microstructural element and the second microstructural element are disposed; and
a non-solid volume to which the first microstructural element andor the second microstructural element are exposed,
wherein, the first microstructural element comprises a patterned locking portion disposed at least partially through the second microstructural element to mechanically lock the first microstructural element and the second microstructural element.
2. The three-dimensional microstructure of claim 1, wherein the patterned locking portion is rounded.
3. The three-dimensional microstructure of claim 1, wherein the microstructure comprises a coaxial transmission line comprising a center conductor, an outer conductor and a dielectric support member for supporting the center conductor, wherein the dielectric support member is the first microstructural element, and the inner conductor andor the outer conductor is the second microstructural element.
4. The three-dimensional microstructure of claim 3, wherein the non-solid volume is under vacuum or in a gas state, and is disposed between the center conductor and the outer conductor.
5. The three-dimensional microstructure of claim 3, wherein the coaxial transmission line has a generally rectangular coaxial geometry.
6. The three-dimensional microstructure of claim 3, wherein the dielectric support member comprises at least one patterned locking portion at opposing ends of the dielectric support member in mechanically locking engagement with opposing surfaces of the outer conductor.
7. The three-dimensional microstructure of claim 1, wherein the patterned locking portion comprises an aperture extending at least partially through the first microstructural element.
8. The three-dimensional microstructure of claim 7, wherein metal material is disposed in the aperture affixing the first microstructural element to the second microstructural element.
9. The three-dimensional microstructure of claim 8, wherein the second microstructural element comprises metal material and the metal material in the aperture is of the same metal material as the metal material of the second microstructural element.
10. The three-dimensional microstructure of claim 7, wherein the aperture has a reentrant shape.
11. The three-dimensional microstructure of claim 7, wherein the aperture extends completely through the first microstructural element from a first surface to a second surface thereof.
12. The three-dimensional microstructure of claim 1, wherein the patterned locking portion comprises a reentrant profile.
13. A method of forming a three-dimensional microstructure by a sequential build process, comprising:
forming a plurality of layers over a substrate, wherein the layers comprise at least one of a first material, a second material and a sacrificial material;
forming a first microstructural element comprising the first material and including a patterned locking portion;
forming a second microstructural element comprising the second material; and
removing the sacrificial material to form a non-solid volume to which the first microstructural element andor the second microstructural element are exposed,
wherein, the patterned locking portion is disposed at least partially through the second microstructural element to mechanically lock the first microstructural element and the second microstructural element.
14. The method of claim 13, wherein the patterned locking portion comprises a reentrant profile.
15. The method of claim 13, wherein the patterned locking portion comprises an aperture extending at least partially therethrough.
16. The method of claim 15, comprising depositing a metal material in the aperture, affixing the first microstructural element to the second microstructural element.
17. The method of claim 13, wherein the first material is a dielectric material and the second material is a metal material.
18. The method of claim 13, wherein the microstructure comprises a coaxial transmission line comprising a center conductor, an outer conductor and a dielectric support member for supporting the center conductor, wherein the dielectric support member is the first microstructural element, and the inner conductor andor the outer conductor is the second microstructural element.
19. A three-dimensional microstructure formed by a sequential build process, comprising:
a first microstructural element formed of a first material;
a second microstructural element formed of a second material; and
a non-solid volume to which the first microstructural element andor the second microstructural element are exposed,
the first microstructural element comprising a patterned locking portion including a reentrant profile and disposed at least partially through the second microstructural element to mechanically lock the first microstructural element and the second microstructural element.
20. A three-dimensional microstructure formed by a sequential build process, comprising:
a first microstructural element formed of a first material;
a second microstructural element formed of a second material; and
a non-solid volume to which the first microstructural element andor the second microstructural element are exposed,
the first microstructural element comprising a patterned locking portion disposed at least partially through the second microstructural element to mechanically lock the first microstructural element and the second microstructural element,
the microstructure including a coaxial transmission line comprising a center conductor, an outer conductor and a dielectric support member for supporting the center conductor, the dielectric support member being the first microstructural element, and the inner conductor andor the outer conductor being the second microstructural element,
the dielectric support member comprising a patterned locking portion at opposing ends of the dielectric support member in mechanically locking engagement with opposing surfaces of the outer conductor.
21. A three-dimensional microstructure formed by a sequential build process, comprising:
a first microstructural element formed of a first material;
a second microstructural element formed of a second material; and
a non-solid volume to which the first microstructural element andor the second microstructural element are exposed,
the first microstructural element comprising a patterned locking portion disposed at least partially through the second microstructural element to mechanically lock the first microstructural element and the second microstructural element,
the patterned locking portion comprising an aperture extending at least partially through the first microstructural element and including a reentrant shape.
22. A three-dimensional microstructure formed by a sequential build process, comprising:
a first microstructural element formed of a first material;
a second microstructural element formed of a second material; and
a non-solid volume to which the first microstructural element andor the second microstructural element are exposed,
the first microstructural element comprising a patterned locking portion disposed at least partially through the second microstructural element to mechanically lock the first microstructural element and the second microstructural element,
the patterned locking portion comprising an aperture extending at least partially through the first microstructural element,
wherein metal material is disposed in the aperture affixing the first microstructural element to the second microstructural element.
23. A three-dimensional microstructure formed by a sequential build process, comprising:
a first microstructural element formed of a first material;
a second microstructural element formed of a second material; and
a non-solid volume to which the first microstructural element andor the second microstructural element are exposed,
the first microstructural element comprising a patterned locking portion disposed at least partially through the second microstructural element to mechanically lock the first microstructural element and the second microstructural element,
the patterned locking portion comprising an aperture extending completely through the first microstructural element from a first surface to a second surface thereof.