Author: claimsbot

What is claimed is:

1. A liquid crystal display device comprising opposing upper and lower substrates, liquid crystal sandwiched between the upper and lower substrates, and an upper polarization layer and a lower reflective polarization layer disposed above and below the liquid crystal, respectively, wherein the lower reflective polarization layer is formed by stacking prism-shaped dielectric interference films having two types of wedge-shaped cross section inclined surfaces formed continuously at regular intervals, and wherein angles formed between each of the two types of inclined surfaces and the lower substrate are different.
2. A liquid crystal display device according to claim 1, wherein the lower reflective polarization layer is a transflective polarization layer which has a polarization axis and a reflection axis orthogonal to the polarization axis and which reflects a portion of a component of incident light parallel to the reflection axis and passes a portion of the component of the incident light parallel to the reflection axis therethrough, and wherein the liquid crystal display device further comprises a lower polarization layer provided below the lower reflective polarization layer.
3. A liquid crystal display device according to claim 1, wherein the lower reflective polarization layer is partly provided at an inside surface side of the lower substrate, and wherein the liquid crystal display device further comprises a lower polarization layer provided below the lower reflective polarization layer.
4. A liquid crystal display device according to any one of claims 1 to 3, wherein an angle between one of the two types of inclined surfaces and the lower substrate is from 20 degrees to 50 degrees inclusive, and wherein an angle between the other of the two types of inclined surfaces and the lower substrate is from 50 degrees to 80 degrees inclusive.
5. A liquid crystal display device according to any one of claims 2 to 4, wherein athe polarization axis of the lower reflective polarization layer and a polarization axis of the lower polarization layer are disposed substantially orthogonal to each other.
6. A liquid crystal display device according to claim 5, wherein an angle between the polarization axis of the lower reflective polarization layer and the polarization axis of the lower polarization layer is from 60 degrees to 120 degrees inclusive.
7. A liquid crystal display device according to any one of claims 1 to 6, further comprising a scattering layer, disposed above the lower reflective polarization layer, for scattering light reflected by the lower reflective polarization layer.
8. A liquid crystal display device according to any one of claims 1 to 7, further comprising a color filter provided at either an inside surface side of the upper substrate or athe inside surface side of the lower substrate.
9. An electronic device comprising the liquid crystal display device of any one of claims 1 to 8.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for adjusting a frequency working between a north bridge chip and a random access memory of a computer system, comprising steps of:
monitoring a frequency change of the CPU of the computer system after the computer system enters an operating system; and
automatically adjusting the frequency working between the north bridge chip and the random access memory when the frequency change of the CPU exceeds threshold.
2. The method according to claim 1 further comprising steps of:
executing a POST procedure to detect and calibrate the frequency working between the north bridge chip and the random access memory and a phase difference of the frequency after the frequency adjustment;
modifying settings of BIOS with the calibration results; and
applying the adjusted frequency to the work between the north bridge chip and the random access memory.
3. The method according to claim 1 wherein the frequency working between the north bridge chip and the random access memory decreases with the decrease of the frequency of the CPU.
4. The method according to claim 3 wherein the frequency of the CPU is decreased for throttling when the computer system has been in an idle state for more than a preset period of time.
5. The method according to claim 4 wherein the frequency of the CPU is increased when the computer system restores from the idle state.
6. The method according to claim 5 wherein the frequency working between the north bridge chip and the random access memory increases with the increase of the frequency of the CPU.
7. A method for adjusting a frequency working between a north bridge chip and a random access memory of a computer system, comprising steps of:
monitoring a workload index of the north bridge chip after the computer system enters an operating system; and
automatically adjusting the frequency working between the north bridge chip and the random access memory when the workload index changes to a certain level.
8. The method according to claim 7 further comprising steps of:
executing a POST procedure to detect and calibrate the frequency working between the north bridge chip and the random access memory and a phase difference of the frequency after the frequency adjustment;
modifying settings of BIOS with the calibration results; and
applying the adjusted frequency to the work between the north bridge chip and random access memory.
9. The method according to claim 7 wherein said workload index is the temperature detected around the north bridge chip.
10. The method according to claim 9 wherein the frequency working between the north bridge chip and the random access memory is lowered when the temperature detected around the north bridge chip exceeds a threshold.
11. The method according to claim 10 wherein the frequency working between the north bridge chip and the random access memory restores when temperature detected around the north bridge chip restores to a normal level.
12. The method according to claim 7 wherein said workload index is the data flow processed by the north bridge chip.
13. The method according to claim 11 wherein the frequency working between the north bridge chip and the random access memory is lowered when the north bridge chip is in an idle state.
14. The method according to claim 12 wherein the frequency working between the north bridge chip and the random access memory restores when the north bridge chip restores from the idle state.
15. A method for adjusting a frequency working between a north bridge chip and a random access memory of a computer system, comprising steps of:
determining whether a setting of a software program executed by the computer system is changed after the computer system enters an operating system; and
dynamically adjusting the frequency working between the north bridge chip and the random access memory according to the setting when the setting is changed.
16. The method according to claim 15 further comprising steps of:
executing a POST procedure to detect and calibrate the frequency working between the north bridge chip and the random access memory and a phase difference of the frequency after the frequency adjustment;
modifying settings of BIOS with the calibration results; and
applying the adjusted frequency to the work between the north bridge chip and random access memory.
17. The method according to claim 15 wherein the setting of the software program is changeable by the user.
18. The method according to claim 15 wherein the software program is a power inspection software program.
19. The method according to claim 15 wherein the frequency working between the north bridge chip and the random access memory is dynamically adjusted by coordinating the north bridge chip and the random access memory.

What is claimed is:

1. A semiconductor sensor device comprising a plurality of sensor elements, a signal read circuit for reading levels of output signals from said sensor elements to output pixel data for said sensor elements, said signal read circuit having a bias circuit for supplying a bias signal to said output signals, a first comparator for comparing said pixel data against a specified threshold level to output result signals having 1 or 0, a counter for counting a number of said result signals for said pixel data, a second comparator for comparing sad number of said result signals against a specified number, and a bias controller for controlling said bias signal so that said number of said result signals becomes substantially equal to said specified number.
2. The semiconductor sensor device as defined in claim 1, wherein said bias controller determines bits of said bias signal from a most significant bit to a least significant bit.
3. The semiconductor sensor device as defined in claim 1, further comprising a fixed pattern noise (FPN) correction circuit for correcting said pixel data by using FPN correction data, wherein said controller calculates first and second desired values for said bias signal based on said number of said result signals having 1 and said number of said result signals having 0, respectively, and said FPN correction circuit determines said FPN correction data based on said first and second desired values.
4. The semiconductor sensor device as defined in claim 4, further comprising a fixed pattern noise (FPN) correction circuit for correcting said pixel data by using FPN correction data, wherein said second comparator compares said number of said result signals against a first specified number and a second specified number, and said controller calculates first and second desired values for said bias signal based on said first specified number and said second specified number, respectively, and said FPN correction circuit determines said FPN correction data based on said first and second desired values.
5. A semiconductor sensor device comprising a plurality of sensor elements, a signal read circuit for reading levels of output signals from said sensor elements to output pixel data for said sensor elements, said signal read circuit having a bias circuit for supplying a bias signal to said output signals, a fixed pattern noise (FPN) correction circuit for correcting said pixel data by using FPN correction data, a first comparator for comparing said pixel data against a specified threshold level to output result signals having 1 or 0, a counter for counting a number of said result signals for said pixel data, and a bias controller for determining said bias signal at a first value so that first said number of said results signals counted based on said first value becomes substantially equal to second said number of said result signals counted based on a second value which is obtained based on said first value and a full scale of said FPN correction data.
6. A method for controlling a semiconductor sensor device having a plurality of sensor elements, a signal read circuit for reading levels of output signals from said sensor elements to output pixel data for said sensor elements, said signal read circuit having a bias circuit for supplying a bias signal to said output signals, said method comprising the steps of:
comparing said pixel data against a specified threshold level to output result signals having 1 or 0;
counting a number of said result signals for said pixel data;
comparing said number of said result signals against a specified number; and
controlling said bias signal so that said number of said result signals becomes substantially equal to said specified number.
7. The method as defined in claim 6, wherein said controlling step includes determining bits of said bias signal from a most significant bit to a least significant bit.
8. The method as defined in claim 6, wherein said controlling steps includes calculating first and second desired values for said bias signal based on said number of said result signals having 1 and said number of said result signals having 0, respectively, and determining a FPN correction data based on said first and second desired values.
9. The method as defined in claim 6, wherein said number comparing step includes comparing said number of said result signals against a first specified number and a second specified number, calculating first and second desired values for said bias signal based on said first specified number and said second specified number, respectively, and determining, a FPN correction data based on said first and second desired values.
10. A method for controlling a semiconductor sensor device having a plurality of sensor elements, a signal read circuit for reading levels of output signals from said sensor elements to output pixel data for said sensor elements, said signal read circuit having a bias circuit for supplying a bias signal to said output signals, and a fixed pattern noise (FPN) correction circuit for correcting said pixel data by using FPN correction data, said method comprising the steps of:
comparing said pixel data against a specified threshold level to output result signals having 1 or 0;
counting a number of said result signals for said pixel data; and
determining said bias signal at a first value so that first said number of said results signals counted based on said first value becomes substantially equal to second said number of said result signals counted based on a second value which is obtained based on said first value and a full scale of said FPN correction data.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of assembling a modular floor tile, comprising:
providing a modular floor tile having a top surface layer and a plurality of rigid support members extending from the top surface layer;
providing at least one resilient support assembly comprising first and second resilient support portions;
mounting the first resilient support portion to the modular floor tile;
mounting the second resilient support portion to the modular floor tile.
2. The method of claim 1, wherein providing the at least one resilient support assembly includes forming the first and second resilient support portions as a single, unitary piece.
3. The method of claim 1, wherein providing the at least one resilient support assembly includes forming the first and second resilient support portions as separate pieces.
4. The method of claim 1, wherein mounting the first and second resilient support portions includes concurrently mounting the first and second resilient support portions to the modular floor tile.
5. The method of claim 1, wherein mounting the first resilient support portion includes creating an interference fit between the plurality of rigid support members and the first resilient support portion.
6. The method of claim 1, wherein mounting the second resilient support portion includes positioning at least one of the plurality of rigid support members between the first and second resilient support portions.