Author: claimsbot

1. A wafer boat for holding a plurality of semiconductor wafers in a spaced apart relationship during processing, comprising at least one support member defining a plurality of sets of at least two vertically spaced apart wafer holding provisions, each of which wafer holding provisions is configured to independently hold a wafer in a substantially horizontal orientation, and wherein said sets are arranged such that the wafer boat is configured to accommodate a plurality of juxtaposed stacks of substantially horizontally oriented, vertically spaced apart wafers.
2. The wafer boat according to claim 1, wherein said plurality of sets of wafer holding provisions includes at least three such sets, such that the wafer boat is configured to accommodate at least three juxtaposed stacks of wafers.
3. The wafer boat according to claim 1, further comprising a first end member at a lower extremity of the wafer boat and a second end member at an upper extremity of the wafer boat,
wherein said at least one support member includes a plurality of rod-shaped support members, each interconnecting said end members and defining a plurality of vertically spaced apart wafer engagement provisions,
wherein each set of wafer holding provisions is defined by a set of at least two rod-shaped support members, and wherein each individual holding provision of a certain set of wafer holding provisions is defined by at least two wafer engagement provisions defined by the rod-shaped support members defining the respective set of wafer holding provisions.
4. The wafer boat according to claim 3, wherein said wafer engagement provisions are formed by recesses in said rod-shaped support members.
5. The wafer boat according to claim 3, wherein the rod-shaped support members are substantially straight and extend in parallel between the end members, such that the wafer boat is configured to accommodate a plurality of straight, parallel stacks.
6. The wafer boat according to claim 3, wherein each set of wafer holding provisions is defined by a set of at least three rod-shaped support members.
7. The wafer boat according to claim 3, wherein at least two sets of rod-shaped support members have at least one rod-shaped support member in common.
8. The wafer boat according to claim 3, wherein at least two sets of rod-shaped support members have no rod-shaped support member in common.
9. The wafer boat according to claim 1, wherein each set of wafer holding provisions is associated with a wafer transfer direction along which wafers are insertable into and removable from the wafer holding provisions of the respective set, and
wherein said plurality of sets of wafer holding provisions includes at least two sets whose respective wafer transfer directions include an angle <90\xb0.
10. The wafer boat according to claim 9, wherein said plurality of sets of wafer holding provisions includes at least three sets of which any two respective wafer transfer directions include an angle <120\xb0.
11. The wafer boat according to claim 1, wherein each of said wafer holding provisions is configured to hold a semiconductor wafer having a characteristic main surface dimension d\u2266200 mm, and preferably d\u2266150 mm.
12. A semiconductor processing apparatus, in particular a vertical furnace, comprising a wafer boat according to claim 1.
13. The semiconductor processing apparatus according to claim 12, comprising:
a reactor tube;
a pedestal, supporting the wafer boat, and configured to be at least partly insertable into the reactor tube; and
a wafer handling robot, including a multi-link articulated arm, configured to load and unload wafers into and from the wafer holding provisions of each of the sets of wafer holding provisions of the wafer boat.
14. The semiconductor processing apparatus according to claim 13, wherein the articulated arm of wafer handling robot includes at least three links.
15. The semiconductor processing apparatus according to claim 13, wherein the wafer boat is rotatably arranged around its central axis.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of making a gate-edge diode in a diode region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising:
forming a first dielectric layer on the substrate in the diode region and the NVM region;
forming a first conductive layer on the first dielectric layer;
forming a second dielectric layer on the first conductive layer;
forming a second conductive layer over the second dielectric layer;
forming a first mask over the diode region having a first pattern, wherein the first pattern is of a plurality of fingers and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the non-volatile memory cell;
performing an etch through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region; and
performing an implant using the gate stack and the plurality of fingers as a mask to provide sourcedrain regions adjacent to the gate stack in the NVM region and diode terminals between the fingers in the diode region to form the gate-edge diode with the diode terminals and the substrate.
2. The method of claim 1, wherein the step of forming the first mask is further characterized by the first pattern being further of a connecting bar connecting the plurality of fingers and the step of performing the etch leaves the connecting bar.
3. The method of claim 2, further comprising removing the second conductive layer from the connecting bar and leave connecting bar as a portion of the first conductive layer.
4. The method of claim 1, wherein the gate stack comprises a control gate as a portion of the second conductive layer and a floating gate as a portion of the first conductive layer.
5. The method of claim 1, further comprising forming sidewall spacers adjacent to the plurality of fingers and the gate stack.
6. The method of claim 5, wherein the step of performing the implant is further characterized by the sidewalls spacers acting as a mask.
7. The method of claim 1, further comprising removing the first dielectric layer between the fingers and adjacent to the gate stack after the step of performing the implant.
8. The method of claim 1, further comprising forming a contact to the first conductive layer.
9. The method of claim 1, further comprising forming an interlayer dielectric over the gate stack and the plurality of fingers.
10. The method of claim 9, further comprising forming contacts through the interlayer dielectric to the diode terminals.
11. A method of making a gate-edge diode in a diode region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising:
forming a first dielectric layer on the substrate in the diode region and the NVM region;
forming a first conductive layer on the first dielectric layer;
forming a second dielectric layer on the first conductive layer;
forming a second conductive layer over the second dielectric layer;
forming a first mask over the diode region having a first pattern, wherein the first pattern is of a plurality of fingers and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of non-volatile memory cell;
performing an etch through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region;
forming sidewall spacers adjacent to the plurality of fingers and the gate stack; and
performing an implant using the gate stack, the plurality of fingers, and the sidewall spacers as a mask to provide sourcedrain regions adjacent to the gate stack in the NVM region and diode terminals between the fingers in the diode region to form the gate-edge diode with the diode terminals and the substrate.
12. The method of claim 11, wherein the step of forming the first mask is further characterized by the first pattern being further of a connecting bar connecting the plurality of fingers and the step of performing the etch leaves the connecting bar.
13. The method of claim 12, further comprising removing the second conductive layer from the connecting bar and leave connecting bar as a portion of the first conductive layer.
14. The method of claim 13, wherein the gate stack comprises a control gate as a portion of the second conductive layer and a floating gate as a portion of the first conductive layer.
15. The method of claim 14, further comprising removing the first dielectric layer between the fingers and adjacent to the gate stack after the step of performing the implant.
16. A method of making a gate-edge diode in a diode region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising:
forming a first dielectric layer on the substrate in the diode region and the NVM region;
forming a polysilicon layer on the first dielectric layer;
forming a second dielectric layer on the polysilicon layer;
forming a conductive layer over the second dielectric layer;
forming a first mask over the diode region having a first pattern, wherein the first pattern is of a plurality of fingers and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the non-volatile memory cell;
performing an etch through the conductive layer, the second dielectric layer, and the polysilicon layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region; and
performing an implant using the gate stack and the plurality of fingers as a mask to provide sourcedrain regions adjacent to the gate stack in the NVM region and diode terminals between the fingers in the diode region to form the gate-edge diode with the diode terminals and the substrate.
17. The method of claim 16, further comprising forming sidewall spacers adjacent to the plurality of fingers and the gate stack, wherein the step of performing the implant is further characterized by the sidewalls spacers acting as a mask.
18. The method of claim 17, further comprising removing the first dielectric layer between the fingers and adjacent to the gate stack after the step of performing the implant.
19. The method of claim 18, further comprising performing a patterned etch of the polysilicon layer prior to the step of forming the conductive layer.
20. The method of claim 19, further comprising:
forming an interlayer dielectric over the gate stack and the plurality of fingers; and
forming contacts through the interlayer dielectric to the diode terminals.

1. A power regulator circuit comprising:
first and second power regulators respectively configured and arranged to provide regulated power at main and standby power levels, the standby power level being less than half of the main power level; and
a controller configured and arranged to
in a standby mode, output a standby signal to operate the second power regulator for supplying power to an integrated circuit at the standby power level,
in a startup mode, output a startup signal to turn the first power regulator on while continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period, and output a start signal for operating a processor in the integrated circuit in a low-frequency mode via the second power regulator, and
after the start-up period, operating the first power regulator for supplying power at the main power level for operating the processor in a high-frequency mode.
2. The circuit of claim 1, wherein, in the startup mode,
the controller is configured to output a signal for operating an oscillator to power the processor in the low-frequency mode, and
the second power regulator is configured to provide regulated power to the oscillator at a startup power level.
3. The circuit of claim 1, wherein, in the startup mode,
the controller is configured to output a signal for operating an oscillator to power the processor in the low-frequency mode,
the second power regulator is configured to provide the regulated power to the oscillator for operating the oscillator at low frequency to power the processor in the low-frequency mode, and
the controller is configured to, in response to the first power regulator providing a threshold power level, control the first power regulator to provide the regulated power to the oscillator for operating the oscillator at a high frequency to power the processor in a high-frequency mode.
4. The circuit of claim 1, wherein the controller is configured and arranged to monitor the power level of the first power regulator and, in response to the first power regulator providing power at a power threshold, terminate the startup mode by turning the second power regulator off and controlling the first power regulator for supplying the power for operating the processor in the high-frequency mode.
5. The circuit of claim 1, wherein the controller is configured and arranged to output the startup signal to control the first power regulator for entering the startup mode from the standby mode in response to receiving a request for accessing the integrated circuit.
6. The circuit of claim 1, wherein the controller is configured and arranged to, in response to receiving a request for accessing the integrated circuit,
output a control signal to control the second power regulator for supplying power to the integrated circuit, and output the start signal for operating the processor in the low-frequency mode to serve the request, and
after the request has been served, output the standby signal to operate the second power regulator for supplying power to the integrated circuit at the standby power level, and outputting a control signal for turning the processor off.
7. The circuit of claim 1, wherein the controller is configured and arranged to, in the startup mode, operate the second power regulator for supplying power to the integrated circuit at a startup power level that is higher than the standby power level.
8. The circuit of claim 1, wherein the second power regulator is configured and arranged for supplying power to the integrated circuit in the startup mode at a power level that is higher than the standby power level, to operate the processor in the low-frequency mode.
9. The circuit of claim 1, wherein the controller is configured to output a control signal to power off a plurality of circuits in the integrated circuit for entering the standby mode, and to control at least one circuit in the integrated circuit to operate at the standby power level.
10. The circuit of claim 1, wherein the controller is configured to output the standby and startup signals by outputting a status signal indicative of the respective standby and startup modes.
11. The circuit of claim 1, wherein the controller is configured to output the start signal for operating a processor in the integrated circuit in a low-frequency mode by outputting a signal to operate a clock generation circuit to oscillate at low frequency for operating the processor.
12. A method for powering an integrated circuit having first and second power regulators respectively configured and arranged to provide regulated power at main and standby power levels, the standby power level being less than half of the main power level, the method comprising:
in a standby mode, outputting a standby signal to operate the second power regulator for supplying power to an integrated circuit at the standby power level,
in a startup mode, outputting a startup signal to turn the first power regulator on while continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period, and outputting a start signal for operating a processor in the integrated circuit in a low-frequency mode via the second power regulator, and
after the start-up period, operating the first power regulator for supplying power for operating the processor in a high-frequency mode.
13. The method of claim 12, wherein outputting a start signal for operating a processor in the integrated circuit in a low-frequency mode includes outputting a start signal for operating an oscillator to power the processor in the low-frequency mode.
14. The method of claim 12, wherein
outputting a start signal for operating a processor in the integrated circuit in a low-frequency mode includes outputting a signal for operating an oscillator to power the processor in the low-frequency mode,
continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period includes operating the second power regulator to provide the regulated power to the oscillator for operating the oscillator at low frequency to power the processor in the low-frequency mode, and
operating the first power regulator for supplying power for operating the processor in a high-frequency mode includes outputting, in response to the first power regulator providing a threshold power level, a control signal to control the first power regulator to provide the regulated power to the oscillator for operating the oscillator at a high frequency to power the processor in a high-frequency mode.
15. The method of claim 12, further including
in the startup mode, monitoring the power level of the first power regulator, and
outputting a control signal to turn the second power regulator off in response to the monitored power level of the first power regulator reaching a power threshold.
16. The method of claim 12, further including,
in response to receiving a request for accessing the integrated circuit, outputting the standby signal to control the second power regulator for supplying power to the integrated circuit, and outputting the start signal for operating the processor in the low-frequency mode to serve the request, and
after the request has been served, outputting the standby signal to operate the second power regulator for supplying power to the integrated circuit at the standby power level, and outputting a signal for turning the processor off.
17. The method of claim 12 wherein, in the startup mode, continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period includes operating the processor at a startup power level that is higher than the standby power level.
18. The method of claim 12, wherein outputting a start signal for operating a processor in the integrated circuit in a low-frequency mode via the second power regulator includes outputting a signal to operate a clock generation circuit to oscillate at low frequency for operating the processor.
19. The method of claim 12, wherein outputting a startup signal to turn the first power regulator on while continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period, and outputting a start signal for operating a processor in the integrated circuit include outputting the signals and operating the second power regulator in response to receiving a request for accessing the integrated circuit.
20. An integrated circuit chip comprising:
a plurality of functional circuit blocks;
a clock generation circuit configured to generate a clock signal;
a microprocessor circuit coupled to receive the clock signal and configured to operate at a frequency based upon the received clock signal;
first and second power regulators respectively configured and arranged to provide regulated power at main and standby power levels, the standby power level being less than half of the main power level; and
a power control circuit configured and arranged to
enter a standby mode in which the integrated circuit chip is not serving requests, by outputting a standby signal to operate the second power regulator for supplying power to the circuit at the standby power level,
in response to a request for accessing the integrated circuit chip, enter a startup mode by outputting a startup signal to turn the first power regulator on while continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period, and outputting a start signal for operating the microprocessor circuit in a low-frequency mode via the second power regulator, and
in response to the first power regulator reaching a full power level, enter a main operation mode by operating the first power regulator for supplying power at the main power level for operating the microprocessor in a high-frequency mode.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An electronic apparatus comprising:
a first display device comprising a first housing and a first display screen which is held in the first housing;
a second display device comprising a second housing and a second display screen which is held in the second housing, the second display screen comprising a sensor which generates a sensor output signal depending on an input on the second display screen;
a connecting mechanism configured to connect the first and second housings together and be able to adjust an opening angle of the first housing and the second housing;
a display processing section configured to display a first display image on the first display screen and a first interface image on the second display screen;
a determining section configured to determine an instruction to the first interface image on the basis of the sensor output signal; and
a control section configured to control the display processing section in response to the instruction to display a second display image in place of the first display image on the first display screen and display a second interface image in place of the first interface image on the second display screen,
wherein the connecting mechanism sets the opening angle of the first housing and the second housing so that the first and second display screens can be viewed from one side of the electronic apparatus, and the second display screen is switched between display of the second interface image on the first interface image and non-display of the second interface image on the first interface image, the display of the second interface image on the first interface image being displayed on top of the first interface image as a translucent or opaque image.
2. The electronic apparatus according to claim 1, wherein the connecting mechanism sets the opening angle of the first housing and the second housing so that the first and second display screens can be viewed from opposite sides of the electronic apparatus, and the first and second display screens display the second display image and the second interface image corresponding to substantially the same image or the second display image and second interface image which are in a mirrored relationship.
3. The electronic apparatus according to claim 1, wherein the first display device further comprises a light source incorporated into the first housing to illuminate the first display screen, and the first housing comprises a structure configured to guide illumination light from the light source to the second display device as backlight illumination or a front-light illumination.
4. The electronic apparatus according to claim 1, wherein the first and second display screens forms one flexible and bendable display unit.
5. An electronic apparatus comprising:
a first display device comprising a first housing and a first display screen which is held in the first housing;
a second display device comprising a second housing and a second display screen which is held in the second housing, the second display screen comprising a sensor which generates a sensor output signal depending on an input on the second display screen;
a connecting mechanism configured to connect the first and second housings together and be able to adjust an opening angle of the first housing and the second housing;
a display processing section configured to display a first display image on the first display screen and a first interface image on the second display screen;
a determining section configured to determine an instruction to the first interface image on the basis of the sensor output signal; and
a control section configured to control the display processing section in response to the instruction to display a second display image in place of the first display image on the first display screen and display a second interface image in place of the first interface image on the second display screen,
wherein the first display device further comprises a light source incorporated into the first housing to illuminate the first display screen, and the first housing comprises a structure configured to guide illumination light from the light source to the second display device as backlight illumination or a front-light illumination.