Author: claimsbot

What is claimed is:

1. A liquid crystal display element comprising:
a pair of bases of which one base is a transparent base transmitting light;
liquid crystals having negative dielectric anisotropy sealed between the pair of bases; and
an inorganic alignment layer formed on each surface of the pair of bases facing toward the liquid crystals, the alignment layer orientating a pre-tilt angle of the liquid crystals toward an angle of 3 to 10 degrees.
2. A method of forming an alignment layer of a liquid crystal display element comprising:
a pair of bases of which one base is a transparent base transmitting light;
liquid crystals having negative dielectric anisotropy sealed between the pair of bases; and
an inorganic alignment layer formed on each surface of the pair of bases facing toward the liquid crystals, the alignment layer orientating a pre-tilt angle of the liquid crystals toward an angle of 3 to 10 degrees,
the method is further characterized in that
each of the pair of bases is displaced in a filming apparatus such that vapor stream of a material for the inorganic alignment layer displaced in the filming apparatus enters into each of the pair of bases at an angle of 40 to 60 degrees with respect to each normal line of the pair of bases,
a gas pressure of either oxygen gas or inert gas introduced into the filming apparatus is controlled so as to conduct the pre-tilt angle to be an angle of 3 to 10 degrees, and that the inorganic alignment layer is formed by being evaporated on each surface of the pair of bases.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A solid-state image pickup device comprising:
an optical structure that forms a subject image;
a solid-state image pickup element that converts, into an electrical signal, a subject image formed by the optical structure;
a holding section, holding the optical structure therein, which contains the solid-state image pickup element; and
a cushioning member, disposed between the optical structure and the holding section so as to avoid an optical path of the optical structure, which absorbs an impact of contact between the optical structure and the holding section,
the cushioning member being made of nonmetallic material.
2. The solid-state image pickup device as set forth in claim 1, wherein that surface of the cushioning member which makes contact with the optical structure is coated with a fluorocarbon resin.
3. The solid-state image pickup device as set forth in claim 2, wherein the cushioning member has a first grooved portion formed by removing a part of that surface of the cushioning member which makes contact with the optical structure.
4. The solid-state image pickup device as set forth in claim 2, wherein the cushioning member is coated with grease.
5. The solid-state image pickup device as set forth in claim 4, wherein:
the cushioning member has a plurality of holes formed on a side surface thereof; and
the holes have the grease injected thereinto.
6. The solid-state image pickup device as set forth in claim 4, wherein:
the cushioning member has a second grooved portion formed in a side surface thereof by removing a peripheral part of the side surface; and
the second grooved portion has the grease injected thereinto.
7. The solid-state image pickup device as set forth in claim 4, wherein:
that cross-section of the cushioning member which is parallel to the surface of contact with the optical structure becomes smaller with longer distance from the optical structure; and
the cushioning member has a side surface coated with the grease.
8. The solid-state image pickup device as set forth in claim 4, wherein:
the cushioning member has a plurality of grooves so formed on a back surface thereof as to extend from an edge portion of the back surface to a center of the back surface; and
the grooves have the grease injected thereinto.
9. The solid-state image pickup device as set forth in claim 4, wherein:
the cushioning member has a third grooved portion formed in a back surface thereof by removing a part of that surface of the cushioning member which makes contact with the holding section; and
the third grooved portion has the grease injected thereinto.
10. The solid-state image pickup device as set forth in claim 4, wherein the solid-state image pickup device has at least one of an automatic focus function, a zoom function, and a macro function.
11. An electronic apparatus including a solid-state image pickup device, the solid-state image pickup device comprising:
an optical structure that forms a subject image;
a solid-state image pickup element that converts, into an electrical signal, a subject image formed by the optical structure;
a holding section, holding the optical structure therein, which contains the solid-state image pickup element; and
a cushioning member, disposed between the optical structure and the holding section so as to avoid an optical path of the optical structure, which absorbs an impact of contact between the optical structure and the holding section,
the cushioning member being made of nonmetallic material.

1. A manual method to transform an infant diaper to enhance the transport thereof comprising the steps of:
A. purchasing a commercially available non-factory vacuumed packaged readily foldable rectangular shaped diaper in the flat of a size not in excess of eleven inches in width nor in excess of thirteen inches in length and of bulky water-absorbent cloth construction material located in a medial area thereof;
B. transforming said diaper preparatory to effectuate an enhanced condition contributing to portability thereof by;
(1) manually folding said length upon itself and said width upon itself into approximately a ten inch width and seven inch length rectangular configurated size;
(2) manually subsequently folding said aforesaid folded length in width again upon itself into approximately a five inch width and seven inch length rectangular configurated size; and
(3) manually third subsequently folding said aforesaid folded in length upon itself diaper into approximately a five inch width and four inch length rectangular configurated size;

C. manually inserting said transformed diaper into a package of flexible plastic construction material;
D. withdrawing by vacuum means the air content of said package contributing to a size reduction in a rectangular shape of approximately three inches by three inches;
E. heat sealing peripheral overlapping edges of said package;
F. transporting said diaper to a site of use;
G. opening at least one sealed together cooperating edges;
H. removing said three inches by three inches shape; and
I. unfolding said removed three inches by three inches shape into said purchased commercially available eleven inches by thirteen inches size;
whereby the diaper is used at said site of use unencumbered by bulk and size handling of the diaper during the transport thereto.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A high-density NAND (HiNAND) circuit with multi-level BL-hierarchical architecture for lowering disturbance, power-consumption, and latency in Program, Program-Verify, Erase-Verify, and Read operations, the HiNAND circuit comprising:
a matrix of NAND memory cells divided to J Groups in column-direction having N global bit lines (GBLs), each Group being divided to L Segments in the column-direction, each Segment being further divided to K Blocks in the column-direction, each Block comprising N Strings in the column-direction or M Pages in row-direction, each String comprising M NAND memory cells connected in series sandwiched by a first String-select transistor and a second String-select transistor, each NAND memory cell in a Page being associated with a word line (WL), J, L, K, M, and N being integer numbers, wherein J is at least equal to or greater than 8;
a BL-hierarchical structure comprising N metal3 lines corresponding to N metal2 lines and further to N metal1 lines all being parallel to each other along the column-direction, each metal3 line being used as one the N GBLs across all J Groups of NAND memory cells, each metal2 line being used as one of N sub-BL lines (SBLs) associated with each column of NAND memory cells across all L Segments in each Group, each metal1 line being used as one of N sub-sub-BL lines (BBLs) across all K Blocks in each Segment;
a plurality of metal0 lines laid out along the row-direction, the plurality of metal0 lines including at least one common source line connected respectively via the first String-select transistor to each of the N Strings of NAND memory cells in one or more Blocks of one or more Segments of each Group, a first powerVss line for all J Groups, a second powerVss line for all L Segments in a Group, and a third powerVss line for all K Blocks in a pair of Segments in one Group;
N first GBL-select transistors commonly controlled by a first gate signal to respectively couple the N GBLs with the first powerVss line;
N second GBL-select transistors commonly controlled by a second gate signal to respectively couple the N GBLs with the corresponding N SBLs;
N first SBL-select transistors commonly controlled by a third gate signal to respectively couple the N SBLs with the second powerVss line;
N second SBL-select transistors commonly controlled by a fourth gate signal to respectively couple the N SBLs with the corresponding N BBLs;
N BBL-select transistors commonly controlled by a fifth gate signal to respectively couple the N BBLs with the third powerVss line; and
a Page Buffer circuit respectively coupled to the N GBLs and configured to store and supply multiple logic page data in the form of sequential pipe-line;
wherein the BL-hierarchical structure in accordance with a preferred set of bias voltage conditions associated with at least the first gate signal, the second gate signal, the third gate signal, the fourth gate signal, and the fifth gate signal is configured to allow temporary storages of program voltage and program-inhibit voltage in the multiple BBLs in one or more Segments of one or more Groups for performing multiple-WL and All-BL Program, Program-Verify, and Read operations simultaneously with less power, latency, and disturbance.
2. The HiNAND circuit of claim 1 wherein the BL-hierarchical structure comprises three levels including a first level for the N metal3 lines, a second level for the N metal2 lines laid out one level below the first level, and a third level for the N metal1 lines laid out one level below the second level.
3. The HiNAND circuit of claim 1 wherein each of the N metal3 lines comprises a first parasitic capacitor associated with one GBL with a full length across all J Groups, each of the N metal2 lines comprises a second parasitic capacitor associated with one SBL with a first length across all L Segments in one Group, each of the N metal1 lines comprises a third parasitic capacitor associated with one BBL with a second length across all K Blocks in one Segment, wherein the first length is about 1J of the full length and the second length is about 1L of the first length, correspondingly, the second parasitic capacitor having a capacitance about 1J of that of the first parasitic capacitor and the third parasitic capacitor having a capacitance about 1L of that of the second parasitic capacitor and about 1(J\xd7L) of that of the first parasitic capacitor, assuming same unit for all capacitors.
4. The HiNAND circuit of claim 3 wherein each of the first, second, and third parasitic capacitor is controlled at least by the N second GBL-select transistors and the N second SBL-select transistors to be isolated from each other to allow temporary charge storage in multiple local BBLs metal1 lines and SBLs metal2 lines in one or more Segments of one or more Groups representing sequentially loaded data from the Page Buffer circuit.
5. The HiNAND circuit of claim 3 wherein the first parasitic capacitor is configured to couple with the second parasitic capacitor and the third parasitic capacitor to share smaller amount of charges independently charged from the second powerVss line and the third powerVss line for reducing power consumption and latency during precharge for Program, Program-Verify, and Read operations.
6. The HiNAND circuit of claim 1 wherein the first powerVss line is configured to discharge each of the N GBLs through all J Groups to Vss=0V by setting the first gate signal to Vdd=1.8V, the second powerVss line is configured to discharge each of the N SBLs in a currently selected Group to Vss by setting the third gate signal to Vdd, the third powerVss line is configured to discharge each of the N BBLs in a selected Segment of the currently selected Group to Vss by setting the fifth gate signal to Vdd.
7. The HiNAND circuit of claim 6 wherein the third powerVss line is configured to pre-charge each of the N BBLs in any selected Block in one or more selected Segments of one or more selected Groups to a MV voltage up to 7V while setting the fifth gate signal up to 10V, setting the corresponding common source line to Vdd, setting a gate signal of the second String-select transistor up to 10V to allow the MV voltage to pass and setting a gate signal of the first String-select transistor to 0V to prevent leakage out of the selected Block, the N BBLs being isolated from both the corresponding N SBLs and N GBLs at 0V by setting the second gate signal, the third gate signal, and the fourth gate signal to 0V, for All-BL Program operation.
8. The HiNAND circuit of claim 6 wherein the second powerVss line is configured to couple with a precharge voltage ranging from Vdd up to 7V for charging the N SBLs and corresponding N BBLs in one selected Segment of one or more selected Groups by setting the corresponding third gate signal up to 10V, setting the corresponding second gate signal to 0V, setting the corresponding fourth gate signal up to 10V, and setting the corresponding fifth gate signal to 0V, for All-BL Read, Erase-Verify, and Program-Verify operations.
9. The HiNAND circuit of claim 7 wherein each String of M NAND memory cells associated with the corresponding one of pre-charged N BBLs in the selected Block is latched to the MV-7V by setting the first String-select transistor and the second String-select transistor to turn off charge leakage paths, followed by turning off the third powerVss line to 0V while setting the fifth gate signal to 0V.
10. The HiNAND circuit of claim 9 wherein the Page Buffer circuit is configured to supply a N-bit logic page data with Vdd or 0V levels across the N GBLs, the N-bit logic page data being converted to a data pattern with MV or 0V levels respectively at the N BBLs in the selected Block by first setting the second gate signal greater than Vdd with margin to share charges of the Vdd or 0V levels at the N GBLs with the corresponding N SBLs, followed by setting the fourth gate signal at Vdd to retain the MV level at part of the N BBLs if corresponding part of the N SBLs are at Vdd level and to allow the remaining part of the N BBLs to drop to 0V if the corresponding part of the N SBLs are at the ground level, the data pattern then being held by switching the fourth gate signal from Vdd to 0V.
11. The HiNAND circuit of claim 10 wherein the Page Buffer circuit is configured to set a first data pattern with MV or 0V levels in a first set of N BBL metal1 lines associated with a first set of N Strings of HiNAND memory cells in a first Block and subsequently to at least set a second data pattern with MV or 0V levels in a second set of N BBL metal1 lines associated with a second set of N Strings of HiNAND memory cells in a second Block, the first Block being selected from one or more Segments of one or more Groups, the second Block being selected from an alternative one of the one or more Segments of either the same or alternative one of the one or more Groups.
12. The HiNAND circuit of claim 11 wherein the first N Strings of HiNAND memory cells comprises a first page of cells at a first relative String location and the second N Strings of HiNAND memory cells comprises a second page of cells at a second relative String location, the second page and the first page connecting to a same WL decoder, the first page of cells and the second page of cells being simultaneously programmed to store data respectively in accordance with the first data pattern and the second data pattern independently pre-set in a serial pipe-line.
13. The HiNAND circuit of claim 8 wherein the N Strings of M NAND memory cells associated with the corresponding charged N BBLs in the selected Block are subjected to the precharge voltage ranging from Vdd up to 7V by setting gate signal of the second String-select transistor to smaller than Vdd and setting gate signal of the top String-select transistor to 0V for keeping drain voltage of each String of M NAND memory cells less than 0.5V to avoid cell-channel punch-through, followed by switching the gate signal of the first String-select transistor from Vdd to up to 10V for discharging the part of the N Strings containing an On-cell with threshold level below a predetermined check voltage for ReadProgram-VerifyErase-Verify operation in a selected page to the corresponding common source line at ground 0V while retaining the precharge voltage for remaining part of the N Strings containing an Off-cell in a page with threshold level above the predetermined check voltage in the selected page.
14. The HiNAND circuit of claim 13 wherein the part of the N Strings containing an On-cell in the selected page is configured to give the corresponding part of N GBLs directly a 0V by setting the second gate signal to Vdd, and the remaining part of the N Strings containing an Off-cell in the selected page is configured to share the charges within each corresponding BBL metal1 line and SBL metal2 line respectively with each corresponding GBLs to provide a reduced GBL voltage as 1J of the precharge voltage or less by setting the second gate signal to Vdd, the reduced GBL voltages forming a data pattern represented by 1J of precharge voltage or 0V levels associated with the selected page.
15. The HiNAND circuit of claim 14 wherein the Page Buffer circuit comprises a Multiplier circuit to increase the reduced GBL voltage at 1J of precharge voltage level to a value sufficiently large to be sensed and amplified by a Latch sense amplifier to a Vdd level latched to a data node in the Page Buffer circuit, thereby converting the data pattern represented by 1J of precharge voltage or 0V levels associated with the selected page to a bit data in Vdd or 0V levels.
16. The HiNAND circuit of claim 1 wherein each memory cell is a 2-poly LV float-gate NMOS transistor or 1-poly MONOS or SONOS charge-trapping NMOS transistor configured to be a SLC type with two threshold states, or a MLC type with four threshold states, or a TLC type with 8 threshold states, or a XLC type with 16 threshold states.
17. The HiNAND circuit of claim 1 wherein each of the first String-select transistors, the second String-select transistors, the BBL-select transistors, the first SBL-select transistors, the second SBL-select transistors, the first GBL-select transistors, and the second GBL-select transistors is a medium high-voltage 1-poly NMOS transistor or shorted-2-poly NMOS transistor with identical device type, characteristics, and breakdown voltage.