Author: claimsbot

1) A substrate material for mounting a semiconductor device, of an aluminumsilicon carbide (Al\u2014SiC) composite alloy which comprises Al\u2014SiC alloy composition part and non alloy composition part, wherein silicon carbide granular particles are dispersed from 10 to 70% by weight in the composite alloy, and silicon carbide is distributed homogeneously in the Al\u2014SiC alloy composition part.
2) The substrate material for mounting a semiconductor device, as set forth in claim 1, fabricated by the sintering method of sintering a pre-formed mixed starting material powders, wherein the fluctuation of the concentration silicon carbide in the Al\u2014SiC alloy composition part is within 1% by weight.
3) The substrate material for mounting a semiconductor device, as set forth in claim 1, wherein the substrate material has a thermal conductivity of 100 Wm\xd7K or higher and a thermal expansion coefficient of 20\xd710\u22126\xb0 C. or lower.
4) The substrate material for mounting a semiconductor device as claimed in claim 1, wherein the silicon carbide granular particles are dispersed from 35 to 70% by weight.
5) The substrate material for mounting a semiconductor device, as set forth in claim 4, wherein the substrate material has a thermal conductivity of 180 Wm\xd7K or higher.
6) The substrate material for mounting a semiconductor device as claimed in claim 1, wherein the composite alloy contains aluminum carbide formed at an interface between aluminum or aluminum alloy and silicon carbide.
7) The substrate material for mounting a semiconductor device as claimed in claim 6, wherein the amount of the aluminum carbide is lower than 5% by weight.
8) The substrate material for mounting a semiconductor device as claimed in claim 7, wherein the silicon carbide composite alloy has a thermal conductivity of 180 Wm\xd7K or higher.
9) The substrate material for mounting a semiconductor device as claimed in claim 6, wherein aluminum carbide is distributed at the interface between the silicon carbide and the aluminum or aluminum alloy in such an amount that the ratio of the peak intensity for aluminum carbide (012) to that for aluminum (200) both determined by X-ray analysis with CuK8 line is not more than 0.025.
10) The substrate material for mounting a semiconductor device as claimed in claim 9, wherein the silicon carbide composite alloy has a thermal conductivity of 180 Wm\xd7K or higher.
11) The substrate material for mounting a semiconductor device as claimed in claim 1, wherein the composite alloy contains silicon as a component of a solid solution therein or as a precipitate.
12) The substrate material for mounting a semiconductor device as claimed in claim 1, wherein the aluminumsilicon carbide composite alloy contains nitrogen in an amount of from 0.01 to 1% by weight.
13) The substrate material for mounting a semiconductor device as claimed in claim 1, wherein the aluminumsilicon carbide composite alloy contains oxygen in an amount of from 0.05 to 0.5% by weight.
14) The substrate material for mounting a semiconductor device as claimed in claim 1, wherein the aluminumsilicon carbide composite alloy contains 3\u2014SiC as the silicon carbide.
15) The substrate material for mounting a semiconductor device as claimed in claim 1, wherein the silicon carbide granular particles have an average particle diameter of from 1 to 100 \u03bcm.
16) The substrate material for mounting a semiconductor device as claimed in claim 14, wherein the silicon carbide granular particles have an average particle diameter of from 10 to 80 \u03bcm.
17) The substrate for mounting a semiconductor device, which comprises a substrate made of the substrate material as claimed in claim 1, and a coating layer coated on a surface of the substrate.
18) The substrate for mounting a semiconductor device, as claimed in claim 17, wherein the coating layer is a plating layer.
19) The substrate for mounting a semiconductor device, as claimed in claim 17, wherein the coating layer is a chromate film.
20) The substrate for mounting a semiconductor device, as claimed in claim 17, wherein the coating layer is a layer of an oxide of either aluminum or silicon.
21) The substrate for mounting a semiconductor device, as claimed in claim 17, wherein the coating layer is a multilayer structure film comprising a first metal layer having a Young’s modulus of 15,000 kgmm2 or lower and a second metal layer formed on the first metal layer, and the second metal layer is made of at least one metal selected from nickel and gold.
22) The substrate for mounting a semiconductor device, as claimed in claim 17, wherein the coating layer is a multilayer structure film comprising a first metal layer having a melting point of 600\xb0 C. or lower and a second metal layer formed on the first metal layer, and the second metal layer is made of at least one metal selected from nickel and gold.
23) The substrate for mounting a semiconductor device, as claimed in claim 17, wherein the coating layer comprises a layer of at least one organic resin selected from an epoxy resin, a silicone resin, a polyimide resin, and the like each containing a metallic filler or not.
24) The substrate for mounting a semiconductor device, as claimed in claim 23, wherein the coating layer further comprises a second metal layer made of at least one metal selected from nickel and gold, formed on the layer of organic resin.
25) The substrate for mounting a semiconductor device, as claimed in claim 17, wherein the coating layer comprises aluminum as the main component.
26) The substrate for mounting a semiconductor device, as claimed in claim 25, wherein the coating layer is made up of crystal grains comprising aluminum and having a diameter of from 0.1 to 10 \u03bcm.
27) The substrate for mounting a semiconductor device, as claimed in claim 26, wherein the coating layer is further covered with an oxide layer having a thickness of from 10 to 800 \u212b.
28) The substrate for mounting a semiconductor device, as claimed in claim 25, wherein the substrate has a surface roughness of from 0.1 to 20 \u03bcm in terms of Rmax.
29) The substrate for mounting a semiconductor device, as claimed in claim 28, wherein the substrate has a surface roughness of from 0.1 to 8 \u03bcm in terms of Rmax.
30) The substrate for mounting a semiconductor device, as claimed in claim 28, wherein the substrate comprises holes having a depth of 100 \u03bcm or smaller on the surface thereof.
31) The substrate for mounting a semiconductor device, as claimed in claim 28, wherein the aluminum coating layer has a purity of 99.9% or higher.
32) The substrate for mounting a semiconductor device, as claimed in claim 25, wherein the coating layer has a thickness of from 1 to 100 \u03bcm.
33) The substrate for mounting a semiconductor device, as claimed in claim 32, wherein the coating layer has a thickness of from 1 to 20 \u03bcm.
34) A semiconductor device, which comprises the substrate material as claimed in claim 1 or the substrate as claimed in claim 17, and a semiconductor chip mounted on the substrate.
35) A method of producing a substrate material of an aluminumsilicon carbide composite alloy by the sintering method, wherein the method comprises steps of:
mixing an aluminum powder and silicon carbide powder to form an aluminumsilicon carbide starting powder mixed homogeneously;
compacting the aluminumsilicon carbide starting powder having a silicon carbide content of from 10 to 70% by weight to form a compact;
and sintering the compact at a temperature of 600\xb0 C. or higher in a non-oxidizing atmosphere to thereby obtain an aluminumsilicon carbide composite alloy.
36) The method of producing a substrate material as claimed in claim 35, wherein the sintering step is conducted at the temperature within a range of from 600 to 750\xb0 C.
37) The method of producing a substrate material as claimed in claim 35, wherein the sintering step is conducted in a nitrogen atmosphere having a nitrogen concentration of 99% by volume or higher.
38) The method of producing a substrate material as claimed in claim 35, wherein the sintering step is conducted in an atmosphere having an oxygen concentration of 200 ppm or lower.
39) The method of producing a substrate material as claimed in claim 35, wherein the sintering step is conducted in an atmosphere having a dew point of \u221220\xb0 C. or lower.
40) A method of producing a substrate for mounting a semiconductor chip as claimed in claim 35, further comprising the step of repressing the aluminumsilicon carbide composite alloy obtained by sintering the aluminumsilicon carbide starting powder, or repressing them and then heating in a non-oxidizing atmosphere so as to prevent from oxidizing aluminum.
41) A method of producing a substrate made of an aluminumsilicon carbide composite alloy by the sintering method, comprising the steps of:
mixing an aluminum powder and silicon carbide powder to form an aluminumsilicon carbide starting powder having a silicon carbide content of from 10 to 70% by weight;
compacting the aluminumsilicon carbide starting powder to form a compact;
sintering the compact at a temperature of 600\xb0 C. or higher in a non-oxidizing atmosphere for aluminum to thereby obtain ed substrate made of an aluminumsilicon carbide composite alloy;
and forming a coating layer on a surface of the pre-formed substrate to thereby obtain the substrate.
42) The method of producing a substrate as claimed in claim 41, wherein the step of forming a coating layer is:
heating the substrate in an oxidizing atmosphere;
or exposing the substrate to a steam atmosphere.
43) The method of producing a substrate as claimed in claim 41, wherein the step of forming a coating layer comprises steps of:
forming a layer of a metal having a Young’s modulus of 15,000 kgmm2 or lower on the substrate material;
polishing the metal layer;
and plating the polished metal layer with at least one metal selected from nickel and gold.
44) The method of producing a substrate as claimed in claim 41, wherein the step of forming a coating layer comprises steps of:
forming a layer of a metal having a melting point of 600\xb0 C. or lower on the substrate surface;
heating the metal layer to a temperature not higher than 600\xb0 C.; and plating the metal layer with at least one metal selected from nickel and gold.
45) The method of producing a substrate as claimed in claim 41, wherein the step of forming a coating layer comprises steps of:
forming a layer of at least one organic resin selected from an epoxy resin, a silicone resin, a polyimide resin, and the like each containing a metallic filler or not on the substrate surface.
46) The method of producing a substrate as claimed in claim 45, wherein the step of forming a coating layer further comprises steps of:
plating a metal layer made of at least one metal selected from nickel and gold on the layer of organic resin.
47) The method of producing a substrate as claimed in claim 46, wherein the forming step of a layer of a metal having a Young’s modulus of 15,000 kgmm2 or lower on the substrate is conducted by barrel plating.
48) The method of producing a substrate as claimed in claim 47, whrein the barrel plating is conducted in a container which contains metal spheres having a particle diameter of from 0.1 to 10 mm and having the same composition as the deposit to be formed.
49) The method of producing a substrate as claimed in claim 48, wherein the spheres contained in the container for use in barrel plating have a surface area which is at least two times that of the corresponding true spheres.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of releasing a restricted functionality of an electronic appliance, comprising:
(1) a selected host device connected to said electronic appliance executing a functionality restriction release program to release the restricted functionality of said electronic appliance;
(2) communicating, between the selected host device and said electronic appliance, information relating to the release of the restricted functionality of said electronic appliance, wherein the selected host device communicates said information to said electronic appliance;
(3) as a result of acts (1) and (2), releasing the restricted functionality of said electronic appliance;
the selected host device determining the status of said restricted functionality;
enabling a driver on said selected host device to control said released functionality on said electronic appliance; and
disabling one or more drivers on one or more other host devices from controlling one or more functionalities of said electronic appliance for which a functionality restriction has not been released.
2. The method of claim 1, further comprising:
identifying one or more of said host devices; and
wherein said restricted functionality of said electronic appliance is released so that said restricted functionality may be used by only one of said one or more host devices.
3. The method of claim 1, wherein said released functionality may be used by said selected host device connected to said electronic appliance.
4. The method of claim 1, further comprising releasing, as a result of said communicating act, the restricted functionality of said electronic appliance so that said functionality may be used by multiple host devices connected to said electronic appliance.
5. The method of claim 1, further comprising installing the functionality restriction release program stored on recording media.

1. A photoelectric conversion device comprising:
a light-absorbing layer including a compound semiconductor capable of photoelectric conversion, the compound semiconductor containing a group Ib element including Cu, a group IIIb element and a group VIb element; and
a semiconductor layer on one surface-side of the light-absorbing layer, the semiconductor layer having a plane orientation different from that of the light-absorbing layer, the semiconductor layer containing a group Ib element including Cu, at least one element selected from Cd, Zn and In, and a group VIb element,
wherein the photoelectric conversion device includes
a region in which Cu content decreases from the light-absorbing layer to the semiconductor layer across a junction interface; and
a plurality of Cu-deficient portions which are present at mutual intervals and a remaining portion other than the Cu-deficient portions are present in the one surface-side of the light-absorbing layer, the Cu-deficient portions including a higher content of the at least one element selected from Cd, Zn, and In than the remaining portion and a lower content of Cu than the remaining portion.
2. The photoelectric conversion device according to claim 1, wherein the group VIb element included in the light-absorbing layer includes Se and the group VIb element included in the semiconductor layer includes S, wherein S content increases from the light-absorbing layer to the semiconductor layer across the junction interface.
3. The photoelectric conversion device according to claim 1, wherein the light-absorbing layer has a plane orientation of (112) and the semiconductor layer has a plane orientation of (111).
4. The photoelectric conversion device according to claim 1, wherein the region extends 10 nm or more from the junction interface in a direction perpendicular to the junction interface.
5. The photoelectric conversion device according to claim 1, wherein the Cu-deficient portion has an average width in a direction parallel to the junction interface of 10 to 300 nm in a cross-sectional view of the light-absorbing layer taken in its thickness direction.
6. The photoelectric conversion device according to claim 1, wherein the Cu-deficient portion has an average depth in a direction perpendicular to the junction interface of 10 nm or more in a cross-sectional view of the light-absorbing layer taken in its thickness direction.
7. The photoelectric conversion device according to claim 1, wherein the Cu-deficient portion has an occupancy ratio in the junction interface of 10% or more in a cross-sectional view of the light-absorbing layer taken in its thickness direction.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of forming an insulated gate bipolar transistor (IGBT) device, comprising:
forming a p-type drift layer;
forming an n-type well in the p-type drift layer;
epitaxially growing a p-type channel adjustment layer on the p-type drift layer and on the n-type well;
implanting p-type dopant ions to form a p-type emitter region extending through the channel adjustment layer and into the n-type well at a surface of the drift layer, the p-type emitter region at least partially defining a channel region in the n-type well adjacent the p-type emitter region;
implanting n-type dopant ions to form an n-type connector region extending through the channel adjustment layer and into the n-type well at a surface of the drift layer;
forming a gate oxide layer on the channel region; and
forming a gate on the gate oxide layer.
2. The method of claim 1, further comprising annealing the implanted ions.
3. The method of claim 2, further comprising:
forming a graphite coating on the channel adjustment layer, wherein annealing the implanted ions comprises annealing the channel adjustment layer and the graphite coating; and
removing the graphite coating after annealing the implanted ions.
4. The method of claim 3, further comprising crystallizing the graphite coating before annealing the implanted ions.
5. The method of claim 3, wherein annealing the implanted ions comprises annealing the implanted ions at a temperature greater than 1700\xb0 C.
6. The method of claim 3, wherein annealing the implanted ions comprises annealing the implanted ions at a temperature greater than 1800\xb0 C.
7. The method of claim 1, wherein forming the gate oxide layer comprises forming the gate oxide layer in dry O2, the method further comprising annealing the gate oxide layer in wet O2.
8. The method of claim 7, wherein forming the gate oxide layer comprises forming the gate oxide layer in dry O2 at a temperature less than or equal to about 1200\xb0 C.
9. The method of claim 7, further comprising annealing the gate oxide layer in an inert atmosphere at a temperature less than or equal to about 1200\xb0 C. after forming the gate oxide layer and before annealing the gate oxide layer in wet O2.
10. The method of claim 7, wherein annealing the gate oxide layer in wet O2 comprises annealing the gate oxide layer in wet O2 at a temperature less than or equal to about 950\xb0 C.
11. The method of claim 10, wherein annealing the gate oxide layer in wet O2 comprises annealing the gate oxide layer in wet O2 for at least one hour.
12. The method of claim 7, wherein annealing the oxide layer in wet O2 comprises generating pyrogenic steam in a pyrogenic chamber, supplying the pyrogenic steam to an anneal chamber, and annealing the oxide layer in the anneal chamber.
13. The method of claim 12, wherein generating pyrogenic steam comprises heating the pyrogenic chamber, supplying hydrogen and oxygen gas to the pyrogenic chamber, and combusting the hydrogen gas and the oxygen gas to form the pyrogenic steam, wherein the hydrogen gas and the oxygen gas are supplied to the pyrogenic chamber at a molecular ratio of hydrogen to oxygen of about 1.8 or more.
14. The method of claim 1, further comprising implanting p-type dopant ions into the drift layer to form a HET region adjacent to the n-type well, and wherein the p-type emitter region is spaced apart from the NET region and defines a channel region between the p-type emitter region and the JFBT region.
15. The method of claim 1, wherein the channel adjustment layer is formed to have a thickness of about 0.1 \u03bcm to about 0.5 \u03bcm, and wherein the channel adjustment layer has a net acceptor concentration of about 1\xd71016 cm\u22123 to about 5\xd71018 cm\u22123.
16. The method of claim 1, wherein the drift layer comprises an epitaxial silicon carbide layer.
17. The method of claim 1, where the forming the p-type drift layer comprises forming the p-type drift layer on an n-type substrate.
18. The method of claim 17, wherein the substrate comprises silicon carbide.
19. The method of claim 1, wherein a distance from a bottom of the p-type emitter region to a bottom of the n-type well region is equal to or greater than about 0.45 \u03bcm.
20. A method of forming an insulated gate bipolar transistor (IGBT) device, comprising:
forming a drift layer of a first conductivity type;
forming a well of a second conductivity type in the drift layer;
forming a JFET region with first conductivity type dopant ions in the drift layer;
forming a channel adjustment layer of the first conductivity type on the HET region and the well;
implanting first conductivity type dopant ions to form an emitter region of the first conductivity type extending through the channel adjustment layer and into the well, wherein the emitter region is spaced apart from the NET region by the well;
implanting second conductivity type dopant ions to form a connector region of the second conductivity type adjacent the emitter region;
forming a gate oxide layer on the channel region; and
forming a gate on the gate oxide layer.
21. The method of claim 20, wherein forming the HET region comprises epitaxially growing the JFET region with additional first conductivity type dopant ions on the drift layer.
22. The method of claim 20, wherein forming the HET region comprises forming the JFET region with a dopant concentration of about 1\xd71016 cm\u22123.
23. The method of claim 20, wherein forming the JFET region comprises implanting aluminum in the drift lay adjacent the well.
24. The method of claim 20, further comprising:
forming a graphite coating on the channel adjustment layer;
annealing the implanted ions in the channel adjustment layer;
annealing the graphite coating; and
removing the graphite coating after annealing the implanted ions.