Author: claimsbot

1. A nonvolatile memory structure comprising:
a semiconductor substrate;
a transistor located on a surface of said semiconductor substrate, said transistor comprising a first dielectric on the surface of said semiconductor substrate, a conducting gate stacked above said first dielectric, and several first doped regions in said semiconductor substrate as a source and a drain thereof, respectively; and
a capacitor located on the surface of said semiconductor substrate, said capacitor comprising a second doped region in said semiconductor substrate, a second dielectric on a surface of said second doped region, and a second conducting gate stacked above said second dielectric, said first and second conducting gates being electrically connected together as a single floating gate.
2. The nonvolatile memory structure as claimed in claim 1, wherein said transistor is a MOSFET.
3. The nonvolatile memory structure as claimed in claim 1, wherein said semiconductor is p-type or n-type.
4. The nonvolatile memory structure as claimed in claim 1, wherein said first doped region and said second doped region are doped with impurities of a first type, while said semiconductor substrate is doped with impurities of a second type, and said first type impurities and said second type impurities are different.
5. The nonvolatile memory structure as claimed in claim 3, wherein if said semiconductor substrate is p-type, then said first doped region and said second doped region are n-type.
6. The nonvolatile memory structure as claimed in claim 4, wherein if said semiconductor substrate is p-type, then said first doped region and said second doped region are n-type.
7. The nonvolatile memory structure as claimed in claim 3, wherein if said semiconductor substrate is n-type, then said first doped region and said second doped region are p-type.
8. The nonvolatile memory structure as claimed in claim 4, wherein if said semiconductor substrate is n-type, then said first doped region and said second doped region are p-type.
9. The nonvolatile memory structure as claimed in claim 1, wherein a third doped region is provided in said semiconductor substrate and below said first doped region, and said third doped region is doped with impurities of the same type with said second doped region.
10. The nonvolatile memory structure as claimed in claim 7, wherein if said semiconductor substrate is n-type, then said second and third doped regions are p-type.
11. The nonvolatile memory structure as claimed in claim 7, wherein if said semiconductor substrate is p-type, then said second and third doped regions are n-type.
12. A method of operating a nonvolatile memory, said nonvolatile memory comprising several first doped regions as a source and a drain and a first conducting gate, and a capacitor structure composed of a second doped region and a second conducting gate on a p-type semiconductor substrate, said first and second conducting gates being connected together to form a single floating gate, a substrate voltage, a source voltage, a drain voltage, and a control gate voltage being applied on said substrate, said source, said drain and said second doped region, respectively, said method comprising:
performing a program step to let said substrate voltage be grounded or nonzero but close to zero and let said source voltage and said drain voltage be higher than said substrate voltage but much smaller than said control gate voltage; and
performing an erase step to let said source voltage and said drain voltage be higher than said substrate voltage but much smaller than said control gate voltage.
13. A method of operating a nonvolatile memory, said nonvolatile memory comprising an N-well, several first doped regions as a source and a drain and a first conducting gate, and a capacitor structure composed of a second doped region and a second conducting gate on a p-type semiconductor substrate, said first and second conducting gates being connected together to form a single floating gate, a well voltage, a substrate voltage, a source voltage, a drain voltage, and a control gate voltage being applied on said N-well, said substrate, said source, said drain and said second doped region, respectively, said method comprising:
performing a program step to let said substrate voltage be grounded or nonzero but close to zero and let said well voltage and said drain voltage be higher than said source voltage and let said source voltage be higher than said control gate voltage and let said control gate voltage be higher than said substrate voltage; and
performing an erase step to let said well voltage be much larger than said substrate voltage and said control gate voltage be much larger than said well voltage and let said source voltage and said drain voltage be smaller than said substrate voltage.
14. A method of operating a nonvolatile memory, said nonvolatile memory comprising several first doped regions as a source and a drain and a first conducting gate and a capacitor structure composed of a second doped region and a second conducting gate on an n-type semiconductor substrate, said first and second conducting gates being connected together to form a single floating gate, a substrate voltage, a source voltage, a drain voltage, and a control gate voltage being applied on said substrate, said source, said drain and said second doped region, respectively, said method comprising:
performing a program step to let said substrate voltage be grounded or nonzero but close to zero and let said source voltage and said drain voltage be lower than said substrate voltage but much higher than said control gate voltage; and
performing an erase step to let control gate voltage be smaller than said substrate voltage and let said source voltage and said drain voltage be negative but have much smaller magnitudes than that of said control gate voltage.
15. A method of operating a nonvolatile memory, said nonvolatile memory comprising a P-well, several first doped regions as a source and a drain and a first conducting gate and a capacitor structure composed of a second doped region and a second conducting gate on an n-type semiconductor substrate, said first and second conducting gates being connected together to form a single floating gate, a well voltage, a substrate voltage, a source voltage, a drain voltage, and a control gate voltage being applied on said P-well, said substrate, said source, said drain and said second doped region, respectively, said method comprising:
performing a program step to let said substrate voltage be grounded or nonzero but close to zero and let said source voltage be higher than said well voltage and let said drain voltage be higher than said source voltage and let said control gate voltage be higher than said source voltage but smaller than said substrate voltage; and
performing an erase step to let said well voltage be much smaller than said substrate voltage and let said control gate voltage be much smaller than said well voltage and let said source voltage and said drain voltage be higher than said substrate voltage.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A voltage balancing unit for a symmetric monopole high voltage direct current, HVDC, transmission line being arranged for interconnecting a first voltage source converter, VSC, and a second VSC, the transmission line comprising:
a first pole and a second pole, and two pairs of first arresters, a first pair being arranged at a first end of the transmission line and a second pair being arranged at a second end of the transmission line, a first arrester of either pair being connected between the first pole and ground and a second arrester of either pair being connected between the second pole and ground, the first arresters having a first switching impulse protective level, SIPL,
wherein the voltage balancing unit is arranged to perform voltage balancing for a voltage unbalance caused by an earth fault and comprises:
a pair of second arresters having a second SIPL which is less than the first SIPL, and
a switching device configured to:
connect, through being closed after the earth fault has been cleared and in response to determining that the voltage unbalance exists between the first pole and the second pole, a first arrester of the pair of second arresters between the first pole and ground, and a second arrester of the pair of second arresters between the second pole and ground, and
disconnect, in response to determining that the voltage unbalance is cleared, the second arresters.
2. The voltage balancing unit according to claim 1, wherein the pair of second arresters is arranged at either of the ends of the transmission line.
3. A high voltage direct current, HVDC, power transmission unit comprising:
a first voltage source converter, VSC, comprising an alternating current, AC, side and a direct current, DC, side, the AC side of the first VSC being connectable to a first AC network,
a symmetric monopole transmission line being arranged for interconnecting the DC side of the first VSC and a DC side of a second VSC, an AC side of the second VSC being connectable to a second AC network, the transmission line comprising a first pole and a second pole, and
a voltage balancing unit according to claim 2.
4. The voltage balancing unit according to claim 1, wherein the first SIPL is in the range of 1.8 to 2.0 per unit, p.u., and the second SIPL is in the range of 1.15 to 1.20 p.u.
5. A high voltage direct current, HVDC, power transmission unit comprising:
a first voltage source converter, VSC, comprising an alternating current, AC, side and a direct current, DC, side, the AC side of the first VSC being connectable to a first AC network,
a symmetric monopole transmission line being arranged for interconnecting the DC side of the first VSC and a DC side of a second VSC, an AC side of the second VSC being connectable to a second AC network, the transmission line comprising a first pole and a second pole, and
a voltage balancing unit according to claim 4.
6. The voltage balancing unit according to claim 1, wherein the switching device comprises:
a pair of high speed switches, HSSs, a first HSS being connected in series with the first arrester of the pair of second arresters and a second HSS being connected in series with the second arrester of the pair of second arresters, the HSSs being in an open state under normal operation, and
a pair of disconnectors, a first disconnector being connected in series with the first arrester of the pair of second arresters and a second disconnector being connected in series with the second arrester of the pair of second arresters, the disconnectors being in a closed state under normal operation,
wherein the switching means is further configured to:
close, in response to determining that a voltage unbalance exists, the HSSs, and
in response to determining that the voltage unbalance is cleared:
open the disconnectors,
open the HSSs, and
close the disconnectors.
7. A high voltage direct current, HVDC, power transmission unit comprising:
a first voltage source converter, VSC, comprising an alternating current, AC, side and a direct current, DC, side, the AC side of the first VSC being connectable to a first AC network,
a symmetric monopole transmission line being arranged for interconnecting the DC side of the first VSC and a DC side of a second VSC, an AC side of the second VSC being connectable to a second AC network, the transmission line comprising a first pole and a second pole, and
a voltage balancing unit according to claim 6.
8. A high voltage direct current, HVDC, power transmission unit comprising:
a first voltage source converter, VSC, comprising an alternating current, AC, side and a direct current, DC, side, the AC side of the first VSC being connectable to a first AC network,
a symmetric monopole transmission line being arranged for interconnecting the DC side of the first VSC and a DC side of a second VSC, an AC side of the second VSC being connectable to a second AC network, the transmission line comprising a first pole and a second pole, and
a voltage balancing unit according to claim 1.
9. The HVDC power transmission unit according to claim 8, further comprising an AC circuit breaker being arranged for:
disconnecting, in response to determining that a voltage unbalance exists, the first VSC from the first AC network, and
reconnecting, in response to determining that the voltage unbalance is cleared, the first VSC to the first AC network.
10. The HVDC power transmission unit according to claim 8, further comprising a pair of DC circuit breakers being arranged for:
disconnecting, in response to determining that a voltage unbalance exists, the transmission line from the first VSC, and
reconnecting, in response to determining that the voltage unbalance is cleared, the transmission line to the first VSC.
11. A method of voltage balancing in a symmetric monopole high voltage direct current, HVDC, transmission line being arranged for interconnecting a first voltage source converter, VSC, and a second VSC, the transmission line comprising:
a first pole and a second pole, and two pairs of first arresters, a first pair being arranged at a first end of the transmission line and a second pair being arranged at a second end of the transmission line, a first arrester of either pair being connected between the first pole and ground and a second arrester of either pair being connected between the second pole and ground, the first arresters having a first switching impulse protective level, SIPL,
the method being performed for a voltage unbalance caused by an earth fault and comprising the steps of:
providing a pair of second arresters having a second SIPL which is less than the first SIPL,
connecting, through being closed after the earth fault has been cleared and in response to determining that the voltage unbalance exists between the first pole and the second pole, a first arrester of the pair of second arresters between the first pole and ground, and a second arrester of the pair of second arresters between the second pole and ground, and
disconnecting, in response to determining that the voltage unbalance is cleared, the second arresters.
12. The method according to claim 11, wherein the pair of second arresters is connected at either of the ends of the transmission line.
13. The method according to claim 11, wherein the first SIPL is in the range of 1.8 to 2.0 per unit, p.u., and the second SIPL is in the range of 1.15 to 1.20 p.u.
14. The method according to claim 11, further comprising:
providing a pair of high speed switches, HSSs, a first HSS being connected in series with the first arrester of the pair of second arresters and a second HSS being connected in series with the second
arrester of the pair of second arresters, the HSSs being in an open state under normal operation, and
providing a pair of disconnectors, a first disconnector being connected in series with the first arrester of the pair of second arresters and a second disconnector being connected in series with the second arrester of the pair of second arresters, the disconnectors being in a closed state under normal operation,
wherein the step of connecting the second arresters comprises:
closing the HSSs, and

wherein the step of disconnecting the second arresters comprises:
opening the disconnectors,
opening the HSSs, and
closing the disconnectors.
15. The method according to claim 11, wherein the first VSC is connectable to a first AC network, the method further comprising the steps of:
disconnecting, in response to determining that a voltage unbalance exists, the first VSC from the first AC network, and
reconnecting, in response to determining that the voltage unbalance is cleared, the first VSC to the first AC network.
16. The method according to claim 11, further comprising the steps of: disconnecting, in response to determining that a voltage unbalance exists, the transmission line from the first VSC, and
reconnecting, in response to determining that the voltage unbalance is cleared, the transmission line to the first VSC.

1. A method for generating an identifier having a specified format and uniquely associated with a storage device, the method comprising:
receiving, from the storage device, an identifier associated with the storage device and having a first format which differs from the specified format;
generating a data string having a predefined length from the identifier associated with the storage device and having the first format, the predefined length of the string determined from the specified format;
combining additional identification data with the data string having the predefined length;
generating the identifier having the specified format by reformatting the additional identification data and the data string having the predefined length according to one or more formatting parameters associated with the specified format; and
storing the identifier having the specified format in a computer-readable storage medium.
2. The method of claim 1 wherein the identifier associated with the storage device and having the first format which differs from the specified format comprises an AT Attachment (\u201cATA\u201d) serial number.
3. The method of claim 1 wherein the identifier having the specified format comprises a Network Address Authority (\u201cNAA\u201d) identifier.
4. The method of claim 1, wherein generating the data string having the predefined length from the identifier associated with the storage device and having the first format comprises:
applying a hash function to the identifier associated with the storage device and having the first format.
5. The method of claim 4, wherein applying the hash function to the identifier associated with the storage device and having the first format comprises:
identifying a first byte of the identifier associated with the storage device and having the first format;
logically shifting the first byte by a shift amount to produce a shifted first byte;
adding the shifted first byte to an accumulator value;
incrementing the shift amount by a specified value to generate an incremented shift amount;
identifying a second byte of the identifier;
logically shifting the second byte by the incremented shift amount to produce a shifted second byte; and
adding the shifted second byte to the accumulator value.
6. The method of claim 5, wherein incrementing the shift amount by the specified value to generate the incremented shift amount comprises:
responsive to the incremented shift amount exceeding a threshold value, initializing the incremented shift amount to an initial value.
7. The method of claim 5, further comprising:
generating the data string having the predefined length from a subset of the accumulator.
8. The method of claim 7, wherein the subset of the accumulator comprises a least-significant three bytes of the accumulator.
9. The method of claim 8, wherein the subset of the accumulator comprises a least-significant three bytes of the accumulator.
10. The method of claim 5, further comprising:
identifying an upper byte of the accumulator;
identifying a lower byte of the accumulator;
generating a modified lower byte by performing an exclusive-OR of the upper byte and the lower byte; and
generating the data string having the predefined length from a subset of the accumulator and the modified lower byte.
11. The method of claim 1, wherein the additional identification data comprises an Organizationally Unique Identifier (\u201cOUI\u201d) associated with an entity.
12. The method of claim 1, wherein the additional identification data comprises a type identifier associated with the specified format.
13. The method of claim 1, wherein reformatting the additional identification data and the data string having the predefined length according to one or more formatting parameters associated with the specified format comprises:
generating a data packet having a specified packet size and including specified data types.
14. The method of claim 13, wherein the specified packet size comprises eight bytes, and the specified data types comprise an Organizationally Unique Identifier, a type identifier associated with the specified format and the data string having the predefined length.
15. A computer readable storage medium storing a computer program product including instructions executable by a processor of a computing device to perform a computer-implemented method for generating an identifier having a specified format and uniquely associated with a storage device, the method comprising:
receiving, from the storage device, an identifier associated with the storage device and having a first format which differs from the specified format;
generating a data string having a predefined length from the identifier associated with the storage device and having the first format, the predefined length of the string determined from the specified format;
combining additional identification data with the data string having the predefined length;
generating the identifier having the specified format by reformatting the additional identification data and the data string having the predefined length according to one or more formatting parameters associated with the specified format; and
storing the identifier having the specified format in a computer-readable storage medium.
16. The computer readable storage medium of claim 15, wherein the identifier associated with the storage device and having the first format which differs from the specified format comprises an AT Attachment (\u201cATA\u201d) serial number.
17. The computer readable storage medium of claim 15, wherein the identifier having the specified format comprises a Network Address Authority (\u201cNAA\u201d) identifier.
18. The computer readable storage medium of claim 15, wherein generating the data string having the predefined length from the identifier associated with the storage device and having the first format comprises:
applying a hash function to the identifier associated with the storage device and having the first format.
19. The computer readable storage medium of claim 18, wherein applying the hash function to the identifier associated with the storage device and having the first format comprises:
identifying a first byte of the identifier associated with the storage device and having the first format;
logically shifting the first byte by a shift amount to produce a shifted first byte;
adding the shifted first byte to an accumulator value;
incrementing the shift amount by a specified value to generate an incremented shift amount;
identifying a second byte of the identifier;
logically shifting the second byte by the incremented shift amount to produce a shifted second byte; and
adding the shifted second byte to the accumulator value.
20. The computer readable storage medium of claim 19, wherein incrementing the shift amount by the specified value to generate the incremented shift amount comprises:
responsive to the incremented shift amount exceeding a threshold value, initializing the incremented shift amount to an initial value.
21. The computer readable storage medium of claim 20, further comprising:
generating the data string having the predefined length from a subset of the accumulator.
22. The computer readable storage medium of claim 15, wherein the additional identification data comprises an Organizationally Unique Identifier (\u201cOUI\u201d) associated with an entity.
23. The computer readable storage medium of claim 15, wherein the additional identification data comprises a type identifier associated with the specified format.
24. The computer readable storage medium of claim 15, wherein reformatting the additional identification data and the data string having the predefined length according to one or more formatting parameters associated with the specified format comprises:
generating a data packet having a specified packet size and including specified data types.
25. The computer readable storage medium of claim 24, wherein the specified packet size comprises eight bytes, and the specified data types comprise an Organizationally Unique Identifier, a type identifier associated with the specified format and the data string having the predefined length.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A non-transitory machine readable medium of a controller of a network control system for configuring a plurality of middlebox instances to implement a middlebox in a distributed manner in a plurality of hosts, the non-transitory machine readable medium storing sets of instructions for:
assigning a first set of identifiers to a first middlebox instance that associates an identifier in the first set with a first packet; and
assigning a second set of identifiers to a second middlebox instance that associates an identifier in the second set with a second packet.
2. The non-transitory machine readable medium of claim 1, wherein none of the identifiers in the first set is identical with any identifier in the second set.
3. The non-transitory machine readable medium of claim 1, wherein the first packet and the second packet have identical source network address and identical destination network address.
4. The non-transitory machine readable medium of claim 1, wherein a number of identifiers in the first set is different than a number of identifiers in the second set.
5. The non-transitory machine readable medium of claim 1, wherein the first middlebox instance associates the identifier in the first set with the first packet by replacing a source port number of the first packet with the identifier in the first set.
6. The non-transitory machine readable medium of claim 1, wherein at least one of the identifiers in the first set is identical with one of the identifiers in the second set.
7. The non-transitory machine readable medium of claim 1, wherein the first set of identifiers and the second set of identifiers are identical sets.
8. The non-transitory machine readable medium of claim 1, wherein the identifier in the first set and the identifier in the second set are identical.
9. The non-transitory machine readable medium of claim 1, wherein the first packet and the second packet have different destination addresses.
10. A non-transitory machine readable medium of a controller of a network control system for configuring a plurality of middlebox instances to implement a middlebox in a distributed manner in a plurality of hosts, the non-transitory machine readable medium storing sets of instructions for:
receiving a request for a first set of identifiers from a first middlebox instance;
determining whether the first set of identifiers are available; and
when the first set of identifiers are available, assigning the first set of identifiers to the first middlebox instance.
11. The non-transitory machine readable medium of claim 10, wherein the sets of instructions further comprise a set of instructions for:
after assigning the first set of identifiers to the first middlebox instance, recording that the first set of identifiers are not available.
12. The non-transitory machine readable medium of claim 10, wherein the sets of instructions further comprise a set of instructions for:
when the first set of identifiers are not available, sending a message indicating the first set of identifiers are not available to the first middlebox instance.
13. The non-transitory machine readable medium of claim 10, wherein the sets of instructions further comprise sets of instructions for:
receiving a request to release a second set of identifiers from a second middlebox instance; and
recording that the second set of identifiers are available.
14. The non-transitory machine readable medium of claim 10, wherein the sets of instructions further comprise sets of instructions for:
after assigning the first set of identifiers to the first middlebox instance, determining whether the first middlebox instance is alive; and
when the first middle instance is not alive, recording that the first set of identifiers are available.
15. A non-transitory machine readable medium of a first controller of a network control system for configuring a plurality of middlebox instances to implement a middlebox in a distributed manner in a plurality of hosts, the network control system comprising a plurality of controllers, the non-transitory machine readable medium storing sets of instructions for:
receiving configuration data for configuring the middlebox instances to provide source network address translation (SNAT) service to packets coming to the middlebox instances;
identifying a set of other controllers in the network control system that manage the middlebox instances; and
directing the identified set of other controllers to send the configuration data to the middlebox instances.
16. The non-transitory machine readable medium of claim 15, wherein the configuration data include a set of addresses to which the middlebox instances translate source network address of the packets.
17. The non-transitory machine readable medium of claim 15, wherein the first controller is a logical controller and the identified set of other controllers are physical controllers.
18. The non-transitory machine readable medium of claim 15, wherein the network control system is for generating physical control plane data for managing first and second managed forwarding elements that implement forwarding operations associated with a first logical datapath set, wherein the sets of instructions further comprise a set of instructions for converting logical control plane data for the first logical datapath set to universal physical control plane data.
19. The non-transitory machine readable medium of claim 18, wherein the first controller is a master controller for the first logical datapath set, wherein each of the identified set of other controllers is a master controller for a set of managed forwarding elements that are hosted in the same middlebox instances in which the middlebox instances are hosted.
20. The non-transitory machine readable medium of claim 15, wherein the configuration data include at least one mapping of a pair of addresses.