Author: claimsbot

1. A method for increasing wireless networking speed for use between an electronic device equipped with a wireless network apparatus and a wireless network having a group of wireless network base stations, said method comprising:
(A) providing the wireless network apparatus with two medium access control (MAC) addresses so as to simulate two wireless network cards;
(B) selecting, from among the group of wireless network base stations, two wireless network base stations respectively for the wireless network cards; and
(C) making the electronic device simultaneously communicate with the selected wireless network base stations using the wireless network cards;
wherein step (B) further comprises:
(B1) searching the wireless network for the group of wireless network base stations;
(B2) selecting, from among the group of wireless network base stations searched in sub-step (B1), one wireless network base station which is not recorded in a history list, which has a strongest signal strength, and which is not connected to one of said wireless network cards, the history list being used for recording those wireless network base stations that have been unsuccessful in establishing connection with one of the wireless network cards in the past;
(B3) attempting to establish connection between the wireless network base station selected in sub-step (B2) and one of the wireless network cards which is not connected with any wireless network base station of the group;
(B4) recording the wireless network base station selected in sub-step (B2) in the history list and returning to sub-step (B2) if it is determined that the attempt to establish the connection has failed in sub-step (B3);
(B5) returning to sub-step (B2) if it is determined that the attempt to establish the connection is successful in sub-step (B3) and that one of the wireless network cards has not established connection with one wireless network base station within the group; and
(B6) proceeding to step (C) if it is determined that the attempt to establish the connection is successful in sub-step (B3) and that each of the wireless network cards is connected to one wireless network base station within the group,
wherein in sub-step (B2), if all of the wireless network base stations in the group of wireless network base stations are recorded in the history list, one wireless network base station which has been recorded in the history list the longest is selected.
2. The method as claimed in claim 1,
wherein step (C) further comprises:
(C1) assigning a communication loading of 50% to each of the wireless network base stations selected in step (B);
(C2) making the electronic device communicate with each of the wireless network base stations selected in step (B) using a corresponding one of the wireless network cards with the communication loading assigned to the wireless network base station;
(C3) recording an actual communication loading and a response time for each of the wireless network base stations;
(C4) if it is determined with reference to the actual communication loadings and the response times recorded in sub-step (C3) for the wireless network base stations that it is necessary to adjust the assigned communication loadings for the two wireless network base stations and that the actual communication loading recorded in sub-step (C3) for each of the two wireless network base stations is not smaller than a predetermined loading threshold, adjusting the assigned communication loading for each of the two wireless network base stations according to an assignment rule, and returning to sub-step (C2);
(C5) if it is determined with reference to the actual communication loadings and the response times recorded in sub-step (C3) for the wireless network base stations that it is unnecessary to adjust the assigned communication loadings for the two wireless network base stations, returning to sub-step (C3);
(C6) if it is determined that the actual communication loading recorded in sub-step (C3) for one of the wireless network base stations is smaller than the predetermined loading threshold, determining whether a signal strength of said one of the wireless network base stations is greater than a predetermined signal strength threshold;
(C7) if it is determined that the signal strength is greater than the predetermined signal strength threshold in sub-step (C6), recording said one of the wireless network base stations in a priority list and the history list;
(C8) if it is determined that the signal strength is not greater than the predetermined signal strength threshold in sub-step (C6), recording said one of the wireless network base stations in the history list; and
(C9) making the electronic device stop communicating with said one of the wireless network base stations using the corresponding one of the wireless network cards and returning to step (B) to select, from among the group of wireless network base stations, another wireless network base station in place of said one of the wireless network base stations for the corresponding one of the wireless network cards.
3. The method as claimed in claim 2, wherein in step (B), if all of the wireless network base stations in the group are recorded in one of the priority list and the history list, one wireless network base station which has been recorded in the priority list the longest is selected, and if no wireless network base stations is recorded in the priority list, one wireless network base station which has been recorded in the history list the longest is selected.
4. A computer program product, comprising a non-transitory computer readable storage medium that includes program instructions, which when executed by an electronic device, cause the electronic device to perform the method according to claim 1.
5. A wireless network apparatus to be provided on an electronic device for enabling the electronic device to communicate wirelessly and simultaneously with two wireless network base stations, said wireless network apparatus comprising:
two wireless network transceiving modules capable of communicating with a corresponding wireless network base station;
a memory recorded with two medium access control (MAC) addresses;
a driver for simulating two wireless network cards respectively based on the MAC addresses; and
a processor coupled electrically to said memory and said wireless network transceiving modules, capable of converting wireless network signals that are received from said wireless network transceiving modules via said wireless network cards into digital signals acceptable by the electronic device, and further capable of converting digital signals that originate from the electronic device into wireless network signals for subsequent transmission to said wireless network transceiving modules via said wireless network cards,
wherein said processor is loaded with a first application program, which when executed, causes said processor to search a wireless network for a group of wireless network base stations, and to select, from among the group of wireless network base stations, two wireless network base stations respectively for said wireless network cards, and a second application program, which when executed, causes said processor to simultaneously communicate with the selected wireless network base stations using said wireless network cards;
wherein said first application program causes said processor to select, from among the group of wireless network base stations searched thereby, for each of said wireless network cards, a wireless network base station which is not recorded in a history list and which has a strongest signal strength, to attempt to establish connection between said wireless network card and the wireless network base station thus selected, and to determine whether the attempt to establish the connection is successful, the history list being used for recording those wireless network base stations that have been unsuccessful in establishing connection with one of said wireless network cards in the past;
wherein said second application program is executed by said processor if it is determined that the attempt is successful for both of said wireless network cards; and
wherein if it is determined that the attempt has failed, said first application program causes said processor to record the wireless network base station thus selected in the history list, and to re-select, from among the group of wireless network base stations searched thereby, a wireless network base station with the strongest signal strength and not recorded in the history list for the corresponding one of said wireless network cards,
wherein if all of the wireless network base stations in the group of wireless network base stations are recorded in the history list, two wireless network base stations which have been recorded in the history list the longest are selected for said wireless network cards.
6. The wireless network apparatus as claimed in claim 5, wherein said processor is caused by said second application program
to assign a communication loading of 50% to each of the wireless network base stations selected thereby,
to make the electronic device communicate with each of the wireless network base stations using a corresponding one of said wireless network cards with the communication loading assigned to the wireless network base station,
to record an actual communication loading and a response time for each of the wireless network base stations,
to adjust the assigned communication loading for each of the wireless network base stations if it is determined with reference to the actual communication loadings and the response times thus recorded for the wireless network base stations that adjustment of the assigned communication loading is necessary and that the actual communication loading for each of the wireless network base stations is not smaller than a predetermined loading threshold,
to determine, upon determining that the actual communication loading for one of the wireless network base stations is smaller than the predetermined loading threshold, whether a signal strength of said one of the wireless network base stations is greater than a predetermined signal strength threshold,
to record said one of the wireless network base stations in a priority list and the history list if it is determined that the signal strength is greater than the predetermined signal strength threshold,
to record said one of the wireless network base stations in the history list if it is determined that the signal strength is not greater than the predetermined signal strength threshold, and
to make the electronic device stop communicating with said one of the wireless network base stations using the corresponding one of said wireless network cards and re-execute said first application program so as for said processor to select, from among the group of wireless network base stations, another wireless network base station in place of said one of the wireless network base stations for the corresponding one of said wireless network cards.
7. The wireless network apparatus as claimed in claim 6, wherein if all of the wireless network base stations in the group are recorded in one of the priority list and the history list, one wireless network base station which has been recorded in the priority list the longest is selected by said processor, and if no wireless network base stations is recorded in the priority list, one wireless network base station which has been recorded in the history list the longest is selected by said processor.
8. The wireless network apparatus as claimed in claim 5, wherein said driver is to be installed in the electronic device for execution thereby.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for adaptively performing state-to-symbolic transformation in a canonical representation during constrained-random simulation, wherein the canonical representation is used for generating random stimulus that satisfies a set of constraints which are defined over a set of state variables and a set of random variables, the method comprising:
using a first canonical representation to generate random stimulus for the constrained-random simulation, wherein the first canonical representation is constructed using the set of random variables and a first subset of the set of state variables;
monitoring parameters associated with the constrained-random simulation to obtain monitoring data;
determining, based at least on the monitoring data, a second subset of the set of state variables which is different from the first subset of the set of state variables;
constructing a second canonical representation using the set of random variables and the second subset of the set of state variables; and
using the second canonical representation to generate random stimulus for the constrained-random simulation.
2. The method of claim 1, wherein monitoring parameters associated with the constrained-random simulation involves monitoring the number of times a state variable changes its value.
3. The method of claim 1, wherein monitoring parameters associated with the constrained-random simulation involves monitoring the number of simulation cycles a state variable’s value is equal to 0.
4. The method of claim 1, wherein monitoring parameters associated with the constrained-random simulation involves monitoring the number of simulation cycles a state variable’s value is equal to 1.
5. The method of claim 1, wherein monitoring parameters associated with the constrained-random simulation involves monitoring a canonical representation’s size.
6. The method of claim 1, wherein monitoring parameters associated with the constrained-random simulation involves monitoring how many canonical representations are being managed by a canonical representation manager.
7. The method of claim 1, wherein monitoring parameters associated with the constrained-random simulation involves monitoring correlations between two or more parameters associated with the constrained-random simulation.
8. The method of claim 1, wherein monitoring parameters associated with the constrained-random simulation involves monitoring a canonical representation’s growth rate.
9. The method of claim 1, further comprising maintaining a cache of canonical representations which are used for generating random stimulus during the constrained-random simulation.
10. The method of claim 9, wherein a cache entry in the cache points to a canonical representation, and wherein the cache entry’s tag is based at least on values of one or more state variables.
11. The method of claim 9, further comprising removing cache entries that are not expected to be used with the second canonical representation.
12. The method of claim 9, wherein monitoring parameters associated with the constrained-random simulation involves monitoring the number of cache entries in the cache.
13. The method of claim 9, wherein monitoring parameters associated with the constrained-random simulation involves monitoring the cache’s hit rate.
14. The method of claim 9, wherein monitoring parameters associated with the constrained-random simulation involves monitoring the cache’s miss rate.
15. A computer-readable storage device storing instructions that when executed by a computer cause the computer to perform a method for adaptively performing state-to-symbolic transformation in a canonical representation during constrained-random simulation, wherein the canonical representation is used for generating random stimulus that satisfies a set of constraints which are defined over a set of state variables and a set of random variables, the method comprising:
using a first canonical representation to generate random stimulus for the constrained-random simulation, wherein the first canonical representation is constructed using the set of random variables and a first subset of the set of state variables;
monitoring parameters associated with the constrained-random simulation to obtain monitoring data;
determining, based at least on the monitoring data, a second subset of the set of state variables which is different from the first subset of the set of state variables;
constructing a second canonical representation using the set of random variables and the second subset of the set of state variables; and
using the second canonical representation to generate random stimulus for the constrained-random simulation.
16. The method of claim 15, wherein monitoring parameters associated with the constrained-random simulation involves monitoring the number of times a state variable changes its value.
17. The method of claim 15, wherein monitoring parameters associated with the constrained-random simulation involves monitoring a canonical representation’s size.
18. The method of claim 15, wherein monitoring parameters associated with the constrained-random simulation involves monitoring correlations between two or more parameters associated with the constrained-random simulation.
19. The method of claim 15, further comprising maintaining a cache of canonical representations which are used for generating random stimulus during the constrained-random simulation.
20. An apparatus to adaptively perform state-to-symbolic transformation in a canonical representation during constrained-random simulation, wherein the canonical representation is used for generating random stimulus that satisfies a set of constraints which are defined over a set of state variables and a set of random variables, the apparatus comprising:
a first generating mechanism configured to use a first canonical representation to generate random stimulus for the constrained-random simulation, wherein the first canonical representation is constructed using the set of random variables and a first subset of the set of state variables;
a monitoring mechanism configured to monitor parameters associated with the constrained-random simulation to obtain monitoring data;
a transforming mechanism configured to:
determine, based at least on the monitoring data, a second subset of the set of state variables which is different from the first subset of the set of state variables; and
construct a second canonical representation using the set of random variables and the second subset of the set of state variables; and

a second generating mechanism configured to use the second canonical representation to generate random stimulus for the constrained-random simulation.

1. A computer-accessible medium which includes a computer program thereon for generating digital information associated with at least one individual, wherein when the computer program is executed by a processing arrangement, the processing arrangement is configured to provide the procedures comprising:
using the processing arrangement, generating a data structure relating to motions of a plurality of individuals; and
using the processing arrangement, generating a plurality of data elements relating to an invariance of the motions across the individuals, wherein the data elements are generated using an orthonormal decomposition of motion data relating to each of the individuals performing one or more of the motions.
2. The computer-accessible medium of claim 1, wherein the orthonormal decomposition is an n-mode singular value decomposition.
3. The computer-accessible medium of claim 1, wherein the motion data includes joint angles.
4. A computer-accessible medium which includes a computer program thereon for generating digital information associated with at least one subject, wherein when the computer program is executed by a processing arrangement, the processing arrangement is configured to provide the procedures comprising:
using the processing arrangement, generating a data structure relating to motions of a plurality of subjects and a plurality of actions; and
using the processing arrangement, generating a plurality of data elements relating to an invariance across each of the actions for at least one respective subject, wherein the data elements are generated using an orthonormal decomposition of motion data relating to each of the subjects performing one or more of the motions.
5. The computer-accessible medium of claim 4, wherein the orthonormal decomposition is an n-mode singular value decomposition.
6. The computer-accessible medium of claim 4, wherein the action data includes joint angles.
7. The computer-accessible medium of claim 1, wherein, when the computer program is executed by the processing arrangement, the processing arrangement is configured to at least one of display or store the digital information in a storage arrangement in at least one of a user-accessible format or a user-readable format, and wherein the digital information includes at least one of the data structure or the plurality of data elements.
8. The computer-accessible medium of claim 4, wherein, when the computer program is executed by the processing arrangement, the processing arrangement is configured to at least one of display or store the digital information in a storage arrangement in at least one of a user-accessible format or a user-readable format, and wherein the digital information includes at least one of the data structure or the plurality of data elements.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of controlling a clock synchronization circuit in a memory device, said method comprising:
receiving a first command to read first data from said memory device;
turning on said clock synchronization circuit to produce an output clock signal in response to said receiving said first command;
synchronizing said output clock signal with a reference clock signal;
reading said first data from said memory device after said synchronizing;
receiving a second command to read second data from said memory device after said reading said first data;
reading said second data from said memory device; and
turning off said clock synchronization circuit after said second reading.
2. The method of claim 1 further comprising delaying said turning off for a fixed period of time after said reading.
3. A method of controlling a clock synchronization circuit in a memory device, said method comprising:
receiving a command to read data from said memory device;
signaling said clock synchronization circuit to turn on in response to said receiving;
locking said clock synchronization circuit to a reference clock signal, where said clock synchronization circuit is locked with said reference clock signal in less time than a column address strobe latency of said memory device;
reading said data from said memory device after said locking; and
signaling said clock synchronization circuit to turn off in response to completion of said reading.
4. The method of claim 3 wherein said receiving comprises receiving a command at memory control logic to read data from said memory device.
5. The method of claim 3 wherein said signaling said clock synchronization circuit to turn on comprises signaling said clock synchronization circuit from memory control logic to turn on said clock synchronization circuit.
6. The method of claim 3 wherein said signaling said clock synchronization circuit to turn off comprises signaling said clock synchronization circuit from memory control logic to turn off said clock synchronization circuit.
7. A method of controlling a clock synchronization circuit in a memory device, said method comprising:
deactivating said clock synchronization circuit;
receiving a first read command;
activating said clock synchronization circuit;
reading first data in accordance with said first read command;
receiving a second read command;
reading second data in accordance with said second read command;
deactivating said clock synchronization circuit in response to completion of said second reading.
8. A memory device comprising:
a memory array operative to store data;
a controller operative to receive commands to read said stored data from said memory array;
a clock synchronization circuit operative to receive a reference clock signal and to output a synchronized clock output signal; and
a signal line coupling said controller to said clock synchronization circuit, said signal line operative to convey signals from said controller to said clock synchronization circuit to turn on said synchronization circuit in response to said controller receiving a read command and to turn off said synchronization circuit after said reading, wherein said synchronization circuit is synchronized in less time than a column address strobe latency of said memory device.
9. A memory device comprising:
a memory array having an array of control inputs operative to receive control signals and having an array of data inputs and outputs, said inputs operative to receive data and said outputs operative to output data;
IO logic having an array of control inputs operative to receive control signals, a first array of data inputs and outputs coupled to said memory array data inputs and outputs, and a second array of data inputs and outputs, said IO logic operative to receive data from said memory array and output said data from said second array, said IO logic also operative to receive data from said second array and output said data to said memory array;
control logic having an array of inputs operative to receive instructions and an array of control outputs, a portion of said outputs coupled to said memory array and a portion of said outputs coupled to said IO logic, said control logic operative to control said memory array and said IO logic;
WRITE logic having an array of data inputs operative to receive data and an array of data outputs operative to transmit data to said IO logic second array; and
READ logic having an array of data inputs operative to receive data from said IO logic second array and an array of data outputs operative to output said data, said READ logic further comprising:
clock synchronization circuit operative to control the timing of said receiving data, wherein said clock synchronization circuit is turned on and off by said control logic and wherein said synchronization circuit is synchronized in less time than a column address strobe latency of said memory device.
10. Apparatus for controlling a clock synchronization circuit in a memory device, said apparatus comprising:
means for receiving a first command to read first data from said memory device;
means for turning on said clock synchronization circuit to produce an output clock signal in response to said means for receiving said first command;
means for synchronizing said output clock signal with a reference clock signal;
means for reading said first data from said memory device after said synchronizing;
means for receiving a second command to read second data from said memory device after said reading said first data;
means for reading said second data from said memory device; and
means for turning off said clock synchronization circuit after said second reading.
11. The apparatus of claim 10 further comprising means for delaying said turning off for a fixed period of time after said reading.
12. Apparatus for controlling a clock synchronization circuit in a memory device, said apparatus comprising:
means for receiving a command to read data from said memory device;
means for signaling said clock synchronization circuit to turn on in response to said receiving;
means for locking said clock synchronization circuit to a reference clock signal, where said clock synchronization circuit is locked with said reference clock signal in less time than a column address strobe latency of said memory device;
means for reading said data from said memory device after said locking; and
means for signaling said clock synchronization circuit to turn off in response to completion of reading said data.
13. Apparatus for controlling a clock synchronization circuit in a memory device, said apparatus comprising:
means for deactivating said clock synchronization circuit;
means for receiving a first read command;
means for activating said clock synchronization circuit;
means for reading first data in accordance with said first read command;
means for receiving a second read command;
means for reading second data in accordance with said second read command; and
means for deactivating said clock synchronization circuit in response to completion of said second reading.
14. A system comprising:
a processor;
a memory controller coupled to said processor;
a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller, at least one of said DRAM chips comprising a clock synchronization circuit operative to receive a reference clock signal and to output a synchronized clock output signal;
a plurality of signal buses coupling said processor to said memory controller and said memory controller to said DRAM chips; and
a signal line coupling said memory controller to said clock synchronization circuit, said signal line conveying signals from said memory controller to said clock synchronization circuit to turn said clock synchronization circuit on in response to said controller receiving a read command and to turn said clock synchronization circuit off after said read command is processed, wherein said synchronization circuit is synchronized in less time than a column address strobe latency of said memory device.
15. The system of claim 14 wherein said at least one of said DRAM chips comprises:
a memory array having an array of control inputs operative to receive control signals and having an array of data inputs and outputs, said inputs operative to receive data and said outputs operative to output data;
IO logic having an array of control inputs operative to receive control signals, a first array of data inputs and outputs coupled to said memory array data inputs and outputs, and a second array of data inputs and outputs, said IO logic operative to receive data from said memory array and output said data from said second array, said IO logic also operative to receive data from said second array and output said data to said memory array;
WRITE logic having an array of data inputs operative to receive data and an array of data outputs operative to transmit data to said IO logic second array; and
READ logic having an array of data inputs operative to receive data from said IO logic second array and an array of data outputs operative to output said data.
16. The system of claim 14 wherein said clock synchronization circuit is a synchronous mirror delay.