Author: claimsbot

1. A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device comprising, forming a layer of a first conductive material over a substrate, depositing an insulating layer over said first conductive material and said substrate, forming an opening in said insulating layer to expose at least a portion of said first conductive material, depositing a second conductive material over said insulating layer and within said opening, removing portions of said second conductive material to form a conductive area within said opening, recessing said conductive area within said opening to a level below an upper surface of said insulating layer, forming a cap of a third conductive material over the recessed conductive area within said opening, said third conductive material selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, depositing a stack of a chalcogenide based memory cell material over said cap, and depositing a conductive material over said chalcogenide stack.
2. A method as claimed in claim 1 in which said third conductive material comprises cobalt.
3. A method as claimed in claim 1 in which said third conductive material comprises silver.
4. A method as claimed in claim 1 in which said third conductive material comprises gold.
5. A method as claimed in claim 1 in which said third conductive material comprises copper.
6. A method as claimed in claim 1 in which said third conductive material comprises nickel.
7. A method as claimed in claim 1 in which said third conductive material comprises palladium.
8. A method as claimed in claim 1 in which said third conductive material comprises platinum.
9. A method as claimed in claim 1 in which said second conductive material comprises tungsten.
10. A method as claimed in claim 1 including removing portions of said cap to planarize said cap.
11. A method as claimed in claim 1 in which said cap is formed to have a thickness of from about 200 to about 500 angstroms.
12. A method as claimed in claim 1 in which said insulating layer is selected from the group consisting of borophosphosilicate glass, tetraethylorthosilicate glass, and silicon nitride.
13. A method as claimed in claim 1 wherein said cap of third conductive material is formed by electroless plating.
14. A method as claimed in claim 13 including activating the surface of the recessed conductive area.
15. A method as claimed in claim 1 including the step of depositing a refractory metal or refractory metal nitride layer in said opening prior to the deposition of said second conductive material.
16. A method as claimed in claim 15 in which said refractory metal comprises titanium.
17. A method as claimed in claim 15 in which said refractory metal nitride comprises titanium nitride.
18. A method of funning a metal cap over a conductive interconnect in a chalcogenide-based memory device comprising, providing an insulating layer over a substrate, said insulating layer having an opening therein, said opening exposing at least a portion of a first conductive material on said substrate, depositing a second conductive material over said insulating layer and within said opening, removing portions of said second conductive material to form a conductive area within said opening, recessing said conductive area within said opening to a level below an upper surface of said insulating layer, forming a cap of a third conductive material over the recessed conductive area within said opening, said third conductive material selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, depositing a stack of a chalcogenide based memory cell material over said cap, and depositing a conductive material over said chalcogenide stark.
19. A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device comprising, providing an insulating layer over a substrate, said insulating layer having an opening therein, said opening exposing at least a portion of a first conductive material on said substrate, depositing a second conductive material over said insulating layer and within said opening, removing portions of said second conductive material to form a conductive area within said opening, recessing said conductive area within said opening to a level below an upper surface of said insulating layer, forming a cap of a cobalt metal over said recessed conductive area, depositing a stack of a chalcogenide based memory cell material over said cap, and depositing a conductive material over said chalcogenide stack.
20. A method as claimed in claim 19 including removing portions of said cap to planarize said cap.
21. A method as claimed in claim 19 wherein said cap of cobalt metal is fanned by electroless plating.
22. A method as claimed in claim 21 including the step of activating the surface of the recessed conductive area.
23. A method of forming a metal cap over a tungsten interconnect in a chalcogenide-based memory device comprising, forming a tungsten interconnect recessed within an opening in an insulating layer, and forming a metal cap over said recessed tungsten layer by electroless deposition of a metal selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof.
24. A method as claimed in claim 23 in which said metal comprises cobalt.
25. A method as claimed in claim 23 in which said metal comprises silver.
26. A method as claimed in claim 23 in which said metal comprises gold.
27. A method as claimed in claim 23 in which said metal comprises copper.
28. A method as claimed in claim 23 in which said metal comprises nickel.
29. A method as claimed in claim 23 in which said metal comprises palladium.
30. A method as claimed in claim 20 in which said metal comprises platinum.
31. A method as claimed in claim 23 including activating the surface of the recessed tungsten layer.
32. A method as claimed in claim 23 including removing portions of said cap to planarize said cap.
33. A method of forming a conductive metal interconnect for a semiconductor circuit comprising, providing a semiconductor structure having semiconductor devices formed thereon, forming an insulating layer over said semiconductor structure, forming a trench in said insulating layer down to said semiconductor structure exposing at least a portion of said semiconductor devices, substantially filling said trench wit tungsten, recessing said tungsten to a level below the upper surface of said insulating layer, and electrolessly depositing a metal cap over the recessed tungsten, said metal cap comprising a metal selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, depositing a stack of a chalcogenide based memory cell material over said cap, and depositing a conductive material over said chalcogenide stack.
34. A method as claimed in claim 33 in which said metal comprises cobalt.
35. A method as claimed in claim 33 in which said metal comprises silver.
36. A method as claimed in claim 33 in which said metal comprises gold.
37. A method as claimed in claim 33 in which said metal comprises copper.
38. A method as claimed in claim 33 in which said metal comprises nickel.
39. A method as claimed in claim 33 in which said metal comprises palladium.
40. A method as claimed in claim 33 in which said metal comprises platinum.
41. A method as claimed in claim 33 including activating the surface of the recessed tungsten prior to electrolessly depositing said metal cap.
42. A method as claimed in claim 33 including removing portions of said cap to planarize said cap.
43. A conductive interconnect for a chalcogenide-based memory device comprising, an insulating layer having an opening therein on a semiconductor substrate, a recessed tungsten layer in said opening, an electrolessly deposited metal cap on said tungsten layer, said metal cap comprising a metal selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, a stack of a chalcogenide based memory cell material over said cap, and a conductive material over said chalcogenide stack.
44. A conductive interconnect as claimed in claim 43 in which said metal comprises cobalt.
45. A conductive interconnect as claimed in claim 43 in which said metal comprises silver.
46. A conductive interconnect as claimed in claim 43 in which said metal comprises gold.
47. A conductive interconnect as claimed in claim 43 in which said metal comprises copper.
48. A conductive interconnect as claimed in claim 43 in which said metal comprises nickel.
49. A conductive interconnect as claimed in claim 43 in which said metal comprises palladium.
50. A conductive interconnect as claimed in claim 43 in which said metal comprises platinum.
51. A conductive interconnect as claimed in claim 43 in which said metal cap is planarized to be coplanar with an upper surface of said insulating layer.
52. A processor-based system comprising a processor, and a chalcogenide-based memory device coupled to said processor, said chalcogenide-based memory device comprising an insulating layer having an opening therein on a semiconductor substrate, a recessed tungsten layer in said opening, an electrolessly deposited metal cap on said tungsten layer, said metal cap comprising a metal selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, a stack of a chalcogenide based memory cell material over said cap, and a conductive material over said chalcogenide stack.
53. A system as claimed in claim 52 in which said metal comprises cobalt.
54. A system as claimed in claim 52 in which said metal comprises silver.
55. A system as claimed in claim 52 in which said metal comprises gold.
56. A system as claimed in claim 52 in which said metal comprises nickel.
57. A system as claimed in claim 52 in which said metal comprises copper.
58. A system as claimed in claim 52 in which said metal comprises palladium.
59. A system as claimed in claim 48 in which said metal comprises platinum.
60. A system as claimed in claim 52 in which said metal cap is planarized to be coplanar with an upper surface of said insulating layer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of improving discontinuous reception (DRX) functionality for a user equipment (UE) of a wireless communication system, the method comprising:
entering a DRX cycle;
executing a first equation according to a system frame number, a subframe number, and a DRX cycle parameter, for generating a first result;
executing a second equation according to a DRX start offset parameter and the DRX cycle parameter, for generating a second result; and
starting an on duration timer for monitoring a Physical Downlink Control Channel when the first result is equivalent to the second result.
2. The method of claim 1, wherein the first equation is R1=(SFN\xd710)+SubFN mod (DRX Cycle), wherein R1 indicates the first result, SFN indicates the system frame number, mod indicates modulo operation, SubFN indicates the subframe number, and DRX Cycle indicates the DRX cycle parameter.
3. The method of claim 1, wherein the second equation is R2=(DRX Start Offset) mod (DRX Cycle), wherein R2 indicates the second result, DRX Cycle indicates the DRX cycle parameter, mod indicates modulo operation, and DRX Start Offset indicates the DRX start offset parameter.
4. The method of claim 1, wherein the DRX cycle is a short DRX cycle or a long DRX cycle.
5. A communication device in a user equipment (UE) of a wireless communication system for improving discontinuous reception (DRX) functionality, the communication device comprising:
a control circuit for realizing functions of the communication device;
a processor installed in the control circuit for executing a program to control the control circuit; and
a memory installed in the control circuit coupled to the processor for storing the program;
wherein the program comprises:
entering a DRX cycle;
executing a first equation according to a system frame number, a subframe number, and a DRX cycle parameter, for generating a first result;
executing a second equation according to a DRX start offset parameter and the DRX cycle parameter, for generating a second result; and
starting an on duration timer for monitoring a Physical Downlink Control Channel when the first result is equivalent to the second result.
6. The communication device of claim 5, wherein the first equation is R1=(SFN\xd710)+SubFN mod (DRX Cycle), wherein R1 indicates the first result, SFN indicates the system frame number, mod indicates modulo operation, SubFN indicates the subframe number, and DRX Cycle indicates the DRX cycle parameter.
7. The communication device of claim 5, wherein the second equation is R2=(DRX Start Offset) mod (DRX Cycle), wherein R2 indicates the second result, DRX Cycle indicates the DRX cycle parameter, mod indicates modulo operation, and DRX Start Offset indicates the DRX start offset parameter.
8. The communication device of claim 5, wherein the DRX cycle is a short DRX cycle or a long DRX cycle.

What is claimed is:

1. A range selection control device of a shift-by-wire type automatic transmission of a motor vehicle, comprising:
a range selector that issues a range selection command signal representative of an operation range of the transmission meeting with a driver’s intention, the operating range being at least one of P(parking)-range, R(reverse)-range, N(neutral)-range and D(drive)-range;
an actuator that causes the transmission to assume a certain operation range when receiving an instruction signal; and
a control unit that issues the instruction signal by processing the range selection command signal, so that the transmission is able to assume an operation range that meets with the driver’s intention,
wherein the control unit is configured to carry out:
when the range selector fails to issue the range selection command signal, presuming a range selection intended by the driver based on a previous operation of the range selector; and
based on the presumption, causing through the actuator the transmission to actually carry out at least one of first and second range selection operations, the first range selection operation meeting with the driver’s intention and the second range selection operation being to maintain the operation range that has been kept just before the failure of the range selector.
2. A range selection control device as claimed in claim 1, in which the control unit is further configured to presume the driver’s intended range selection based on both the operation range that has been kept just before the failure of the range selector and a direction in which the range selector has been moved just before the range selector failure.
3. A range selection control device as claimed in claim 1, in which the control unit is further configured to carry out:
upon presuming that the range selection intended by the driver would be a range switch from one of P-range and N-range to D-range with the range selector being in failure, maintaining one of P-range and N-range.
4. A range selection control device as claimed in claim 1, in which the control unit is further configured to carry out:
upon presuming that the range selection intended by the driver would be a range change from D-range to one of P-range and N-range with the range selector being in failure, effecting actually the range change to one of P-range and N-range.
5. A range selection control device as claimed in claim 4, in which the control unit is further configured to carry out:
upon presuming that the range selection intended by the driver would be a range change from D-range to P-range with the range selector being in failure, determining whether or not a speed of the vehicle is within a safe parking speed range that permits a safe parking lock of the transmission;
effecting actually the range change to P-range when the vehicle speed is determined within the safe parking speed range; and
effecting actually the range change to N-range when the vehicle speed is over the safe parking speed range.
6. A range selection control device as claimed in claim 4, in which the control unit is further configured to carry out:
upon presuming that the range selection intended by the driver would be a range change from D-range to N-range with the range selector being in failure, determining whether or not a speed of the vehicle is within a lower speed range that needs no engine braking,
effecting actually the range change to N-range when the vehicle speed is determined within the lower speed range; and
maintaining D-range when the vehicle speed is determined higher than the lower speed range.
7. In a range selection control device of a shift-by-wire type automatic transmission of a motor vehicle having a range selector that issues a range selection command signal representative of an operation range of the transmission meeting with a driver’s intention, the operating range being at least one of P(parking)-range, R(reverse)-range, N(neutral)-range and D(drive)-range, and actuator that causes the transmission to assume a certain operation range when receiving an instruction signal, the instruction signal being produced by processing the range selection command signal, so that the transmission is able to assume an operation range that meets with the driver’s intention,
a method of operating the range selection control device comprising:
when the range selector fails to issue the range selection command signal, presuming a range selection intended by the driver based on a previous operation of the range selector; and
based on the presumption, causing through the actuator the transmission to actually carry out at least one of first and second range selection operations, the first range selection being meeting with the driver’s intention and the second range selection operation being to maintain the operation range that has been kept just before the failure of the range selector.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A device for a motor vehicle, comprising:
a first camera and a second camera, wherein the first camera and the second camera are configured to at least one of (a) function as a stereo camera for at least a part of a recording of each of the first and second cameras to be simultaneously of a same scene, and (b) produce different images for a same imaging stimulus; and
a processor configured to:
perform a traffic sign recognition function based on color values of a color image obtained from the first camera and without regard to output of the second camera;
perform a night vision support function based on an image obtained from the second camera and without regard to output of the first camera;
convert the color image obtained from the first camera into a grayscale image; and
perform a driver assistance function, that includes at least one of object recognition, carriageway edge recognition, and lane recognition, based on a combination of the grayscale image and the image obtained from the second camera.
2. The device as recited in claim 1, wherein the first camera and the second camera are configured to produce different images for the same imaging stimulus.
3. The device as recited in claim 1, wherein the first camera and the second camera are configured to function as the stereo camera for the at least the part of the recording of each of the first and second cameras to be simultaneously of a same scene.
4. The device as recited in claim 2, wherein a light sensitivity of the first camera is higher than a light sensitivity of the second camera.
5. The device as recited in claim 2, wherein the second camera is a black-and-white camera.
6. The device as recited in claim 2, wherein the first and second cameras differ from each other with respect to at least one of a focal width of a lens, an aperture of a lens, a coating on a lens, and an optical filter of the camera.
7. The device as recited in claim 2, wherein the first and second cameras differ with respect to at least one of an image sensor technology, a spectral sensitivity, and a spectral sensitivity of at least one color channel.
8. The device as recited in claim 2, wherein the first and second cameras differ from each other with respect to at least one of a resolution of the camera interface, at least one exposure parameter, and an image rate.
9. The device as recited in claim 2, wherein the device is configured in such a way that at least one of an image of the first camera and an image of the second camera is processed with regard to at least one image property so that images of the first and second cameras are almost the same with respect to the at least one image property after processing.
10. The device as recited in claim 9, wherein the image property is at least one of a horizontal geometric resolution of the image, a vertical geometric resolution of the image, a gray-scale value resolution of the image, and an image brightness.
11. The device as recited in claim 2, wherein the first and second cameras differ from each other with respect to at least one of a pixel size, a pixel geometry, a horizontal geometric resolution, and a vertical geometric resolution.
12. The device as recited in claim 1, wherein the second camera is not adapted for producing color images.