Author: claimsbot

What is claimed is:

1. A semiconductor epitaxial structure for a light-emitting device, comprising:
a first window layer;
a p-n junction active layer stacked on the first window layer; and
a second window layer stacked on the p-n junction active layer, and the second window layer having a textured surface, wherein the textured surface is caused by a plurality of interference lines formed by a plurality of overlaid coherent light beams.
2. The structure according to claim 1, wherein a material of the p-n junction active layer is selected from a group consisting of GaAs and AlxGa1-xAs, and a material of the first window layer and the second window layer is selected from a group consisting of GaAs and AlyGa1-yAs (0x<y), and an energy gap of the p-n junction active layer is smaller than an energy gap of the first window layer and the second window layer.
3. The structure according to claim 1, wherein a material of the p-n junction active layer is selected from a group consisting of GaInP and (AlxGa1-x)zInP, and a material of the first window layer and the second window layer is selected from a group consisting of GaInP and (AlyGa1-y)xInP (0x<y), and an energy gap of the p-n junction active layer is smaller than an energy gap of the first window layer and the second window layer.
4. The structure according to claim 1, wherein a method of forming the textured surface comprises:
forming a photoresist layer on the second window layer;
performing a first exposure process, which is to project the interference lines formed by the overlaid coherent light beams to the photoresist layer;
performing a developing process to form a textured pattern on a surface of the photoresist layer; and
performing an etching process to transfer the textured pattern of the photoresist layer to the second window layer.
5. The structure according to claim 4, wherein after performing the first exposure process, further comprises:
rotating the photoresist layer 90 degrees; and
performing a second exposure process, which is to project the interference lines formed by the overlaid coherent light beams to the photoresist layer.
6. The structure according to claim 4, wherein after performing the first exposure process, further comprises:
rotating the photoresist layer 60 degrees;
performing a second exposure process, which is to project the interference lines formed by the overlaid coherent light beams to the photoresist layer;
rotating the photoreist layer 60 degrees in the same direction continuously; and
performing a third exposure process, which is to project the interference lines formed by the overlaid coherent light beams to the photoresist layer.
7. The structure according to claim 1, wherein the overlaid coherent light beams are a plurality of overlaid coherent laser light beams.
8. The structure according to claim 1, further comprises a transparent layer over the second window layer, wherein the transparent layer is formed after transferring the textured pattern of the photoresist layer to the second window layer, and a material of the transparent layer comprises epoxy.
9. A semiconductor light-emitting device comprises:
a semiconductor substrate;
a first electrode connected to the semiconductor substrate;
a first window layer stacked on the semiconductor substrate;
a p-n junction active layer stacked on the first window layer;
a second window layer stacked on the p-n junction active layer, and the second window layer having a textured surface, wherein the textured surface of the second window layer is caused by a plurality of interference lines; and
a second electrode connected to the second window layer.
10. The device according to claim 9, wherein a material of the p-n junction active layer is selected from a group consisting of GaAs and AlxGa1-xAs, and a material of the first window layer and the second window layer is selected from a group consisting of GaAs and AlyGa1-yAs (0x<y), and an energy gap of the p-n junction active layer is smaller than an energy gap of the first window layer and the second window layer.
11. The device according to claim 9, wherein a material of the p-n junction active layer is selected from a group consisting of GaInP and (AlxGa1-x)zInP, and a material of the first window layer and the second window layer is selected from a group consisting of GaInP and (AlyGa1-y)zInP (0x<y), and an energy gap of the p-n junction active layer is smaller than an energy gap of the first window layer and the second window layer.
12. The device according to claim 9, wherein a method of forming the textured surface comprises:
forming a photoresist layer on the second window layer;
performing a first exposure process, which is to project the interference lines formed by a plurality of overlaid coherent light beams to the photoresist layer;
performing a developing process to form a textured pattern on a surface of the photoresist layer; and
performing an etching process to transfer the textured pattern of the photoresist layer to the second window layer.
13. The device according to claim 12, wherein the overlaid coherent light beams are a plurality of overlaid coherent laser light beams.
14. The device according to claim 12, wherein after performing the first exposure process, further comprises:
rotating the photoresist layer 90 degrees; and
performing a second exposure process, which is to project the interference lines formed by the overlaid coherent light beams to the photoresist layer.
15. The device according to claim 12, wherein after performing the first exposure process, further comprises:
rotating the photoresist layer 60 degrees;
performing a second exposure process, which is to project the interference lines formed by the overlaid coherent light beams to the photoresist layer; and
rotating the photoreist layer 60 degrees in the same direction continuously; and
performing a third exposure process, which is to project the interference lines formed by the overlaid coherent light beams to the photoresist layer.
16. A light-emitting device comprising:
a luminescent layer having a textured surface, wherein the textured surface of the luminescent layer is caused by at least one projection of light interference lines formed by a plurality of overlaid coherent light beams.
17. The device according to claim 16, wherein the luminescent layer includes a first window layer, an active layer, and a second window layer, and the active layer is located between the first window layer and the second window layer.
18. The device according to claim 16, wherein the overlaid coherent light beams are a plurality of overlaid coherent laser light beams.
19. The device according to claim 16, wherein a method of forming the textured surface comprises:
forming a photoresist layer on the luminescent layer;
performing a first exposure process, which is to project the light interference lines formed by the overlaid coherent light beams to the photoresist layer;
performing a developing process to form a textured pattern on a surface of the photoresist layer; and
performing an etching process to transfer the textured pattern of the photoresist layer to the second window layer.
20. The device according to claim 19, wherein after performing the first exposure process, further comprises:
rotating the photoresist layer 90 degrees; and
performing a second exposure process, which is to project the light interference lines formed by the overlaid coherent light beams to the photoresist layer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of providing a power failure warning in a storage system, comprising:
partitioning early warning power off warning (EPOW) control logic of a storage enclosure to be symmetric with a power distribution network power domain.
2. The method of claim 1, further including detecting a loss of input power.
3. The method of claim 1, further including detecting a loss of an output stage of a power supply to a virtual enclosure of the storage system.
4. The method of claim 1, further including sending an early warning power off warning (EPOW) notification signal to a processing unit responsible for an operation of the storage system, the notification signal compliant with the early power off warning (EPOW) control logic.
5. The method of claim 1, wherein the storage enclosure is configured in a just-a-bunch-of-disks (JBOD) or switched-bunch-of-disks (SBOD) topology.
6. The method of claim 1, wherein partitioning early warning power off warning (EPOW) control logic further includes dedicating a first output stage of a power supply to a first virtual storage enclosure within the storage enclosure.
7. A power failure warning system for a storage system having a plurality of storage enclosures, comprising:
a power system control module coupled to a power supply for control and management of input power to the storage system, wherein an output stage of the power supply is dedicated to a first virtual storage enclosure within one of the plurality of storage enclosures.
8. The power failure warning system of claim 7, wherein the power system control module is adapted to detect a loss of input power.
9. The power failure warning system of claim 7, wherein the power system control module is adapted to detect a loss of the output stage of the power supply.
10. The power failure warning system of claim 7, wherein the power system control module sends an early power off warning (EPOW) notification signal to a processing unit responsible for an operation of the storage system, the notification signal compliant with an early warning power off warning (EPOW) control logic.
11. The power failure warning system of claim 7, wherein the plurality of storage enclosures are configured in a just-a-bunch-of-disks (JBOD) or switched-bunch-of-disks (SBOD) topology.
12. A computer program product comprising:
a computer usable medium having computer usable program code for providing a power failure warning in a storage system, the computer program product including:
computer usable program code for partitioning early warning power off warning (EPOW) control logic of a storage enclosure to be symmetric with a power distribution network power domain.
13. The computer program product of claim 12, further including computer usable program code for detecting a loss of input power.
14. The computer program product of claim 12, further including computer usable program code for detecting a loss of an output stage of a power supply to a virtual enclosure of the storage system.
15. The computer program product of claim 12, further including computer usable program code for sending an early power off warning (EPOW) notification signal to a processing unit responsible for an operation of the storage system, the notification signal compliant with the early power off warning (EPOW) control logic.
16. The computer program product of claim 12, wherein the storage enclosure is configured in a just-a-bunch-of-disks (JBOD) or switched-bunch-of-disks (SBOD) topology.

1. A method for creating an inertial sensor aided depth map of a scene, comprising:
capturing at least a first image and a second image during movement of a device caused by a user while framing or recording the scene;
compensating for rotation between the first image and the second image;
calculating an amount of translation of the device between the first image and the second image;
calculating a pixel shift of a plurality of key points of the first image and the second image; and
estimating a depth to one or more of the plurality of key points of the first image and the second image.
2. The method of claim 1, further comprising:
identifying the plurality of key points of the first image and the second image.
3. The method of claim 1, wherein the calculating the amount of translation is based on inertial sensors of the device.
4. The method of claim 1, wherein the estimating comprises estimating an absolute depth from the device to the one or more of the plurality of key points or a relative depth of the one or more of the plurality of key points with respect to each other.
5. The method of claim 1, further comprising:
estimating an amount of rotation of the device between the first image and the second image.
6. The method of claim 5, wherein the estimating the amount of rotation is based at least in part on data from a gyroscope.
7. The method of claim 6, further comprising:
periodically calibrating the gyroscope based on periods of time during which movement of the device is below a threshold.
8. The method of claim 5, wherein the estimating the amount of rotation is based at least in part on a comparison of tracking features of each of the first image and the second image.
9. The method of claim 1, wherein the calculating the amount of translation is based at least in part on data from an accelerometer.
10. The method of claim 9, further comprising:
periodically calibrating the accelerometer based on periods of time during which the movement of the device is below a threshold.
11. The method of claim 10, wherein the periodically calibrating comprises determining when the movement of the device is below the threshold by comparing consecutive images recorded by the device.
12. The method of claim 1, wherein the calculating the amount of translation comprises integrating a gravity-compensated acceleration to obtain the amount of translation of the device between the first image and the second image.
13. The method of claim 1, wherein the capturing is performed within a given time and a given range of motion.
14. The method of claim 1, wherein the plurality of key points are a plurality of key points of each of the first image and the second image.
15. The method of claim 1, further comprising:
determining a focus setting based on the estimating.
16. The method of claim 15, wherein the focus setting is a focal length or a lens position that is adjusted based on the estimated depth.
17. The method of claim 15, wherein the determining is based on a facial recognition algorithm.
18. The method of claim 15, wherein the determining is based on a user selected region of the first image or the second image.
19. The method of claim 1, further comprising:
obtaining an orientation of the device with respect to a vertical axis using an accelerometer; and
estimating a driving current for a lens of the device based on the obtaining.
20. The method of claim 1, where the device is one of a wireless device with an integrated camera, a smartphone, a camera, or a video camcorder.
21. An apparatus for creating an inertial sensor aided depth map of a scene, comprising:
logic configured to capture at least a first image and a second image during movement of a device caused by a user while framing or recording the scene;
logic configured to compensate for rotation between the first image and the second image;
logic configured to calculate an amount of translation of the device between the first image and the second image;
logic configured to calculate a pixel shift of a plurality of key points of the first image and the second image; and
logic configured to estimate a depth to one or more of the plurality of key points of the first image and the second image.
22. The apparatus of claim 21, further comprising:
logic configured to identify the plurality of key points of the first image and the second image.
23. The apparatus of claim 21, wherein the calculating the amount of translation is based on inertial sensors of the device.
24. The apparatus of claim 21, wherein the estimating comprises estimating an absolute depth from the device to the one or more of the plurality of key points or a relative depth of the one or more of the plurality of key points with respect to each other.
25. The apparatus of claim 21, further comprising:
logic configured to estimate an amount of rotation of the device between the first image and the second image.
26. The apparatus of claim 25, wherein the logic configured to estimate the amount of rotation is based at least in part on data from a gyroscope.
27. The apparatus of claim 26, further comprising:
logic configured to periodically calibrate the gyroscope based on periods of time during which movement of the device is below a threshold.
28. The apparatus of claim 25, wherein the logic configured to estimate the amount of rotation is based at least in part on a comparison of tracking features of each of the first image and the second image.
29. The apparatus of claim 23, wherein the logic configured to calculate the amount of translation is based at least in part on data from an accelerometer.
30. The apparatus of claim 29, further comprising:
logic configured to periodically calibrate the accelerometer based on periods of time during which the movement of the device is below a threshold.
31. The apparatus of claim 30, wherein the logic configured to periodically calibrate comprises determining when the movement of the device is below the threshold by comparing consecutive images recorded by the device.
32. The apparatus of claim 23, wherein the logic configured to calculate the amount of translation comprises logic configured to integrate a gravity-compensated acceleration to obtain the amount of translation of the device between the first image and the second image.
33. The apparatus of claim 23, wherein the logic configured to capture is performed within a given time and a given range of motion.
34. The apparatus of claim 23, wherein the plurality of key points are a plurality of key points of each of the first image and the second image.
35. The apparatus of claim 23, further comprising:
logic configured to determine a focus setting based on the estimating.
36. The apparatus of claim 35, wherein the focus setting is a focal length or a lens position that is adjusted based on the estimated depth.
37. The apparatus of claim 35, wherein the determining is based on a facial recognition algorithm.
38. The apparatus of claim 35, wherein the determining is based on a user selected region of the first image or the second image.
39. The apparatus of claim 21, further comprising:
logic configured to obtain an orientation of the device with respect to a vertical axis using an accelerometer; and
logic configured to estimate a driving current for a lens of the device based on the obtaining.
40. The apparatus of claim 21, where the device is one of a wireless device with an integrated camera, a smartphone, a camera, or a video camcorder.
41. An apparatus for creating an inertial sensor aided depth map of a scene, comprising:
means for capturing at least a first image and a second image during movement of a device caused by a user while framing or recording the scene;
means for compensating for rotation between the first image and the second image;
means for calculating an amount of translation of the device between the first image and the second image;
means for calculating a pixel shift of a plurality of key points of the first image and the second image; and
means for estimating a depth to one or more of the plurality of key points of the first image and the second image.
42. A non-transitory computer-readable medium for creating an inertial sensor aided depth map of a scene, comprising:
at least one instruction to capture at least a first image and a second image during movement of a device caused by a user while framing or recording the scene;
at least one instruction to compensate for rotation between the first image and the second image;
at least one instruction to calculate an amount of translation of the device between the first image and the second image;
at least one instruction to calculate a pixel shift of a plurality of key points of the first image and the second image; and
at least one instruction to estimate a depth to one or more of the plurality of key points of the first image and the second image.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device comprising:
a light-receiving element which outputs electric charges in response to incident light; and
a drive transistor which is gated by an output of the light-receiving element to generate a source-drain current that is proportional to the incident light,
wherein the drive transistor comprises:
a first gate electrode;
a first channel region under the first gate electrode;
first and second source-drain regions which are disposed at respective ends of the first channel region, the first and second source-drain regions having a first conductivity type; and
a first channel stop region on a first side of the first channel region, the first channel stop region having a second conductivity type that is different from the first conductivity type.
2. The semiconductor device of claim 1, wherein the first and second source-drain regions each include a first dopant, and the first channel stop region includes a second dopant, wherein a concentration of the second dopant in the first channel region exceeds concentrations of the first dopants in the first and second source-drain regions.
3. The semiconductor device of claim 2, wherein the first channel stop region is between the first channel region and the light receiving element.
4. The semiconductor device of claim 1, wherein the first channel region includes a first segment under the first gate electrode that extends in a first direction and a second segment under the first gate electrode that extends in a second direction that intersects the first direction.
5. The semiconductor device of claim 1, wherein the first channel region is on a first side of the first channel stop region, and a shallow trench isolation (STI) region is on a second side of the first channel stop region that is opposite the first side of the first channel stop region.
6. The semiconductor device of claim 1, wherein a second channel stop region is on a second side of the first channel region that is opposite the first side of the first channel region.
7. The semiconductor device of claim 1, wherein a shallow trench isolation (STI) region is on a second side of the first channel region that is opposite the first side of the first channel region.
8. The semiconductor device of claim 7, wherein the drive transistor is formed in a substrate, and wherein a first depth of the first channel stop region into the substrate is smaller than a second depth of the STI region into the substrate.
9. The semiconductor device of claim 1, further comprising a select transistor which is gated by a select line to provide an output of the drive transistor to a column line, wherein the select transistor comprises:
a second gate electrode;
a second channel region under the second gate electrode;
a third source-drain region which is at a first a first end of the second channel region and that has the first conductivity type; and
a second channel stop region on a first side of the second channel region, the second channel stop region having the second conductivity type,
wherein the second source-drain region is at a second end of the second channel region that is opposite the first end of the second channel region.
10. The semiconductor device of claim 9, further comprising a shallow trench isolation (STI) or deep trench isolation (DTI) region on a second other side of the second channel region that is opposite the first side of the second channel region.
11. A semiconductor device comprising:
a first channel region in a substrate that has a first segment that extends in a first direction and a second segment that extends in a second direction that intersects the first direction;
a second channel region which is electrically connected to the first channel region, the second channel region including a segment that extends in a third direction that intersects the second direction;
a first gate electrode on the first channel region;
a second gate electrode on the second channel region, the second gate electrode separated from the first gate electrode;
a first source-drain region at a first end of the first channel region, a second source-drain at a second end of the second channel region and a third source-drain region between the first channel region and the second channel region, the first, second and third source-drain regions having a first conductivity type; and
a first channel stop region on a side of a bent portion of the first channel region that has a second conductivity type that is different from the first conductivity type.
12. The semiconductor device of claim 11, further comprising a second channel stop region which is disposed on a side of the bent portion of the second channel region and that has the second conductivity type.
13. The semiconductor device of claim 12, wherein the first channel stop region and the second channel stop region are integrally formed with each other.
14. The semiconductor device of claim 12, wherein the first channel stop region is disposed on only one side of the first channel region, and a shallow trench isolation (STI) or deep trench isolation (DTI) region is disposed on the opposite side of the first channel region.
15. The semiconductor device of claim 11, wherein the first gate electrode is larger than the first channel region and overlaps both the first channel region and the first channel stop region.
16. A semiconductor device, comprising:
a substrate having a channel region having a first conductivity type therein;
a first source-drain region at a first end of the channel region;
a second source-drain region at a second end of the channel region that is opposite the first end of the channel region; and
a first channel stop region in the substrate on a first side of the channel region that has a second conductivity type that is opposite the first conductivity type.
17. The semiconductor device of claim 16, further comprising a second channel stop region on a second side of the channel region that is opposite the first side of the channel region.
18. The semiconductor device of claim 16, wherein the channel region is a bent channel region that has a first section and a second section that are not collinear with each other.
19. The semiconductor device of claim 16, further comprising a trench isolation region on a second side of the channel region that is opposite the first side of the channel region.
20. The semiconductor device of claim 16, further comprising a trench isolation region on a second side of the channel region that is opposite the first side of the channel region, the first channel stop region and the trench isolation region defining the channel region.