1460748070-14bd802f-2601-4d7b-9be9-d24ccced38b2

1. Valve, comprising:
a base body with a passage opening;
a movable valve member for closing and opening the passage opening; and
an actuating mechanism, by means of which the valve member can be moved in order to open up the passage opening, the actuating mechanism having at least two elements in wire form made from a shape memory alloy, which elements are secured to the base body or a carrier body connected to the base body and can be shortened in the event of the temperature rising to a temperature above a threshold temperature;
wherein the elements in wire form can be shortened alternately and are operatively connected to the valve member in such a way that the valve member can be moved from a stable position on the passage opening into a stable position close to the passage opening in the event of one element being shortened on one side, and can be moved back into the stable position on the passage opening in the event of the other element being shortened on one side;
the two elements in wire form run approximately parallel to one another and perpendicular to a direction of movement of the valve member.
2. Valve according to claim 1, wherein the two elements in wire form comprise ohmic resistors capable of being heated to above the threshold temperature by the application of a current.
3. Valve according to claim 1, wherein the two elements in wire form are secured directly to the valve member.
4. Valve according to claim 3, wherein the two elements in wire form comprise ohmic resistors capable of being heated to above the threshold temperature by the application of a current.
5. Valve according to claim 1, wherein the two elements in wire form are secured to a guide element for guiding the valve member.
6. Valve according to claim 5, wherein the two elements in wire form comprise ohmic resistors capable of being heated to above the threshold temperature by the application of a current.
7. Valve according to claim 1, wherein:
the valve member is disposed at a free end of the elements in wire form.
8. Valve according claim 7, wherein the two elements in wire form are secured directly to the valve member.
9. Valve according to claim 7, wherein the two elements in wire form are secured to a guide element for guiding the valve member.
10. Valve according to claim 7, wherein the two elements in wire form comprise ohmic resistors capable of being heated to above the threshold temperature by the application of a current.
11. Valve according to claim 1, wherein the valve member is a ball.
12. Valve according to claim 11, wherein a recess is formed in the base body next to the passage opening, which recess serves as seat for the ball in the open state of the valve.
13. Valve according to claim 12, wherein the ball is connected to a coil spring, by means of which the ball is respectively pressed onto the passage opening or the recess in the base body.
14. Valve according to claim 13, wherein the two elements in wire form are disposed on either side of the coil spring approximately parallel to an axis of the coil spring.
15. Valve, comprising:
a base body with a passage opening and a recess next to the passage opening;
a movable valve member in the form of a ball for closing and opening the passage opening;
an actuating mechanism, by means of which the valve member can be moved in order to open up the passage opening, the actuating mechanism having at least two elements in wire form made from a shape memory alloy, which elements are secured to the base body or a carrier body connected to the base body and can be shortened in the event of the temperature rising to a temperature above a threshold temperature;
a coil spring connected to the ball, by means of which the ball is respectively pressed onto the passage opening or the recess in the base body, which recess serves as seat for the ball in an open state of the valve; and
wherein the elements in wire form can be shortened alternately and are operatively connected to the valve member in such a way that the valve member can be moved from a stable position on the passage opening into a stable position close to the passage opening in the event of one element being shortened on one side, and can be moved back into the stable position on the passage opening in the event of the other element being shortened on one side; and
the two elements in wire form are disposed on either side of the coil spring approximately parallel to an axis of the coil spring.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A reactor assembly, comprising:
a first block having an array of reactors defined therein; and
a second block having an array of openings defined within a surface of the second block, the array of openings aligned with openings of the array of reactors so that each reactor is associated with at least one corresponding opening defined within the surface of the second block when the surface of the second block is placed on a surface of the first block; and
a network of channels defined within the second block, the network of channels in fluid communication with a fluid source defined within the second block, wherein the network of channels is configured within the second block to provide a continuous flow of fluid through the network of channels to each of the reactors.
2. The assembly of claim 1, wherein a diameter of each opening of the array of openings is less than a diameter of each of the reactors.
3. The assembly of claim 1, further comprising a delivery line for each opening of the array of openings which are angled with respect to a normal axis of the surface of the second block.
4. (canceled)
5. (canceled)
6. The assembly of claim 1, further comprising a delivery line for each of the array of openings in the second block which are angled differently relative to each other.
7. (canceled)
8. The assembly of claim 1, further comprising an o-ring integrated into the first block.
9. The assembly of claim 1, further comprising an o-ring integrated into the second block.
10. The assembly of claim 1, further comprising a tube extending into each reactor of the array of reactors, the tubes coupled to a vacuum source.
11. A cleaner assembly for a reactor assembly having an array of reactors defined therein, comprising:
a flat plate having an upper surface and a lower surface and mountable on the reactor assembly;
an array of openings defined within the lower surface;
a network of channels defined within the flat plate, wherein the flat plate is removably sealed against a surface defining an opening for each reactor of the array of reactors; and
a fluid source coupled to the network of channels, the fluid source operable to provide a continuous flow of fluid through the network of channels to each opening of the array of openings.
12. The cleaner assembly of claim 11 wherein multiple openings of the plurality of openings provides fluid to one of the array of reactors.
13. The cleaner assembly of claim 12 wherein a delivery line for each one of the multiple openings is angled differently relative to each other.
14. The cleaner assembly of claim 12 wherein a diameter of each opening of the multiple openings is different.
15. The cleaner assembly of claim 11 wherein the lower surface of the flat plate is removably sealed against a surface defining an opening for each reactor of the array of reactors through an o-ring.
16. The cleaner assembly of claim 11 wherein a delivery line for each opening of the array of openings is angled with respect to a normal axis of the lower surface.
17. The cleaner assembly of claim 11, wherein the fluid is deionized water.
18. The cleaner assembly of claim 11, wherein each reactor of the array of reactors includes a tube extending into the reactor, the tube coupled to a vacuum source.
19. The cleaner assembly of claim 11, wherein each reactor includes an impeller.
20. The cleaner assembly of claim 19, wherein an opening of the array of openings is aligned with a corresponding opening of the impeller.

1460748063-aa3b987a-46a5-402f-b152-3f066f0198af

1. Light-scattering methacrylic polymer material comprising:
from 80 to 90 percent by weight of a methacrylic (co)polymer containing predominantly methyl methacrylate units;
from 5 to 15 percent by weight of a fire retardant compatible with the methyl methacrylate monomer and the methacrylic (co)polymer, the said fire retardant being chosen from a halogenated polyphosphonate compound, a halogenated neutral ester compound of phosphoric acid or a mixture of these two compounds; and
from 1 to 5 percent by weight of silica having an elementary particle size of less than 500 nm.
2. The polymer material of claim 1 wherein said silica has an elementary particle size of less than 100 nm.
3. The polymer material according to claim 1, characterized in that the methacrylic (co)polymer employed is a methyl methacrylate homopolymer.
4. The polymer material according to claim 1, characterized in that the halogenated polyphosphonate compound used is a chlorinated polyphosphonate.
5. The polymer material according to claim 1, characterized in that the halogenated neutral ester of phosphoric acid is tris(2-chloroisopropyl) phosphate.
6. The polymer material according to claim 1, characterized in that the silica is a precipitated silica.
7. The polymer material according to claim 1, characterized in that the silica has an elementary particle size of less than 15 nm.
8. The polymer material according to claim 7, characterized in that the silica has an elementary particle size of less than 10 nm.
9. The polymer material according to claim 1, characterized in that it comprises:
from 82 to 86 percent by weight of the methacrylic (co)polymer;
from 10 to 12 percent by weight of the fire retardant; and
from 2 to 4 percent by weight of precipitated silica.
10. The polymer material according to claim 9 characterized in that it comprises:
from 82 to 86 percent by weight of the methacrylic (co)polymer;
from 10 to 12 percent by weight of TCIP;
from 2 to 4 percent by weight of silica RP 635.
11. The polymer material according to claim 1, characterized in that it is in the form of sheets.
12. The polymer material according to claim 11, characterized in that the sheets have a thickness of between 2.5 and 8 mm.
13. The polymer material according to claim 12, characterized in that the sheets have a thickness of between 3 and 6 mm.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A power saving method applied to a CPU that is in a C3 state and a peripheral device issues a bus master request, comprising the steps of:
asserting a stop signal to prohibit said CPU from fetching instructions;
asserting a first control signal to drive said CPU leaving said C3 state; and
asserting a second control signal to drive said CPU entering a C2 state;
wherein said CPU returns to said C3 state after leaving said C2 state.
2. The method as claimed in claim 1, wherein said stop signal is asserted by a pin disposed in a system chip to a corresponding pin of said CPU.
3. The method as claimed in claim 1, further comprises a step of enabling an arbiter to transfer said bus master request to said CPU after said CPU is in C2 state.
4. The method as claimed in claim 3, wherein after said CPU completes said bus master request, further comprises:
disabling said arbiter;
asserting a third control signal to drive said CPU leaving said C2 state; and
asserting a fourth control signal to drive said CPU returning to said C3 state.
5. The method as claimed in claim 4, wherein said steps of asserting said first control signal, said second control signal, said third control signal and said fourth control signal are driven by a power management unit of a system chip.
6. The method as claimed in claim 4, wherein said CPU transits to a C0 state after leaving said C2 state, and transits to said C0 state after leaving said C3 state.
7. The method as claimed in claim 4, wherein after said CPU returns to said C3 state and said peripheral device issues an interrupt event, further comprises:
asserting said first control signal to drive said CPU leaving said C3 state and entering a C0 state;
asserting a resume signal to said CPU; and
enabling said arbiter to transfer said interrupt event to said CPU for processing.
8. The method as claimed in claim 4, wherein after said CPU returns to said C3 state and said peripheral device issues said bus master request again, asserting said first control signal and said second control signal to said CPU and enabling said arbiter to snoop said bus master request; after said bus master request is completed, disabling said arbiter and asserting said third control signal and said fourth control signal to said CPU.
9. A power saving method applied to a CPU that is in a non-snooping sleeping state and a peripheral device issues a bus master request, comprising the steps of:
asserting a stop signal to prohibit said CPU from fetching instructions;
asserting a first control signal to drive said CPU leaving said non-snooping sleeping state; and
asserting a second control signal to drive said CPU entering a snooping sleeping state that allows snooping function;
wherein said CPU transits to a normal processing state after leaving said snooping sleeping state.
10. The method as claimed in claim 9, wherein said stop signal is asserted by a pin disposed in a system chip to a corresponding pin of said CPU.
11. The method as claimed in claim 9, further comprises a step of enabling an arbiter to transfer said bus master request to said CPU after said CPU is in snooping sleeping state.
12. The method as claimed in claim 11, wherein after said CPU completes said bus master request, further comprises:
disabling said arbiter;
asserting a third control signal to drive said CPU leaving said snooping sleeping state; and
asserting a fourth control signal to drive said CPU returning to said non-snooping sleeping state.
13. The method as claimed in claim 12, wherein said CPU transits to said normal processing state after leaving said snooping sleeping state.
14. The method as claimed in claim 12, wherein said steps of asserting said first control signal, said second control signal, said third control signal and said fourth control signal are driven by a power management unit of a system chip.
15. The method as claimed in claim 12, wherein after said CPU returns to said non-snooping sleeping state and said peripheral device issues an interrupt event, further comprises:
asserting said first control signal to drive said CPU leaving said non-snooping sleeping state and entering said normal processing state;
asserting a resume signal to said CPU; and
enabling said arbiter to transfer said interrupt event to said CPU for processing.
16. The method as claimed in claim 12, wherein after said CPU returns to said non-snooping sleeping state and said peripheral device issues said bus master request again, asserting said first control signal and said second control signal to said CPU and enabling said arbiter to snoop said bus master request; after said bus master request is completed, disabling said arbiter and asserting said third control signal and said fourth control signal to said CPU.
17. The method as claimed in claim 9, wherein said non-snooping sleeping state is C3 state and said snooping sleeping state is C2 state and said normal processing state is C0 state.