Author: claimsbot

1. A brewing device for making and dispensing hot and cold beverages, the beverages made by mixing beverage ingredients supplied from a separate preparation part, the device comprising:
one or more separate dispensing points (3) for dispensing the hot and cold beverages into a container, each dispensing point having an outlet pipe (4) provided with an outlet head (5), and wherein the outlet head (5) has a mixing chamber (22a) configured for heating and foaming of milk,
pipes, hoses or channel connections provided inside the outlet pipe (4), each pipe, hose or channel connection delivering an individual beverage ingredient to the mixing chamber (22a) located in the outlet head (5), so that the individual beverage ingredients may be mixed in the mixing chamber (22a) in the outlet head (5) or the individual beverage ingredients may pass therethrough from the preparation part (1) through the outlet head (5), for dispensing into the container.
2. The brewing device according to claim 1, wherein a channel connection (16, 16a, 16b) connects a milk container (7) to the mixing chamber (22a) for delivering milk to the mixing chamber (22a), and wherein discharge openings (23) in the mixing chamber supply water vapour with or without air under pressure, to the mixing chamber (22a), for mixing with the milk delivered therein, forming a milk foam which is discharged through an outlet opening (25) in the outlet head (5).
3. The brewing device according to claim 2, further comprising a nozzle (18) located in the outlet head (5) for supplying the water vapour and to produce a negative pressure for drawing the supply of milk thereto and mixing therewith, the mixture supplied to the mixing chamber (22a).
4. The brewing device according to claim 1 wherein the pipes, hoses or channel connections located in the outlet pipe are configured for dispensing flavour additives, juices and carbonated cold water.
5. The brewing device of claim 1 further comprising a control unit which is adapted for remote control.
6. A method of cleaning the brewing device according to claim 2 comprising:
flushing the supply channels (16, 16a, 16b) and the outlet openings (23, 25) with cold water after each supply of milk or milk foam has passed therethrough.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A process for measuring enzyme activities in liquids, which comprises withdrawing enzyme inhibitors, that correspond to at least one of the enzymes in the sample, adding a substrate to the sample manipulated in this manner, so as to get cleavage products from the substrate by reacting with the enzyme, and detecting the increasing concentration per unit of time of at least one of this cleavage products during an incubation time.
The said process is characterized by withdrawing the enzyme inhibitors from the sample by means of chromatography.
2. A process according to claim 1 characterized in that the sample passes through a column (1) filled with a chromatographic carrier, that is treated with a substance capable of binding the enzyme inhibitors.
3. A process according to one of the claims 1 or 2 characterized in that the said sample is diluted with a column buffer.
4. A process according to one of the claims 1 to 3 characterized in that a suitable measuring buffer is added to the said sample in order to produce definite experimental conditions.
5. A process according to one of the claims 1 to 4 characterized in that the substrate is thermostated at least during the incubation time.
6. A process according to one of the claims 1 to 5 characterized in that the increasing concentration of one of the cleavage products of the substrate is detected by means of fluorescence measurements.
7. A device for measuring the activity of enzymes in liquids by means of a process according to one the claims 1 to 6 and 23 to 27, in particular characterized in that there is provided a column (1) filled with a chromatographic carrier treated with a substance capable of binding such enzyme inhibitors which correspond to at least one enzyme in the sample, and that there is a valvepump arrangement (7, 11, 14, 15) connected in series to the end of the column (1), so as to fill at least one test vessel with a substrat and at least a part of the sample, and that there is provided a detector for measuring the increase of the concentration per unit of time of at least one cleavage product.
8. A device according to claim 7 characterized in that the column (1) can be used repeatedly, as there is an excess of the substance corresponding to the capacity of the column (1).
9. A device according to one of the claims 7 or 8 characterized in that the column (1) is exchangeable.
10. A device according to one of the claims 7 to 9 characterized in that the sample supply tube (2) is alternatively fed out of the sample supply (3) or a reservoir (4) containing column buffer.
11. A device according to claim 10 characterized in that there is provided a control device (8) connected in series to the column (1) in order to check the purity of the column buffer discharged from the column (1).
12. A device according to claim 11 characterized in that the said control device (8) works photometrically.
13. A device according to claim 11 characterized in that the said control device is also able to measure the electrolytic conductance of liquids.
14. A device according to one of the claims 10 to 13 characterized in that there is an arrangement (9) connected in series to the column (1) for measuring the degree of dilution of the discharged sample caused by the column buffer.
15. A device according to claim 14 characterized in that the said arrangement (9) is able to measure the volume of liquids.
16. A device according to one of the claims 10 to 15 characterized in that there is a device for mixing (10) connected in series to the column (1) as to produce a homogenous mixture of the said sample with the column buffer.
17. A device according to one of the claims 7 to 16 characterized in that it enables one by means of the valvepump arrangement (11, 14, 15) to admix a measuring buffer to the said sample, and if need be, to the column buffer and to the substrate in the test tube (5) so as to produce definite experimental conditions.
18. A device according to one of the claims 7 to 17 characterized in that the detector is including a device for measuring fluorescence.
19. A device according to one of the claims 7 to 18 characterized in that there are provided means to thermostate the test tube (5).
20. A device according to one of the claims 7 to 19 characterized in that there is at least one switching valve (6) between the sample supply tube (2) and the column (1) which enables the sample alternatively to pass through the column or bypass the column in order to get into the test tube (5).
21. A device according to one of the claims 7 to 20 characterized in that at least one valve (16) is provided in order to pass a buffer as a wash liquid at least through the column (1) and the valvepump arrangement.
22. A device according to one of the claims 7 to 21 characterized in that there is provided a computer (18) in order to run and control the sample feeding and if need be, the column buffer feeding, if need be, the degree of dilution of the sample to be measured, and if need be, the mixing, charging of the test tubes (5) and the detection and evaluation of the concentration increase per unit of time of at least one of the cleavage products of the substrate.
23. A process for measuring enzyme inhibitors in liquids especially according to the claims 1 to 6, which comprises withdrawing enzymes corresponding to at least one of the enzyme inhibitors in the sample by means of chromatography and analysing the present concentration andor activity of the specific inhibitors by means of specific assays.
24. A process according to claim 23 characterized in that the sample is passed through a column (1) filled with a chromatographic carrier, that is treated with a substance capable of binding enzymes.
25. A process according to claim 23 or 24 characterized in that the manipulated sample is diluted with a suitable column buffer in a definite manner.
26. A process according to one of the claims 23 to 25 characterized in that there is added an appropriate measuring buffer to the manipulated sample as to establish definite experimental conditions.
27. A process according to one of the claims 23 to 26 characterized in that the material involved in the assay for measuring the concentration andor activity of the inhibitor is thermostated at least during the incubation time.

1. A multi-band balun comprising:
a low pass filter having a number of tuning networks to achieve tunable reactive elements within the low pass filter, each tuning network in said low pass filter including at least one switching transistor and at least one fixed reactive element, wherein an input of said low pass filter forms a first differential port of said balun; and
a high pass filter having a number of tuning networks to achieve tunable reactive elements within the high pass filter, each tuning network in said high pass filter including at least one switching transistor and at least one fixed reactive element, wherein an input of said high pass filter forms a second differential port of said balun and an output of said high pass filter is coupled to an output of said low pass filter to form a single-ended port of said balun;
wherein said low pass filter and said high pass filter are integrated on a semiconductor chip.
2. The multi-band balun of claim 1, wherein:
a gate terminal of a first switching transistor within a first tuning network of said low pass filter is coupled to receive a control voltage signal Vc to turn said first switching transistor off and on during balun operation to switch between operational bands; and
said multi-band balun further includes an inverter to invert said control voltage signal Vc and to deliver said inverted version of said signal to a source terminal of said first switching transistor to improve linearity in said multi-band balun.
3. The multi-band balun of claim 2, wherein:
a gate terminal of a second switching transistor within a second tuning network of said low pass filter is coupled to receive said inverted version of said control voltage VC; and
a source terminal of said second switching transistor within said second tuning network of said low pass filter is coupled to receive said control voltage VC to improve linear operation of said balun.
4. The multi-band balun of claim 1, wherein:
said low pass filter is arranged as a pi network having two shunt capacitive tuning networks coupled by a series inductive tuning network; and
said high pass filter is arranged as a T network having two series capacitive tuning networks with a shunt inductive tuning network there between.
5. The multi-band balun of claim 1, wherein:
a gate terminal of a first switching transistor within a first tuning network of said low pass filter is coupled to receive a control voltage signal Vc to turn said first switching transistor off and on during balun operation to switch between operational bands; and
a source terminal of said first switching transistor is coupled to receive a control voltage Vb that is approximately one-half of the supply voltage VDD of the balun to improve linear operation of the balun.
6. The multi-band balun of claim 5, further comprising:
an inverter to generate an inverted version of said control voltage VC;
wherein a gate terminal of a second switching transistor within a second tuning network of said low pass filter is coupled to receive said inverted version of said control voltage VC; and
a source terminal of said second switching transistor within said second tuning network of said low pass filter is coupled to receive said control voltage Vb to improve linear operation of said balun.
7. The multi-band balun of claim 1, wherein:
said semiconductor chip is a front end module chip.
8. The multi-band balun of claim 1, wherein:
said low pass filter includes a first capacitive tuning network to achieve a tunable capacitance therein, said first capacitive tuning network including a first branch having a first switching transistor in series with at least one DC blocking capacitor and a second branch, in parallel with said first branch, having a fixed value capacitor, wherein a parasitic off-state capacitance of said first switching transistor acts as a reactive tuning element of said low pass filter when said first switching transistor is in an off state.
9. The multi-band balun of claim 8, wherein:
said low pass filter includes a second capacitive tuning network to achieve a tunable capacitance therein, said second capacitive tuning network including a third branch having a second switching transistor in series with at least one DC blocking capacitor and a fourth branch, in parallel with said third branch, having a fixed value capacitor, wherein a parasitic off-state capacitance of said second switching transistor acts as a reactive tuning element of said low pass filter when said second switching transistor is in said off state;
wherein said first capacitive tuning network and said second capacitive tuning network are each connected in shunt with a series inductive tuning network coupled there between.
10. A system comprising:
a tunable multi-band balun that can switch between at least first and second operational frequency bands in response to a control signal;
a broadband transmitreceive (TXRX) switch coupled to a first differential port of said tunable multi-band balun; and
first and second radio frequency transmitters and first and second radio frequency receivers coupled to differential ports of said broadband TXRX switch, said first radio frequency transmitter and said first radio frequency receiver operable in a first frequency band and said second radio frequency transmitter and said second radio frequency receiver operative in a second frequency band that is different from said first frequency band, wherein said broadband TXRX switch is configured to couple one of said first radio frequency transmitter, said second radio frequency transmitter, said first radio frequency receiver, and said second radio frequency receiver through to said first differential port based on control signals.
11. The system of claim 10, wherein said tunable multi-band balun comprises:
a low pass filter having a number of tuning networks to achieve tunable reactive elements within the low pass filter, each tuning network in said low pass filter including at least one switching transistor and at least one fixed reactive element, wherein an input of said low pass filter forms a first differential port of said multi-band balun; and
a high pass filter having a number of tuning networks to achieve tunable reactive elements within the high pass filter, each tuning network in said high pass filter including at least one switching transistor and at least one fixed reactive element, wherein an input of said high pass filter forms a second differential port of said multi-band balun and an output of said high pass filter is connected to an output of said low pass filter to form a single-ended port of said multi-band balun.
12. The system of claim 11, wherein:
a gate terminal of a first switching transistor within a first tuning network of said low pass filter is coupled to receive a control voltage signal Vc to turn said first switching transistor off and on during balun operation to switch between operational frequency bands; and
said multi-band balun further includes an inverter to invert said control voltage signal Vc and to deliver said inverted signal to a source terminal of said first switching transistor to improve linearity in said multi-band balun.
13. The system of claim 12, wherein:
a gate terminal of a second switching transistor within a second tuning network of said low pass filter is coupled to receive said inverted version of said control voltage VC; and
a source terminal of said second switching transistor within said second tuning network of said low pass filter is coupled to receive said control voltage VC to improve linear operation of said balun.
14. The system of claim 11, wherein:
said low pass filter is arranged as a pi network having two shunt capacitive tuning networks coupled by a series inductive tuning network; and
said high pass filter is arranged as a T network having two series capacitive tuning networks with a shunt inductive tuning network connected there between.
15. The system of claim 11, wherein:
a gate terminal of a first switching transistor within a first tuning network of said low pass filter is coupled to receive a control voltage signal Vc to turn said first switching transistor off and on to tune said multi-band balun between multiple different frequency bands; and
a source terminal of said first switching transistor is coupled to receive a control voltage Vb that is approximately one-half of the supply voltage VDD of the balun to improve linear operation of the balun.
16. The system of claim 15, further comprising:
an inverter to generate an inverted version of said control voltage VC;
wherein a gate terminal of a second switching transistor within a second tuning network of said low pass filter is coupled to receive said inverted version of said control voltage VC; and
a source terminal of said second switching transistor within said second tuning network of said low pass filter is coupled to receive said control voltage Vb to improve linear operation of said balun.
17. The system of claim 11, wherein:
said low pass filter includes a first capacitive tuning network to achieve a tunable capacitance therein, said first capacitive tuning network including a first branch having a first switching transistor in series with at least one DC blocking capacitor and a second branch, in parallel with said first branch, having a fixed value capacitor, wherein a parasitic off-state capacitance of said first switching transistor acts as a reactive tuning element of said low pass filter when said first switching transistor is in an off state.
18. The system of claim 17, wherein:
said low pass filter includes a second capacitive tuning network to achieve a tunable capacitance therein, said second capacitive tuning network including a third branch having a second switching transistor in series with at least one DC blocking capacitor and a fourth branch, in parallel with said third branch, having a fixed value capacitor, wherein a parasitic off-state capacitance of said second switching transistor acts as a reactive tuning element of said low pass filter when said second switching transistor is in said off state;
wherein said first capacitive tuning network and said second capacitive tuning network are each connected in shunt with a series inductive tuning network coupled there between.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of modifying a data rate used in communications between a first processor and a second processor via a bus, the method comprising:
sending, from the first processor, a first handshake signal to the second processor via the bus;
receiving, by the second processor, the first handshake signal from the first processor via the bus;
sending, from the second processor, a second handshake signal to the first processor via the bus;
receiving, by the first processor, the second handshake signal from the second processor via the bus;
determining, by the first processor, based on the received second handshake signal, that the second processor is capable of transmitting data via the bus at a first modified data rate;
determining, by the second processor, based on the received first handshake signal, that the first processor is capable of transmitting data via the bus at a second modified data rate;
instructing, by the first processor, the second processor to change a data rate at which the second processor transmits data via the bus to the first modified data rate;
instructing, by the second processor, the first processor to change a data rate at which the first processor transmits data via the bus to the second modified data rate;
changing, by the first processor, based on the received instruction from the second processor, the data rate at which the first processor transmits data via the bus to the second modified data rate; and
changing, by the second processor, based on the received instruction from the first processor, the data rate at which the second processor transmits data via the bus to the first modified data rate.
2. The method of claim 1 wherein the first data rate and the second data rate are the same data rate.
3. The method of claim 1 wherein the first data rate and the second data rate are different data rates.
4. The method of claim 1 wherein the first handshake signal comprises a vendor identification.
5. The method of claim 1 wherein the determining, by the first processor, based on the received second handshake signal, that the second processor is capable of transmitting data via the bus at a first modified data rate further comprises determining, by the first processor, based on the received second handshake signal, that the second processor is also capable of transmitting data via the bus at a third modified data rate.
6. The method of claim 1 further comprising:
determining, by the first processor, that a memory is capable of receiving data at a third modified data rate; and
changing, by the first processor, a data rate at which the first processor transmits data to the memory to the third modified data rate.
7. The method of claim 1 wherein the instructing, by the first processor, the second processor to change a data rate at which the second processor transmits data via the bus is done by the first processor writing an entry into a register in the second processor.
8. The method of claim 7 wherein the register in the second processor is an extended capabilities register.
9. The method of claim 1 wherein the instructing, by the first processor, the second processor to change a data rate at which the second processor transmits data via the bus is done by the first processor instructing a Basic InputOutput System (BIOS) to have the second processor change the data rate at which the second processor transmits data via the bus.
10. The method of claim 1 wherein the first processor is a graphics processing unit and the second processor is a system platform processor.
11. The method of claim 1 wherein the first processor is a graphics processing unit and the second processor is another graphics processing unit.
12. A method of increasing a data rate used in communications between a first processor and a second processor via a bus, the method comprising:
sending, from the first processor, a request for data to the second processor via the bus;
receiving, by the second processor, the request for data from the first processor via the bus;
sending, from the second processor, the requested data to the first processor via the bus;
receiving, by the first processor, the requested data from the second processor via the bus;
determining, by the first processor, based on the received data, that the second processor is capable of transmitting data via the bus at a first increased data rate;
instructing, by the first processor, the second processor to change a data rate at which the second processor transmits data via the bus to the first increased data rate;
changing, by the first processor, the data rate at which the first processor transmits data via the bus to a second increased data rate; and
changing, by the second processor, based on the received instruction from the first processor, the data rate at which the second processor transmits data via the bus to the first increased data rate.
13. The method of claim 12 wherein the first data rate and the second data rate are the same data rate.
14. The method of claim 12 wherein the first data rate and the second data rate are different data rates.
15. The method of claim 12 wherein the requested data comprises a vendor identification.
16. The method of claim 12 further comprising:
determining, by the first processor, that a memory is capable of receiving data at a third modified data rate; and
changing, by the first processor, a data rate at which the first processor transmits data to the memory to the third modified data rate.
17. The method of claim 12 wherein the instructing, by the first processor, the second processor to change a data rate at which the second processor transmits data via the bus is done by the first processor writing an entry into a register in the second processor,
wherein the register in the second processor is an extended capabilities register.
18. The method of claim 12 wherein the instructing, by the first processor, the second processor to change a data rate at which the second processor transmits data via the bus is done by the first processor instructing a Basic InputOutput System (BIOS) to have the second processor change the data rate at which the second processor transmits data via the bus.
19. A method of modifying a data rate used in communications between a first processor and a second processor via a bus, the method comprising:
determining, by a Basic InputOutput System (BIOS), that the first processor is capable of transmitting data via the bus at a first modified data rate;
determining, by the BIOS, that the second processor is capable of transmitting data via the bus at the first modified data rate;
instructing, by the BIOS, the first processor to change a data rate at which the first processor transmits data via the bus, where the data rate is to be changed to the first modified data rate;
instructing, by the BIOS, the second processor to change a data rate at which the second processor transmits data via the bus, where the data rate is to be changed to the first modified data rate;
changing, by the first processor, based on the instruction received by the first processor from the BIOS, the data rate at which the first processor transmits data via the bus to the first modified data rate; and
changing, by the second processor, based on the instruction received by the second processor from the BIOS, the data rate at which the second processor transmits data via the bus to the first modified data rate.
20. The method of claim 19 wherein the BIOS instructs the first processor to change a data rate at which the first processor transmits data via the bus is done by writing an entry into a register in the first processor,
wherein the register in the first processor is an extended capabilities register.
21. The method of claim 19 wherein the first processor is a graphics processing unit and the second processor is another graphics processing unit.