Author: claimsbot

1. An image data processing circuit comprising:
a first circuit for calculating an average picture level value of the image data;
a multiplier for multiplying a coefficient by the image data;
a second circuit for calculating a first coefficient for the multiplier based upon the average picture level value;
a third circuit for calculating a second coefficient for the multiplier, the second coefficient being calculated so that the result of multiplying
(1) image data having a value over an input range of a circuit to which data from the multiplier is inputted, and
(2) the second coefficient falls in the input range; and
a selection circuit for selecting the coefficient to be used in the multiplier from the first coefficient calculated by the second circuit and the second coefficient calculated by the third circuit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A computing device comprising:
a camera comprising a sensor matrix to sense an image;
an orientation determiner to determine a first orientation of the camera;
a communication interface to receive a second orientation from a second computing device; and
a controller to read values from the sensor matrix in a manner so as to generate image data having the second orientation if the second orientation is different from the first orientation.
2. The computing device of claim 1, wherein reading values from the sensor matrix in the manner so as to generate image data having the second orientation comprises changing an order in which the sensor matrix is scanned.
3. The computing device of claim 1, wherein reading values from the sensor matrix in the manner so as to generate image data having the second orientation comprises changing how a location of each sensor element of the sensor matrix is represented.
4. The computing device of claim 1, wherein reading values from the sensor matrix in the manner so as to generate image data having the second orientation comprises reading values from only a subset of sensor elements of the sensor matrix.
5. The computing device of claim 1, wherein the generated image data has a different aspect ratio than would have been generated by the camera in the first orientation.
6. The computing device of claim 1, wherein the communication interface is configured to transmit the generated image data to the second computing device.
7. A method comprising:
sensing an image using an image sensor of a device;
comparing a first orientation of the image sensor to a second orientation;
if the first orientation is the same as the second orientation, reading values from the image sensor in a first manner so as to generate image data having the first orientation; and
if the first orientation differs from the second orientation, reading values from the image sensor in a second manner different from the first manner so as to generate image data having the second orientation.
8. The method of claim 7, further comprising setting the second orientation at a beginning of a communication session between the device and a second device.
9. The method of claim 8, further comprising:
receiving an indication from the second device that an orientation of a display of the second device corresponds to a third orientation; and
setting the second orientation to be equal to the third orientation.
10. The method of claim 7, wherein reading values from the image sensor in the second manner different from the first manner so as to generate image data having the second orientation comprises changing a scan direction of the image sensor.
11. The method of claim 7, wherein reading values from the image sensor in the second manner different from the first manner so as to generate image data having the second orientation comprises reading fewer values than would be read according to the first manner.
12. A non-transitory machine-readable storage medium encoded with instructions executable by a processor of a first computing device, the machine-readable medium comprising:
instructions to determine a first orientation of the first computing device using an orientation sensor;
instructions to compare the first orientation to a second orientation associated with a second computing device; and
instructions to read values from an image sensor in a manner so as to generate image data having the second orientation if the first orientation differs from the second orientation.
13. The machine-readable medium of claim 12, wherein the first orientation is associated with a first aspect ratio different from a second aspect ratio associated with the second orientation.
14. The machine-readable medium of claim 13,
wherein the image sensor comprises a matrix of sensor elements, the matrix comprising a longer dimension and a shorter dimension, and
wherein values are read from the image sensor in the manner so as to generate image data having the second orientation by reading only sensor elements that are within an area of the matrix defined by the shorter dimension and a portion of the longer dimension.
15. The machine-readable medium of claim 14, wherein the portion of the longer dimension is determined based on the shorter dimension and the second aspect ratio.

1. A nonvolatile memory device comprising:
a resistance memory cell;
a first sensing node;
a first clamping unit connected between the resistance memory cell and the first sensing node to provide a first clamping bias to the resistance memory cell, wherein the first clamping bias increases over time;
a first compensation unit providing a compensation current to the first sensing node; and
a first sense amplifier connected to the first sensing node to sense a level change of the first sensing node,
wherein in response to first data stored in the resistance memory cell, an output value of the first sense amplifier transitions to a different state after a first amount of time from a time point from where the first clamping bias starts, and
wherein in response to second data that is different from the first data stored in the resistance memory cell, the output value of the first sense amplifier transitions to the different state after a second amount of time that is different from the first amount of time from the time point from where the first clamping bias starts, and
an enable signal generation unit that generates an enable signal, wherein the enable signal generation unit includes:
a reference resistor;
a second sensing node;
a second clamping unit connected between the reference resistor and the second sensing node to provide a second clamping bias to the reference resistor;
a second compensation unit providing second compensation current to the second sensing node; and
a second sense amplifier connected to the second sensing node to sense a level change of the second sensing node,
wherein during the read period, the second clamping bias is changed over time.
2. The nonvolatile memory device of claim 1, wherein the first sense amplifier operates multiple times in response to the enable signal that becomes active multiple times during a read period.
3. The nonvolatile memory device of claim 2, further comprising an enable signal generation unit that generates the enable signal,
wherein the enable signal generation unit includes a plurality of reference resistors, and an active time point of the enable signal differs to correspond to resistance values of the reference resistors.
4. The nonvolatile memory device of claim 3, wherein the read period is a normal read period, and wherein the reference resistor includes the resistance memory cell.
5. The nonvolatile memory device of claim 3, wherein the read period is a verify read period, and wherein the reference resistor includes polysilicon.
6. The nonvolatile memory device of claim 3, wherein the enable signal generation unit comprises a plurality of reference blocks generating a plurality of reference output signals, and further comprises an operator device that receives the plurality of reference output signals and that outputs the enable signal.
7. The nonvolatile memory device of claim 1, wherein the first compensation current and the second compensation current are equal to each other.
8. The nonvolatile memory device of claim 1, wherein the first clamping bias and the second clamping bias are equal to each other.
9. The nonvolatile memory device of claim 1, wherein the first compensation unit adjusts an enable time point of the first sense amplifier through adjustment of a size of the first compensation current.
10. The nonvolatile memory device of claim 1, wherein the first clamping bias is increased in the form of a k-th order function (where, k is a natural number) over time.
11. The nonvolatile memory device of claim 1, wherein the first clamping bias is increased in a step form over time.
12. The nonvolatile memory device of claim 1, wherein a memory cell array that includes the resistance memory cell has a cross point structure.
13. A nonvolatile memory device comprising:
a resistance memory cell storing a multi-bit data;
a first sensing node;
a first clamping unit connected between the resistance memory cell and the first sensing node to provide a first clamping bias to the resistance memory cell;
a first compensation unit providing first compensation current to the first sensing node; and
a first sense amplifier connected to the first sensing node to sense a level change of the first sensing node,
wherein during a read period, the first compensation current is constant, the first clamping bias is increased over time, and the first sense amplifier is enabled multiple times to sense the level change of the first sensing node; and
an enable signal generation unit generating an enable signal, wherein the enable signal generation unit includes:
a reference resistor;
a second sensing node;
a second clamping unit connected between the reference resistor and the second sensing node to provide a second clamping bias to the reference resistor;
a second compensation unit that provides a second compensation current to the second sensing node; and
a second sense amplifier connected to the second sensing node to sense a level change of the second sensing node,
wherein during the read period, the second clamping bias is changed over time.
14. The nonvolatile memory device of claim 13, wherein the first sense amplifier operates multiple times in response to the enable signal that becomes active multiple times during a read period.
15. The nonvolatile memory device of claim 14, further comprising an enable signal generation unit generating the enable signal,
wherein the enable signal generation unit includes a plurality of reference resistors, and an active time point of the enable signal differs to correspond to resistance values of the reference resistors, and
wherein the enable signal generation unit includes a plurality of reference blocks that generate a plurality of reference output signals, and an operator device that receives the plurality of reference output signals and outputs the enable signal.
16. The nonvolatile memory device of claim 13, wherein the first compensation unit adjusts an enable time point of the first sense amplifier through adjustment of a size of the first compensation current.
17. The nonvolatile memory device of claim 13, wherein a memory cell array that includes the resistance memory cell has a cross point structure.
18. A nonvolatile memory device comprising:
a first sensing node, wherein a first protection current is input to the first sensing node and a cell current is output from the first sensing node;
a resistance memory cell through which the cell current flows;
a first sense amplifier that senses a voltage level of the first sensing node;
a second sensing node, wherein a second protection current is input to the second sensing node and a reference current is output from the second sensing node;
a reference resistor through which the reference current flows; and
a second sense amplifier that senses a voltage level of the second sensing node,
wherein in response to an output value of the second sense amplifier being transitioned in accordance with the voltage level of the second sensing node, the first sense amplifier is enabled to sense the voltage level of the first sensing node.
19. The nonvolatile memory device of claim 18, further comprising a first clamping unit connected between the first sensing node and the resistance memory cell to provide a first clamping bias to the resistance memory cell,
wherein the first clamping bias is increased over time.
20. The nonvolatile memory device of claim 18, further comprising a second clamping unit connected between the second sensing node and the reference resistor to provide a second clamping bias to the reference resistor,
wherein the second clamping bias is increased over time.
21. A nonvolatile memory device comprising:
a first clamping unit connected between a resistance memory cell and a first sensing node to provide a first clamping bias, which is increased over time, to the resistance memory cell;
a second clamping unit connected between a reference resistor and a second sensing node to provide a second clamping bias, which is increased over time, to the reference resistor;
a second sense amplifier sensing a voltage level of the second sensing node and outputting a reference output signal;
an operator device outputting an enable signal based on the reference output signal; and
a first sense amplifier sensing a voltage level of the first sensing node in response to the enable signal.
22. The nonvolatile memory device of claim 21, further comprising a compensation unit providing the same compensation current to the first sensing node and the second sensing node.
23. A nonvolatile memory device comprising:
a resistance memory cell;
first to n-th (where, n is a natural number) reference blocks that generate first to n-th reference output signals,
wherein the k-th (where 1\u2266k\u2266n) reference block includes:
a k-th reference resistor;
a k-th sensing node;
a k-th clamping unit connected between the k-th reference resistor and the k-th sensing node to provide a clamping bias, which is increased in process of time, to the k-th reference resistor;
a k-th compensation unit that provides a compensation current to the k-th sensing node; and
a k-th sense amplifier that senses a level change of the k-th sensing node and providing a k-th reference output signal; and

a main sense amplifier that is enabled n times on the basis of the first to n-th reference output signals to read a resistance value of the resistance memory cell.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-15. (canceled)
16. A network switching device for quantifying available service-level capacity of a network for projected network traffic, said network switching device comprising:
an input port and an output port;
a packet-handling module coupled to said input port and said output port; and
a test-packet module to affect presence of a test packet in said network for determining available service-level capacity of said network.
17. The network switching device of claim 16, wherein said test-packet module is either a test-packet injector or a test-packet collector.
18. The network switching device of claim 16, said test-packet module coupled to a network switching-device module, said network switching-device module comprising either an input port, an output port, or a packet-handling module; and
said packet-handling module comprising either an input buffer, a packet-forwarding module, a packet-processing engine, or an output buffer.
19. The network switching device of claim 18, wherein an input buffer is coupled with an input port, and a packet-forwarding engine is coupled to an input buffer; and
wherein said test-packet module comprises a test-packet injector, comprising a test-packet injection engine coupled with said packet-forwarding engine, and a test-packet injection buffer coupled with said input buffer;
wherein said test-packet injector is to inject at least one test packet into network traffic on said network to simulate projected network traffic without interrupting client services in said network.
20. The network switching device of claim 19, wherein said test-packet injector is to simulate said projected network traffic generated on at least one input port to said network switching device.
21. The network switching device of claim 19, wherein said test-packet injector is to incrementally increase a rate of test-packet transmission on said network to simulate increases in said projected network traffic.
22. The network switching device of claim 19, wherein said test-packet injector is remotely configurable to inject at least one test packet into said network traffic.
23. The network switching device of claim 18, wherein a test-packet module comprises a test-packet collector coupled with a packet-processing engine;
wherein said test-packet collector is to remove at least one injected test packet from network traffic before reaching a client, and to provide data quantifying available service-level capacity associated with injection of said test packet to simulate projected network traffic on said network to which said network switching device is coupled; and
wherein said test-packet collector is to provide data on performance of said network based on said injected test packet.
24. The network switching device of claim 16, further comprising:
a test vehicle comprising at least one test-packet injector to simulate said projected network traffic generated on a plurality of output ports from said network switching device.
25. The network switching device of claim 16, wherein the network switching device is a device selected from the group consisting of a network switch and a network router.
26. A packet-injection system for quantifying available service-level capacity of a network, said packet-injection system comprising:
a computer; and
a network service-level manager implemented on said computer, said network service-level manager comprising a packet-injection manager to control injected test packets in network traffic on a network;
said network including a plurality of switching devices, wherein:
at least one switching device comprises a test-packet injector to inject test packets into said network to simulate projected network traffic in response to a packet-injection command received from said packet-injection manager; and
at least one switching device comprises a test-packet collector to remove an injected test packet from network traffic before reaching a client in response to a packet-removal command received from said packet-injection manager, and to provide data to said network service-level manager quantifying available service-level capacity associated with injection of said test packet to simulate projected network traffic on said network.
27. The packet-injection system of claim 26, said network including an intermediate node to monitor an effect of an injected test packet on available service-level capacity of said network.
28. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processer, cause said processor to:
inject test packets into network traffic via a test-packet injector;
remove injected test packets from network traffic via a test-packet collector, and
analyze network performance parameters as a function of injected test packets to simulate effects of projected network traffic on available service-level capacity.
29. The medium of claim 28, further comprising instructions to:
select at least one source for injecting test packets into network traffic, and at least one sink for removing injected test packets from network traffic; and
select parameters for testing said network to analyze network performance parameters of said network.
30. The medium of claim 28, further comprising instructions to:
repeat the injection, removal, and analysis operations if based on analysis of said network performance parameters additional testing of available service-level capacity of said network is indicated.